PRELIMINARY M=it MX29F1610A/B 16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM FEATURES * 5V + 10% write and erase * Page program operation JEDEC-standard EEPROM commands - Internal address and data latches for * Endurance:100,000 cycles 128 bytes/64 words per page - Page programming time: 0.9ms typical - Byte programming time: 7us in average * Low power dissipation - 30mA typical active current - 1UA typical standby current * CMOS and TTL compatible inputs and outputs * Sector Protection - Hardware method that can protect any combination of sectors from write or erase operations. * Deep Power-Down Input - 1uA ICC typical * Industry standard surface mount packaging - 48 lead TSOP, TYPE | - 44 lead SOP * Fast access time: 90/120ns * Sector erase architecture - 16 equal sectors of 128k bytes each - Sector erase time: 1.3 s typical * Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip with Erase Suspend capability - Automatically programs and verifies data at specified addresses * Status Register feature for detection of program or erase cycle compietion * Low VCC write inhibit is equal to or less than 3.2V * Software and hardware data protection GENERAL DESCRIPTION The MX29F 1610A/B is a 16-mega bit Flash memory functionality. The command register allows for 100% TTL organized as either 1M wordx16 or 2M bytex8. The level control inputs and fixed power supply levels during MX29F 161 0A/Bincludes 16-128KB(131,072) blocks or 16- erase and programming, while maintaining maximum 64KW(65,536) blocks. MXICs Flash memories offer the EPROM compatibility. most cost-effective and reliable read/write non-volatile random access memory. The MX29F1610A/B is To allow for simple in-system reprogrammability, the packaged in 48-pin TSOP or 44-pin SOP. For 48-pin MX29F1610A/B does not require high input voltages for TSOP, CE2 and RY/BY are extra pins compared with 44- programming. Five-volt-only commands determine the pin SOP package. This is to optimize the products (such operation of the device. Reading data out of the device is as solid-state disk drives or flash memory cards) control pin similar to reading from an EPROM. budget. All the above three pins(CE2,RY/BY and PWD) plus one extra VCC pin are not provided in 44-pin SOP. It MXIC Flash technology reliably stores memory contents is designed to be reprogrammed and erased in-system or even after 100,000 cycles. The MXICs cell is designed to in-standard EPROM programmers. optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide The standard MX29F 1610A/B offers access times as fast processing and low internal electric fields for erase and as 90ns,allowing operation of high-speed microprocessors programming operations produces reliable cycling. The without wait. To eliminate bus contention, the MX29F1610A/B uses a 5V + 10% VCC supply to perform MX29F1610A/Bhas separate chip enables(CE1 andCE2), the Auto Erase and Auto Program algorithms. output enable (OE), and write enable (WE) controls. The highest degree of latch-up protection is achieved with MXICs Flash memories augment EPROM functionality MXICs proprietary non-epi process. Latch-up protection is with in-circuit electrical erasure and programming. The proved for stresses up to 100 milliamps on address and MX29F1610A/B uses a command register to manage this data pin from -1V to VCC H1V. P/N: PM0506 REV.1.4, MAY 18, 1999 26-1M=Iic MX29F1610A/B PIN CONFIGURATIONS 48 TSOP(TYPE I) (12mm x 20mm) avey 7 ay AIG 2 f 47 | ANS 3 ~ 46 Al4 4 45 ANZ 5 a AMZ 6 43; AML 7 42 AIG 8 41 Ag 9 40 ag | 10 39 AIg "1 38. We 12 MX29F1610A 37 WE 13 36 AIS 14 36 AIT 18 34 AT 16 33 AG WF 32 as | te 31 Ad 19 30 AQ 20 29 A2 at 28 Al 22 2 Ao 23 26 vec 24 25 (NORMAL TYPE) 44 SOP(500mil) We Oo 44 we At8 2 43 AIS AI? 3 42 |. AB AZ 4 41 '[ Ag AB 5 40 A10 AS 39 All AS 7 38 A12 A3 8 < 3 A13 AQ 9 2 36 AltA Al 10 35 AIS AQ 1 34 Alb CE1 2 3 BYTE GND_ a oS 32 | : GND OE 14 31 QI5/A-1 ao 15 30 Q7 as 16 29 Q14 Qi 17 28 Q6 ag 18 27 Q13 Q2 19 26 Qs Qio 20 25 Q12 as 21 24 Q4 Qi 22 23 vec BYTE of 1 48 AIG 2 47 ATS a 46 Aid 4 45 AMS 5 44 Aiz 6 43 Alt | 7 42 Alo; 8 4 Ag g 40 Ag 0 30 AIS nM wa GNo | 12 MX29F1610B 7 we | 13 36 ALS 14 Ey AN? 16 B Ay | 16 33 as | 17 a2 as | 18 31 Ad 19 x Ag 20 2a AZ at 28 Al 22 oa AO 23 26 cE a4 25 (NORMAL TYPE) Pwo PWO 48 1 RYBY BYTE BYTE | 47 co fate GND GN 46 (dal ats Q1S/A1 Q1S/A-1 45 ay Ata a7 a7 | 44 s| ats aid Qi4 43 | Al2 a6 a6 | 42 7] AN a13 aig. | 44 Bi AIO as as | 40 5 Ag are are 2 101 48 4 1! vec || veo | MX29F1610A ny Me Qn at 36 13 WE a3 03 (35 14] AlB Q10 Q10 34 15] AI? Ge g2 | 33 6] Ay Qs a9 32 TW} AG a Qt a1 18] AS 8 og | 3 19) Aa Qc Qo | 29 20) ad OE OE | 28 ai] a2 GND GND | 27 22] a1 cet cer | 26 23] Ad ce2 ce2 | 2% 24} VCC (REVERSE TYPE) PIN DESCRIPTION SYMBOL PIN NAME AO - A19 Address Input Q0-Q14 Data Input/Output QI15/A - 1 Q15(Word mode)/LSB addr.(Byte mode) CEI/CE2 Chip Enable Input PWD Deep Power- Down input OE Output Enable Input WE Write Enable Input RY/BY Ready/Busy Output WP Sector Write Protect Input BYTE Word/Byte Selection Input voc Power Supply GND Ground Pin ND enn [48 yo 1) BYTE GND GNO | 47 RE ANG Qisia1 Q1SA4 46 3 AIS a7 Q7 45 4 Ala ats a4 | 4a sf} Als a6 08 43 6) AI ais O13 42 7] AN a5 a5 44 8 Alo ai2 Ot2 40 g Ag Qs a4 539 19) AB vec vi] alg wear MX29F1610B 2] Go NC NC | 36 13) WE on att 35 14 AIS a3 Qa 134 15 | At? ot ata 33 16! AT Q2 a2 | a2 17] a6 as a9 | as 18] AS ai ay 30 s9| Ad 8 as [as 20; a3 Qo 0 | 28 ai Az OE GE | a7 agi At GND GND | 26 23 AO GND GND | 25 24: CE Note:MX29F 1610B TSOP is MXIC Mask-ROM Pin-compatible flash (REVERSE TYPE) P/N: PMO506 26-2 REV.1.4, MAY 18, 1999M> ae BLOCK DIAGRAM MX29F1610A/B DO We NT WRITE SEB | CONTROL PROGRAMERASE sure _ " . _ =) INPUT HIGH VOLTAGE _= LS viv WP LOGIC | MACHINE PWD (WSM) BYTE ____, BYTE | 7 if fb COMMAND INTERFACE, x REGISTER | | | MX2OFI610A | cr , ADDRESS 8 FLASH x o 7 | LaToH m ARRAY aisat \; | o ARRAY | _ J AND SOURCE ae HV COMMAND | Z | BUFFER | . 0 V-PASS GATE DATA , ) DECODER a SENSE | | Bon DATA "AMPLIFIER | Hy [OS COMMAND DATA LATCH PAGE | PROGRAM | DATA LATCH * || an | . | | < |! | \/ | Q0-15/A-1 < VOBUFFER = | P/N: PM0506 REV.1.4, MAY 18, 1999 26-3M=Ic MxX29F1610A/B Table1. PIN DESCRIPTIONS SYMBOL TYPE NAME AND FUNCTION AO -A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. Q0 - Q7 INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(C1R) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Q8-Qi4 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled INPUT/OUTPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB ADDRESS(BYTE = LOW) INPUT CHIP ENABLE INPUTS: Activate the devices control logic, Input buffers, decoders and sense amplifiers. With either CE1 or CE2 high, the device is de- selected and power consumption reduces to Standby level upon completion of any current program or erase operations. Both CE1,CE2 must be low to select the device. CE2 is not provided in 44-pin SOP package. All timing specifications are the same for both signals. Device selection occurs with the latter falling edge of CET or CE2. The first rising edge of CE1 or CE2 disables the device. PWD INPUT POWER-DOWN: Puts the device in deep power-down mode. PWDis active low; PWD high gates normal operation. PWD also locks out erase or program operation when active low providing data protection during power transitions. INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during a read cycle OE is active low. INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active low. OPEN DRAIN OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine(WSM). When low it indicates that the WSM is performing a erase or program operation. RY/BY high indicate that the WSM is ready for new commands, sector erase is suspended or the device is in deep power-down mode. RY/BY is always active and does not float to tristate off when the chip is deselected or data output are disabled. INPUT WRITE PROTECT: All sectors can be protected by writing a non-volatile protect- bit for each sector. When WP is low, all prottect-bits status can not be changed, i.e., the user can not execute Sector Protection and Sector Unprotect. The WP input buffer is disabled when PWD transitions low(deep power-down mode). INPUT BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address AO, then becomes the lowest order address. vec GND DEVICE POWER SUPPLY(5V+10%) GROUND P/N: PMOS06 REV.1.4, MAY 18, 1999 26-4M=I MxX29F1610A/B BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH) Mode Notes| PWD/|CE1/CE2|OE WE | AO| Ai | A9 | Q0-G7 | Q8-Q14 | Q15/A-1| RY/BY Read 1,2,7 VIH | VIL | VIL 7 VIL | VIH x x x DOUT DOUT DOUT x Output Disable 1,6,7 VIH_ | VIL y VIL | VIH | VIH x x Xx HighZ HighZ HighZ x Standby 167] VIR | vit] WH | x | x } xX} xX | X | Highz HighZ HighZ X VIH | VIL VIH | VIH Deep Power-Down| 1,3 VIL xX X Xx x X | X X ) HighZ HighZ HighZ VOH . Manufacturer ID 4,8 VIH | VIL] ViL | VIL | VIH | VIL} VIL | VID] C2H 00H 0B VOH Device ID 4,8 VIH_ | VIL; VIL | VIL |} VIH_ | VIH} VIL | VID [FAH/FBH 00H OB VOH MX29F 1610A/B | Write 1,5,6 VIH_ | VIL VIL | VIH VIL x xX Xx DIN DIN DIN x Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL) Mode Notes| PWD] CE1 CE2| OF WE | AO! At | A9 | Q0-Q7 | 8-014 | Q15/A-1| RY/BY Read 1,2,7,9| VIH | VIL | VIL | VIL] VIH x Xx Xx DOUT HighZ VIL/VIH x Output Disable 1,6,7 VIH_ | VIL | VIL [| VIH |} VIH x xX x HighZ HighZ x X Standby 1,6,7 VIH | VIL | VIH | X x x x x HighZ HighZ x x VIH | VIL VIH | VIH Deep Power-Down| 1,3 VIL X Xx xX | X X | X X HighZ HighZ X VOH Manufacturer ID 4,8 VIH_ | ViL | ViL | VIL] VIH | VIL | VIL | VID C2H HighZ VIL VOH Device ID 48 VIH_ | VIL | VIL | VIL | VIH_ | VIH-| VIL | VID | FAH/FBH} HighZ VIL VOH MX29F 1610A/B Write 1,56 VIH_ | VIL | VIL | VIK| VIL Xx x x DIN HighZ VIL/VIH x NOTES : 1.X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH. _ 2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH if it is tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3.PWD at GND + 0.2V ensures the lowest deep power-down current. 4. AO and Af at VIL provide manufacturer !D codes. AQ at VIH and Aj at VIL provide device ID codes. AQ at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4) 5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence. __ 6.While the WSM is running. RY/BY in Level-Mode stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation. 8. VID = 11.5V- 12.5V. 9. Q15/A-1 = VIL, QO - Q7 =DO-D7 out . Q15/A-1 = VIH, QO - Q7 = D8 -D15 out. P/N: PMOSO6 REV.1.4, MAY 18, 1999 26-5M=Ic WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. Inthe event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control TABLE 3. COMMAND DEFINITIONS MxX29F1610A/B the program sequences and the CIR will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CIR to respond to its full command set. The CIR stays at read status register mode until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash family command. Command Read/ | Silicon [| Page/Byte} Chip | Sector] Erase | Erase Read Clear Sequence Reset | ID Read | Program | Erase | Erase | Suspend{Resume | Status Reg. J Status Reg, Bus Write 4 4 4 6 6 1 1 4 3 Cycles Req'd First Bus Addr [5555H | 5555H 5555H | 5555H | S5S55H~ XXXX J XXXX 5555H 5555H Write Cycle ata [| AAH [ AAH AAH AAH AAH BOH DOH AAH AAH Second Bus Addr [2AAAH# 2AAAH 2AAAH [2AAAH | 2AAAH 2AAAH 2AAAH Write Cycle Data [| 55H 55H 55H 55H 55H 55H 55H Third Bus Addr [5555H | 5555H 5555H | 5555H | 5555H 5555H 5555H Write Cycle Data | FOH 90H AOH 80H 80H 70H 50H Fourth Bus Addr | RA_ | 00H/01H PA 5555H | 5555H X ReadMrite Cycle {Data | RD | C2H/FAH PD AAH AAH SRD (FBH) Fifth Bus Addr 2AAAH | 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr 5555H SA Write Cycle Data 10H 30H P/N: PM0506 REV.1.4,MAY 18, 1999 26-6M=Ic MX29F1610A/B COMMAND DEFINITIONS(continue Table 3.) Command Sector Sector Verify Sector Sequence Protection | Unprotect Protect Bus Write 6 6 4 Cycles Req'd First Bus Addr 5555H 5555H 5555H Write Cycle Data AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H Third Bus Addr 5555H 5555H 5555H Write Cycle Data 60H 60H 90H Fourth Bus Addr 5555H 5555H * Read/Write Cycle} Data AAH AAH C2H* Fifth Bus Addr 2AAAH 2AAAH Write Cycle Data 55H 55H Sixth Bus Addr SA** SA** Write Cycle Data 20H 40H Notes: 1.Address bit A15 -- A19 = X = Don't care for ail address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AO to A14. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory location to be read. __ PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A16 -- A19 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. SRD = Data read from status register. 5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care. * Refer to Table 4, Figure 12. 6.The details of sector protection/unprotect algorithm are shown in Fig.10 and Fig.11. P/N: PM0506 REV.1.4,MAY 18, 1999 26-7DEVICE OPERATION SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. All addresses are dont cares except AO and A1. MxX29F1610A/B The manufacturer and device codes may also be read via the command register, for instances when the MX29F1610A/B is erased or programmed in a system without access to high voltage on the AQ pin. The command sequence is illustrated in Table 3. Byte 0 (AO=VIL) represents the manfacturers code (MXIC=C2H) and byte 1 (AQ=VIH) the device identifier code(Mx29F1610A=FAH/MX29F 1610B=FBh). The Silicon ID Read mode will be terminated after the following write command cycle. Table 4. MX29F 1610 Silion ID Codes and Verify Sector Protect Code Type Aig Aig |Ayz |Ayg| A, | Ap |Code(HEX)/DQ, DQ, |DQ, |DQ,|/DQ,/DQ, |DQ, Da, Manufacturer Code xX | X |X | X IVILIVIL C2H* 1 1 0 0) 0 | 0 1 0 MX29F1610A/B Device Code} X | X | X | X |VILIVIH) FAH/FBH 1 1 1 1 1 0 1 | 0/4 Verify Sector Protect Sector Address*** | VIH! VIL C2H** 1 1 0 0 0 0 1 0 * MX29F1610A/B Manufacturer Code = C2H, Device Code = FAH/FBH when BYTE = VIL MX29F1610A/B Manufacturer Code = 00C2H, Device Code = OOFAH/OOFBH when BYTE = VIH ** Outputs C2H at protected sector address, 00H at unprotected scetor address. *** All sectors have protect-bit feature. Sector address = (A19, A18,A17,A16) P/N: PM0506 REV.1.4, MAY 18, 1999 26-8M=ic READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabied for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29F1610A/B is accessed like an EPROM. When CE and OF are low and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever GE or OE is high. This dual line control gives designers flexibility in preventing bus contention. CE stands for the combination of CE1 and CE2 in MX29F1610A 48-pin TSOP package. CE and stands for CE in 44-pin SOP package. Note that the read/reset command is not valid when program or erase is in progress. PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two unlock" write cycles. These are followed by writing the page program command- AOH. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a byte (word) load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below. MxX29F1610A/B BYTE-WIDE LOAD/WORD-WIDE LOAD Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes for data protection. A byte load(word load) is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE E high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide loadis determined(Byte =ViLor VIHis latched) on the falling edge of the WE{or CE) during the 3rd command write cycle. PROGRAM Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. Ifa byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte(word) that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the device, successive bytes(words) are entered in the same manner. The time between byte (word) loads must be less than 30us otherwise the load period could be teminated. A6 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A- 1 to AS specify the byte address within the page, AO to A5 specify the word address withih the page. The byte (word) may be loaded in any order; sequential loading is not required. If a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is 1 at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 1,7,8) P/N: PMO506 REV.1.4, MAY 18,1999 26-9M=Ic CHIP ERASE Chip erase is a six-bus cycle operation. There are two unlock write cycles. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the chip erase command-10H. Chip erase does not require the user to program the device prior to erase. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 2,7,9) Table 5. MX29F 1610 Sector Address Table (Byte-Wide Mode) A19|A18/ A17|A16 | Address Range[A19, -1] SAO | 0 0, 0 0 000000H--01FFFFH SA1 0;o]90 1 020000H--03FFFFH SA2 | 0 0 1 0 040000H--OSFFFFH SA3 / 0/0 1 1 O60000H--07FFFFH SA4 | 0 1 0 0 080000H--O9FFFFH SA15| 1 1 1 1 1E0000H--1 FFFFFH SECTOR ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set- up command-80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. MX29F1610A/B Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins on the rising edge ofthe last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. (Refer to table 3, 6 and Figure 3,4,7,9)) ERASE SUSPEND This command only has meaning while the the WSM is executing SECTOR erase operation, andtherefore will only be responded to during SECTOR erase operation. After this command has been executed, the CIR will initiate the WSM to suspend erase operations, and then return to Read Status Register mode. The WSM will set the DQ6 bit to a "1". Once the WSM has reached the Suspend state,the WSM will set the DQ7 bit to a"1", At this time, WSM allows the CIR to respond to the Read Array, Read Status Register and Erase Resume commands only. In this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins, with the exclusion of PWD. PWD low will immediately shut down the WSM and the remainder of the chip. ERASE RESUME This command will cause the CIR to clear the suspend state and set the DQ6 to a0, but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. P/N: PMO506 REV.1.4, MAY 18, 1999 26-10READ STATUS REGISTER The MXICs16 Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status commandto the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on DQ2 - DQ7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode forthe MX29F 1610. Inthe word-wide mode the upper byte, DQ(8:15) is set to OOH during a Read Status command. In the byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains the low order address function. DQO- DQ?1 is set to OH in either x8 or x16 mode. It should be noted that the contents of the status register are latched on the falling edge of OE or CE whichever occurs fast in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fail or Program fail status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F1610A/B automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The internal state machine is set for reading array data upon device power-up, or after deep power-down mode. MX29F1610A/8 CLEAR STATUS REGISTER The Eraes fail status bit (DQ5) and Program fail status bit (DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several pages or erasing multiple blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase} fail bit happens, the program (erase) operation can not be performed further. The program(erase) fail bit must be reset by system software before further page program or sector (chip) erase are attempted. To clear the status register, the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID. P/N: PMO506 REV.1.4, MAY 18, 1999 26-11Mic MX29F1610A/B TABLE 6. MX29F1610 STATUS REGISTER STATUS NOTES | DQ7 | DQ6 DQ5 | DQ4 | DAs IN PROGRESS PROGRAM 1,2 0 0 0 0 0 ERASE 1,3 0 0 0 0 0 SUSPEND (NOT COMPLETE) 1.4 0 0 0 0 0 (COMPLETE) 1 | + | 0 | 0 | 0 COMPLETE PROGRAM 1,2 1 0) 0 0 0 ERASE 1,3 1 0 0 0 0 FAIL PROGRAM 1,5 1 0 0 1 0 ERASE 1,5 1 0 1 0 0 AFTER CLEARING STATUS REGISTER 1 0 0 0 0 NOTES: 1. DQ7 : WRITE STATE MACHINE STATUS 1 = READY, 0 = BUSY DQ6 : ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DQ5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DQ4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3=0 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. 2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode. 3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode. 4. SUSPEND STATUS is for Sector Erase mode . 5. FAIL STATUS bit(DQ4 or DQS5) is provided during Page Program or Sector/Chip Erase modes respectively. 6. DQ3 = 0 ail the time. PIN: PMOSO6 REV.1.4, MAY 18, 1999 26-12M=Ic HARDWARE SECTOR PROTECTION The MX29F1610A/B features sector protection. This feature will disable both program and erase operations. The sector protection feature is enabled using system software by the user(Refer to table 3). The device is shipped with all sectors unprotected. Altematively, MXIC may protect all sectors in the factory prior to shipping the device. SECTOR PROTECTION To activate this mode, a six-bus cycle operation is required. There are two unlock write cycles. These are followed by writing the set-up command. Two more unlock write cycles are then followed by the Lock Sector command - 20H. Sector address is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the tising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is 1 at which time the device stays at the read status register mode. The users have to write Verify Sector Protect command to verify protect status after executing Sector Protector. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence (Refer to table 3,6 and Figure 10,12). VERIFY SECTOR PROTECT To verify the Protect status, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address XXXOH retrieves the Manufacturer code of C2H. A read cycle from XXX1H returns the Device code FAH/FBH. A read cycle from appropriate address returns information as to which sectors are protected. To terminate the operation, itis necessary to write the read/reset command sequence into the CIR. (Refer to table 3,4 and Figure 12) A few retries are required if Protect status can not be verified successfully after each operation. MX29F1610A/B SECTOR UNPROTECT Itis also possible to unprotect the sector , same as the first five write command cycles in activating sector protection mode followed by the Unprotect Sector command - 40H, the automatic Unprotect operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ/7 is 1 at which time the device stays at the read status register mode.(Refer to table 3,6 and Figure 11,12) The users have to write Verify Sector Protect command to verify protect status after executing Sector Unprotect. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. Either Protect or Unprotect sector mode is accomplished by keeping WP high, i.e. protect-bit status can only be changed with a valid command sequence and WP at high. Protect- bit status will not be changed during chip/sector erase operations. Only unprotected sectors can be programmed or erased regardless of the WP pin. DEEP POWER-DOWN MODE The MXIC's16 Mbit flash family supports a typical !CC of 1uA in deep power-down mode. One of the target markets for these devices is in protable equipment where the power consumption of the machine is of prime importance. When PWD is a logic low (GND + 0.2V), all circuits are turned off and the device typically draws 1uA of ICC current. During erase or program modes, PWD low will abort either erase of program operation. The contents of the memory are no longer valid as the data has been corrupted by the PWD function. PWD transitions to VIL or turning power off to the device will clear the status register. PWD pin is not provided in 44-pin SOP package. P/N: PMOSO6 REV.1.4, MAY 18, 1999 26-13MX29F1610A/B RY/BY PIN AND PROGRAM/ERASE POLLING RY/BY is adedicated, open-drain page program and sector erase completion. It transitions to VOL after a program or erase command sequence is written to the MX29F 1610A/ B, and returns to VCC when the WSM has finished executing the internal algorithm. Since RY/BY is an open- drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. RY/BY can be connected to the interrupt input of the system CPU or controller. it is active at all times, not tristated if the CE or OE inputs are brought to VIH. RY/BY is also VCC when the device is in erase suspend or deep power-downmodes. RY/BY pin is not provided in 44-pin SOP package. DATA PROTECTION The MX29F 161 0A/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 10ns (typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. P/N: PMO506 REV.1.4, MAY 18, 1999 26-14MIC MX29F1610A/B Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART a START Y Write Data AAH Address 5555H Y Write Data 55H Address 2AAAH Y Write Data AOH Address 5555H Y Write Program Data/Address at Y Loading End? YES Wait 100us y Read Status Register y a YES y NO YES Page Program Completed Program Error ' z To Continue Other Operations, Oo Ciear S.A. Mode First Program another page? NO y Operation Done, Device Stays At Read S.R. Mode Note : S.R. Stands for Status Register P/N: PMOS06 REV.1.4, MAY 18, 1999 26-15M=Ii MX29F1610A/B Figure 2. AUTOMATIC CHIP ERASE FLOW CHART ! Write Data AAH Address 5555H ' | Write Data 55H Address 2AAAH + Write Data 80H Address 5555H y Write Data AAH Address 5555H _V Write Data 55H Address 2AAAH Y Write Data 10H Address 5555H | Y coc Read Status Register y To Execute Suspend Mode ? Erase Suspend Flow (Figure 4.) YES NO YES oan Y Operation Dane, To Continue Other Device Stays at Operations, Do Clear Read S.A. Mode S.R. Mode First P/N: PM0506 REV.1.4, MAY 18, 1999 26-16MM G MX29F1610A/B Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART V Write Data AAH Address 5555H ' Write Data 55H Address 2AAAH Y Write Data 80H Address 5555H y Write Data AAH Address 55551 Write Data 55H Address 2AAAH J Write Data 30H Sector Address ' Read Status Register To Execute YES Suspend Erase ? Erase Suspend Fiow (Figure 4.} YES NO YES Sector Erase Completed Erase Error _v Operation Done, To Continue Other Device Stays at Operations, Do Clear Read S.R. Mode S.A. Mode First P/N: PMO506 REV.1.4, MAY 18, 1999 26-17Mic MX29F1610A/B Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART START le Write Data BOH Address xxxxH y Read Status Register NO yj YES ! . z YES y Erase Suspend y Write Data AAH Address 5555H Write Data 55H Address 2AAAH ee | Y Write Data FOH Address 5555H ! Read Array Reading End ? YES J Write Data DOH Address xxxxH | Continue Erase NO YES Erase has completed Operation Done, Device Stays at Read 8,R, Mode Erase Error y To Continue Other Operations, Do Clear S.R. Mode First P/N: PMOSO6 26-18 REV.1.4, MAY 18, 1999M=Ic MX29F1610A/B ELECTRICAL SPECIFICATIONS NOTICE: Stresses greater than those listed under ABSOLUTE ABSOLUTE MAXIMUM RATINGS MAXIMUM RATINGS may cause permanent damage to the RATING VALUE device. This is stress rating only and functional operational Ambient Operating Temperature 0C to 70C sections of this specification is not implied. Exposure to . absolute maximum rating conditions for extended period may Storage Temperature -65C to 125C affect reliability. Applied Input Voltage -0.5V to 7.0V NOTICE: . Specifications contained within the following tables are subject Applied Output Voltage -0.5V to 7.0V to change. VCC to Ground Potential -0.5V to 7.0V AQ -0.5V to 13.5V CAPACITANCE TA = 25 C, f= 1.0 MHz SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = OV CIN2 Control Pin Input Capacitance - __ 16 pF VIN=0V COUT Output Capacitance 16 pF VOUT = 0V SWITCHING TEST CIRCUITS DEVICE 1.6K ohm nt AAG UNDER sg TEST | CL Vv v1 DIODES = IN3064 1.2K ohm | OR EQUIVALENT O +5V CL = 100 pF Including jig capacitance SWITCHING TEST WAVEFORMS 2.4V TEST POINTS 0.45V INPUT OUTPUT AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns. P/N: PM0506 REV.1.4, MAY 18,1999 26-19M=ic DC CHARACTERISTICS = 0C to 70C, VCC = 5V+10% MX29F1610A/B SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load 1 +10 uA VCC = VCC Max Current VIN = VCC or GND ILO Output Leakage 1 +10 uA VCC = VCC Max Current VIN = VCC or GND 1SB1 VCC Standby 1 1 100 uA VCC = VCC Max Current(CMOS) CE1, CE2, PWD = VCC + 0.2V ISB2 VCC Standby 2 4 mA VCC = VCC Max Current(TTL) CE1, CE2, PWD = VIH IiDP VCC Deep 1 1 20 uA PWD = GND + 0.2V Power-Down Current iCC1 VCC Read 1 50 60 mA VCC = VCC Max_ Current CMOS: CE1, CE2=GND+ 0.2V BYTE = GND + 0.2V or VCC + 0.2V Inputs = GND + 0.2V or VCC + 0.2V TIL: CE1, CE2 = VIL, BYTE = ViL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT =0 mA ICC2 VCC Read 1 30 35 mA VCC = VCC Max, Current CMOS: CE1, CE2 =GND + 0.2V BYTE = VCC + 0.2V or GND + 0.2V Inputs = GND + 0.2V or VCC + 0.2V TTL: CE1, CE2 = VIL, BYTE = VIH or VIL Inputs = VIL or VIH, f = 5MHz, IOUT = OmA ICC3 VCC Erase 1,2 5 10 mA CE1, CE2 = VIH Suspend Current BLock Erase Suspended Icc4 VCC Program 1 30 50 mA Program in Progress Current Iccs VCC Erase Current 1 30 50 mA Erase in Progress VIL Input Low Voltage 3 -0.3 0.8 Vv ViH input High Voltage 4 2.4 VCC+10.3 OV VOL Output Low Voltage 0.45 v IOL = 2.1mA VOH Output High Voltage 2.4 Vv IOH = -2mA P/N: PM0506 REV.1.4, MAY 18, 1999 26-20M=Ii MxX29F1610A/B DC CHARACTERISTICS = 0C to 70C, VCC = 5V410%(CONTINUE P.21) ~ NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25C. These currents are valid for all product versions (package and speeds). 2. 1CC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC3 and ICC 1/2. 3. VIL min. = -1.0V for pulse width is equal to or less than 50ns. VIL min. = -2.0V for pulse width is equal to or less than 20ns. 4. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS READ OPERATIONS 29F1610A/B-70 29F1610A/B-90 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 70 90 ns CE=OE=VIL - 1CE CE to Output Delay Oe 70 : 90 ns OE=VIL 10E OE to Output Delay 40 =t<<S ttt DE OE High to Output Delay 0 ; 35 0 35 ns CE=VIL 10H : Address to Output hold oO! ge : - ns CE-OE=VIL tBACC BYTE to Output Delay 70 90 ns CE= OE=VIL tBHZ BYTE Low to Output in High Z 35 50 ns CE=VIL tDPR Deep Power-Down Recovery 0 0 ns TEST CONDITIONS: NOTE: * Input pulse levels: 0.45V/2.4V 1. tDF is defined as the time at which the output achieves the + Input rise and fall times: 10ns open circuit condition and data is no longer driven. * Output load: 1 TTL gate+100pF(Including scope and jig) + Reference leveis for measuring timing: 0.8V, 2.0V P/N: PMO506 REV.1.4, MAY 18, 1999 26-21Mic Figure 5. READ TIMING WAVEFORMS MX29F1610A/B Standby Device and Outputs Enabled Standby Vec Power-up address selection Data valid Veco Power-down ADDRESSES ADDRESSES STABLE CE (1) vs fo Ne Jo = VIL . OE 1 iF - VIH WE VIL ~~ OF op ~ (CE VOH - 10H ~ HIGH Z f / . XY NV \ HIGH Z DATA OUT VoL \ Data out valid fii ~ tacc ~ 5.0V VCC LL GND ~t tDPR ~ VIH PWD VIL / NOTE: 1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or CE2 going High. 2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode); dynamic switching of BYTE pin is not recommended. P/N: PMO506 26-22 REV.1.4, MAY 18, 1999MM] GS MX29F1610A/B a Figure 6. BYTE TIMING WAVEFORMS vcc Device and Outputs Enable Standby Power-up Standby address selection Data vatid Vcc Power-down VIH 7 ADDRESSES vn ADDRESSES STABLE VIH cea) fo Nf = VIL OE tDF ~- - VIH _ ~ WE VIL 10E ~~ tCE - we tOH VOH HIGHZ Lili paacumn SSC _HIGHZ DATAOUT Data Output VOL WAA tACC. ~ VOH | : vec vot {DPR - - ee VIH PWD VIL NOTE: 1.CE is defined as the latter of CE1 ar CE2 going Low or the first of CE1 or CE2 going High. 2.For real world application, BYTE pin should be either static high(word mode) or static low{byte mode); dynamic switching of BYTE pin is not recommended. P/N: PMGS506 REV.1.4, MAY 18, 1999 26-23M>= =Ic MX29F1610A/B AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29F1610A/B-70 29F1610A/B-90 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. UNIT tWC Write Cycle Time 90 120 ns tAS Address Setup Time 0 0 ns tAH Address Hold Time 50 60 ns tDS Data Setup Time 50 60 ns tDH Data Hold Time 0 0 ns tOES Output Enable Setup Time 0 0 ns tCES CE Setup Time 0 0 ns tGHWL Read Recover TimeBefore Write 0 0 tcS CE Setup Time 0 0 ns tCH CE Hold Time 0 0 ns twP Write Pulse Width 50 60 ns tWPH Write Pulse Width High 30 50 ns tBALC Byte(Word) Address Load Cycle 0.3 30 0.3 30 us tBAL Byte(Word) Address Load Time 100 100 us tSRA Status Register Access Time 70 90 ns tCESR CE Setup before S.R. Read 70 70 ns tWHRL WE High to RY/BY Going Low 90 90 ns tWHRLP WE High to RY/BY Going Low 90 90 us (in Page Program mode) tPHWL PWD High Recovery to WE Going Low 0 0 ns tVCS VCC Setup Time 50 50 us P/N: PMOS06 REV.1.4, MAY 18, 1999 26-24M=Ii MxX29F1610A/B Figure 7, COMMAND WRITE TIMING WAVEFORMS CE tCH - 1OES a r ts OE ~ ~ we ~~ - WE ~~ 'GHWL ~ tWPH ~~ - twP _ - =z MS taH - ADDRESSES VALID tDS tOH ~~ - ~~ - (D/Q) ' voc vcs =_ PE PWD - ~ tPHWL NOTE: 1.BYTE pin is treated as Address pin. All timing specifications for BYTE pin are the same as those for address pin. 2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application, BYTE pin should be either static high(word mode) or static low(byte mode). | P/N: PMOS06 REV.1.4, MAY 18, 1999 26-25M=Ie MX29F1610A/B Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS Word offset AO~AS 55H Address A-1 (byte mode only) A6~A14 A15~A19 Page Address two ~ - 1BALG tBAL - =a > <? - = VI NS NS NS NS NS NS twP(WPH _ > ~<a a tCES _ OE _/ Vf tWHRLP - -_ RY/BY PS ton - 1 tSRA = DATA AAH 55H AQH Write Last Write SRD Data iPHWL ~ ~- PWD NOTE: 1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation. P/N: PM0506 REV.1.4, MAY 18, 1999 26-26M=]| G MX29F1610A/B , a Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS AQ~A14 A16~A19 twP tWPH <_ > NS NS NS NS NS NS a WC - tCES oc 8 860__/ \ fo tWHRL _ => RY/BY 1DS 10H ~ - ~ {SRA ~~ DATA AAH 55H 80H AAH (30H/10H) SRD tPHWL ~~ PWD NOTES: 1.CE# is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2."*" means "don't care in this diagram. 3."SA" means "Sector Adddress. P/N: PMOS06 REV.1.4, MAY 18, 1999 26-27M=]i MX29F1610A/B Figure 10. SECTOR PROTECTION ALGORITHM (Only one sector can be protected at one time) Sector protect Flow N=N+1 Y Verify Sector NO Protect/Unprotect Flow ! ! ' NO YES t YES ' Write RESET Command Device Failed Y Sector Unprotect Complete and Device Return to Read Mode NOTE 1 : Address means A14-A0 for word and byte mode NOTE 2 : Sector Address=(A19,A18,A17,A16) NOTE 3 : Sector protection will be disabled when WP is low P/N: PMOS06 REV.1.4, MAY 18, 1999 26-28Me 7 ns Sector Protect Flow START ' Write Command Address=5555H Data=AAH ' Write Command Address=2AAAH Data=55H Y Write Command Address=5555H Data=60H Y Write Command Addrass=5555H Data=AAH y Write Command Address=2AAAH Data=55H Y Write Command Address=Sector Address;Data=20H y Read Status at Register ' NO ' YES END MxXxX29F1610A/B Verify Sector Protect/Unprotect Flow START ' Write Command Address=5555H Data=AAH ' Write Command Address=24AAH Data=55H ' Write Command Addrass=5555H Data=90H Wait Jus ' Read Data Ouput DQ?7-DQ0 with Address=Sector Address and A1=VIH ' Data=C2:Protect Data=00:Unprotect Verify Another Sector? NO END P/N: PMO506 REV.1.4, MAY 18, 1999=I MxX29F1610A/B Y N=1 I Sector Unprotect Flow NeN+1 Y Verify Sector Protect/Unprotect Flow NO NO YES ' YES 1 Write RESET Command Device Failed Y Sector Unprotect Complete and Device Return to Read Mode NOTE 1 : Address means A14-A0 for word and byte mode NOTE 2 : During interation, sector address should be the sectors which have not passed the verify procedure after previous interation NOTE 3 : The sector(s), which had passed the sector unprotect verification must not enter the sector unprotect flow anymore NOTE 4 : During loading sector addresses, DATA=BOH means the last sector address loaded to be unprotected NOTE 5 : Sector Address=(A19, A18, A17, A16)} NOTE 6: Sector Unprotect will be disabled when WP is low P/N: PM0506 REV.1.4, MAY 18, 1999 26-30Mic MxX29F1610A/B Sector Unprotect Flow START ' Write Command Address=5555H Data=AAH ' Write Command Address=2AAAH Data=55H Y Write Command Address=5555H Data=60H Y Write Command Address=5555H Data=AAH Write Command Address=2AAAH Data=55H ' Write Command Address=Sector Address;Data=40H Y Load Other Sector Addresses If Necessary;Data=40H mi Load The Last Sector Address; Data=BOH ' Read Status Register YES END (NOTE 2) (NOTE 3) (NOTE 4) Verify Sector Protect/Unprotect Flow START Y Write Command Address=5555H Data=AAH Y Write Command Address=2AAAH Data=55H ' Write Command Address=5555H Data=90H Wait 1us Y Read Data Ouput DQ7-DG0 with Address=Sector Address and A1=VIH 1 Data=C2:Protect Data=00:Unprotect ' Read Status Register Verify Another Sector? NO END PAN: PMO506 26-31 REV.1.4, MAY 18, 1999MX29F1610A/B Figure 12. VERIFY SECTOR PROTECT FLOW CHART ! Write Data AAH, Address 5555H 1 Write Data 55H, Address 2AAAH y Write Data 90H, Address 5555H ' Ptoect Status Read* * 1. Protect Status: Data Outputs C2H as Protected Sector Verified Code. Data Outputs 00H as Unprotected Sector Verified Code. 2. Sepecified address will be (A19,A18,A17,A16) = Sector address (A1, AQ)=(1,0) the rest of the address pins are don't care. 3. Silicon ID can be read via this Flow Chart. Refer to Table 4. P/N: PMO506 26-32 REV.1.4,MAY 18, 1999, ' wa! MX29F1610A/B Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled) WE tWH ~~ - tOES _ - tws OE = _ twe - = -~ CE 1GHWL ~ ICPH al - tcP _? ~~ a (ASL tAH ~ ADDRESSES VALID tos tDH ~- - ~~ ~~ DATA HIGH Z OA Ew vec _S wes ~~+_ Pwo _f - ~~ tPHWL 2. BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application, BYTE pin should be either static high(word mode) or static low(byte mode). P/N: PMOSO6 26-33 REV.1.4, MAY 18, 1999Mic MX29F1610A/B Figure 14. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Altemate CE Controlled) AO~AS Word offset A-1 {(Byte Mode Only) AGB~A14 as tAH a A15~A19 Page Address two ~ ~ 1BALC _ > NSN SNS NSN / J \ (CP tCPH (BAL =a > <P ~~ TNS NS NI NS NS NS SS tCES /S \ ~ OE \ tWHRLP - << RY/BY 1Ds ae (DH - tSRA ~ ~ Data Data tPHWL ~ PWD NOTE: 1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation. P/N: PM0506 REV.1.4, MAY 18, 1999 26-34Mic : MX29F1IG1OA/B ERASE AND PROGRAMMING PERFORMANCE i LIMITS PARAMETER MIN. TYP.(1) MAX.(2) UNITS Sector Erase Time 1 8 s Chip Erase Time 32 256 s Page Programming Time 0.9 27 ms Chip Programming Time 14 42 sec Erase/Program Cycles 400,000 Cycles Byte Program Time 7 300 us LL Note: 1.All numbers are sampled, not 100% tested. 2. Typical values measured at 25 C,VCC=5.0V. LATCHUP CHARACTERISTICS MIN. MAX. Input Voitage with respect to GND on all pins except /O pins -1.0V 13.5V Input Voltage with respect to GND on all 1/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. P/N: PM0506 REV.1.4, MAY 18, 1999 26-35Revision History =I MxX29F1610A/B Revision# Description Page Date 14 Update !SB1 typical value to 1uA--P20 May/13/1998 Add Control Pin Input Capacitance 1.2 Change resistance value at switching test circuits P19 Nov/10/1998 Change IOH value at DC characteristics P20 1.3 Change Pin12 of MX29F1610B TSOP fram NC to GND P2 MAR/31/1999 1.4 Remove the 70ns speed grade. P41 MAY/18/1999 Modify Erase and Programming Performance P35 P/N: PMO506 REV.1.4, MAY 18, 1999 26-36