Low Duty Cycle, 600 mA, 3 MHz Synchronous Step-Down DC-to-DC Converter ADP2102 FEATURES GENERAL DESCRIPTION Input voltage range: 2.7 V to 5.5 V 600 mA maximum load current 95% efficiency Low duty cycle operation Only 3 tiny external ceramic components 3 MHz typical operating frequency Fixed output voltage from 0.8 V to 1.875 V Adjustable output voltage up to 3.3 V 0.01 A shutdown supply current Automatic power save mode Internal synchronous rectifier Internal soft start Internal compensation Enable/shutdown logic input Undervoltage lockout Current limit protection Thermal shutdown Small 8-lead, 3 mm x 3 mm LFCSP package The ADP2102 is a synchronous step-down dc-to-dc converter that converts a 2.7 V to 5.5 V unregulated input voltage to a lower regulated output voltage with up to 95% efficiency and 1% accuracy. The low duty cycle capability of the ADP2102 is ideal for USB applications or 5 V systems that power up submicron subvolt processor cores. Its 3 MHz typical operating frequency and excellent transient response allow the use of small, low cost 1 H inductors and 2.2 F ceramic capacitors. At medium-to-high load currents, it uses a current mode, pseudofixed frequency pulsewidth modulation to extend battery life. To ensure the longest battery life in portable applications, the ADP2102 has a power save mode (PSM) that reduces the switching frequency under light load conditions to significantly reduce quiescent current. The ADP2102 is available in both fixed and adjustable output voltage options with 600 mA maximum output current. The preset output voltage options voltage are 1.875 V, 1.8 V, 1.5 V, 1.375 V, 1.25 V, 1.2 V, 1.0 V, and 0.8 V. The adjustable voltage option is available from 0.8 V to 3.3 V. The ADP2102 requires only three external components and consumes 0.01 A in shutdown mode. APPLICATIONS USB powered devices WLAN and gateways Point of loads Processor core power from 5 V Digital cameras PDAs and palmtop computers Portable media players, GPS The ADP2102 is available in an 8-lead LFCSP package and is specified for the -40 C to +85 C temperature range. TYPICAL PERFORMANCE CHARACTERISTICS VIN = 2.7V 95 VOUT = 1.375V TA = 25C VIN = 3V INPUT VOLTAGE 2.7V TO 5.5V EFFICIENCY (%) 90 CIN 2.2F 85 80 VIN = 3.6V VIN = 4.2V FORCED CCM 75 LX ADP2102 DCM/ CCM 65 ON 06631-052 1000 COUT 2.2F GND OFF 100 LOAD CURRENT (mA) 1H OUTPUT VOLTAGE 0.8V TO 1.875V FB/OUT MODE EN 70 60 10 L VIN 06631-001 100 TYPICAL APPLICATIONS CIRCUIT Figure 1. Figure 2. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. Rev. B ADP2102 TABLE OF CONTENTS Features .............................................................................................. 1 Current Limit .............................................................................. 14 Applications....................................................................................... 1 Soft Start ...................................................................................... 15 General Description ......................................................................... 1 Enable........................................................................................... 15 Typical Performance Characteristics ............................................. 1 Undervoltage Lockout ............................................................... 15 Typical Applications Circuit............................................................ 1 Thermal Shutdown .................................................................... 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications..................................................................................... 3 Inductor Selection ...................................................................... 16 Absolute Maximum Ratings............................................................ 4 Input Capacitor Selection.......................................................... 16 Thermal Resistance ...................................................................... 4 Output Capacitor Selection....................................................... 16 Boundary Condition.................................................................... 4 Typical Applications Circuits.................................................... 17 ESD Caution.................................................................................. 4 Setting the Output Voltage........................................................ 19 Pin Configuration and Function Descriptions............................. 5 Efficiency Considerations ......................................................... 19 Typical Performance Characteristics ............................................. 6 Thermal Considerations............................................................ 20 Theory of Operation ...................................................................... 13 Design Example.......................................................................... 20 Control Scheme .......................................................................... 13 Circuit Board Layout Recommendations ................................... 22 Constant On-Time Timer ......................................................... 13 Recommended Layout............................................................... 22 Forced Continuous Conduction Mode ................................... 13 Outline Dimensions ....................................................................... 24 Power Save Mode........................................................................ 13 Ordering Guide .......................................................................... 24 Synchronous Rectification ........................................................ 14 REVISION HISTORY 9/07--Rev. A to Rev. B Changes to Features, Applications, and General Description .... 1 Changes to Table 4............................................................................ 5 Changes to Table 6.......................................................................... 17 Changes to Table 7.......................................................................... 19 Changes to Circuit Board Layout Recommendations Section.... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 6/07--Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 23 6/07--Revision 0: Initial Version Rev. B | Page 2 of 24 ADP2102 SPECIFICATIONS VIN = 3.6 V, EN = VIN, MODE = VIN, TA = 25C, unless otherwise noted. Bold values indicate -40C TA +85C. 1 Table 1. Parameter INPUT CHARACTERISTICS Input Voltage Range 2 Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Range Output Voltage Initial Accuracy Load Regulation Line Regulation FEEDBACK CHARACTERISTICS FB Regulation Voltage FB Bias Current FB Impedance CURRENT CHARACTERISTICS Operating Current Shutdown Current Output Current LX (SWITCH NODE) CHARACTERISTICS LX On Resistance LX Leakage Current LX Minimum Off-Time LX On-Time Valley Current Limit ENABLE, MODE CHARACTERISTICS EN, MODE Input High Threshold EN, MODE Input Low Threshold EN, MODE Input Leakage Current SOFT START PERIOD THERMAL CHARACTERISTICS Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1 2 Conditions Min VIN rising 2.7 2.2 ADP2102-xx ADP2102-ADJ ADP2102-xx, TA= 25C, ILOAD = 0 mA ADP2102-xx, -40C TA 85C, ILOAD = 0 mA VOUT = 0.8 V to 1.875 V, ILOAD = 0 mA to 600 mA VIN = 2.7 V to 5.5 V, ILOAD = 10 mA 0.8 0.8 -1 -2 ADP2102-ADJ ADP2102-ADJ, ADP2102-0.8 ADP2102-xx 784 Typ 2.4 220 Max Unit 5.5 2.5 V V mV 1.875 3.3 +1 +2 V V % % % % 816 50 mV nA k 0.5 0.3 800 375 ADP2102 PSM mode, ILOAD = 0 mA EN = 0 V ADP2102, VIN = 2.7 V to 5.5 V 70 0.01 99 1 600 A A mA P-channel switch, ILX = 100 mA N-channel synchronous rectifier, ILX = 100 mA VIN = 5.5 V, VLX = 0 V, 5.5 V ADP2102-xx, ADP2102-ADJ ADP2102-0.8 ADP2102-1.0 ADP2102-1.2 ADP2102-1.25 ADP2102-1.375 ADP2102-1.5 ADP2102-1.8 ADP2102-1.875 ADP2102-ADJ-1.2 ADP2102-ADJ-1.5 ADP2102-ADJ-1.875 ADP2102-ADJ-3.3 (VIN = 5 V) 325 200 600 400 1 m m A ns ns ns ns ns ns ns ns ns ns ns ns ns A 55 70 100 103 135 150 180 190 80 155 200 198 100 87 107 131 133 165 182 220 237 131 177 226 238 1 105 135 160 169 195 210 260 270 170 210 275 270 1.3 VIN = 5.5 V, EN = MODE = 0 V, 5.5 V 250 500 150 15 0.4 1 800 V V A s C C All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). The input voltage (VIN) range over which the rest of the specifications are valid. The part operates as expected until VIN goes below the UVLO threshold. Rev. B | Page 3 of 24 ADP2102 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter AVIN, EN, MODE, FB/OUT to AGND LX to PGND PVIN to PGND PGND to AGND AVIN to PVIN Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Soldering Conditions 1 Rating -0.3 V to +6 V -0.3 V to (VIN + 0.3 V) -0.3 V to +6 V -0.3 V to +0.3 V -0.3 V to +0.3 V -40C to +85C1 -40C to +125C -65C to +150C JEDEC J-STD-020 The ADP2102 can be damaged when junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (JA x PD). Unless otherwise specified, all other voltages are referenced to AGND. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. Specified value of JA is based on a 4-layer, 4 in x 3 in, 2 1/2 oz copper board, as per JEDEC standards. For more information, see Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Table 3. Thermal Resistance Package Type 8-Lead LFCSP Maximum Power Dissipation JA 54 0.74 Unit C/W W BOUNDARY CONDITION Natural convection, 4-layer board, exposed pad soldered to PCB. ESD CAUTION Rev. B | Page 4 of 24 ADP2102 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MODE 1 FB/OUT 3 AGND 4 8 AVIN ADP2102 TOP VIEW (Not to Scale) 7 PVIN 6 LX 5 PGND 06631-003 EN 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic MODE 2 EN 3 FB/OUT 4 AGND 5 6 PGND LX 7 PVIN 8 AVIN Description Mode Input. To set the ADP2102 to forced continuous conduction mode (CCM), drive MODE high. To set the ADP2102 to power save mode/auto mode (PSM), drive MODE low. Enable Input. Drive EN high to turn on the ADP2102. Drive EN low to turn it off and reduce the input current to 0.1 A. This pin cannot be left floating. Output Sense Input or Feedback Input. For fixed output versions, OUT is the top of the internal resistive voltage divider. Connect OUT to the output voltage. For adjustable (no suffix) versions, FB is the input to the error amplifier. Drive FB through a resistive voltage divider to set the output voltage. The FB regulation threshold is 0.8 V. Analog Ground. Connect AGND to PGND at a single point as close to the ADP2102 as possible. The exposed paddle is electrically common with the analog ground pin. Power Ground. Switch Output. LX is the drain of the P-channel MOSFET switch and the N-channel synchronous rectifier. Connect the output LC filter between LX and the output voltage. Power Source Input. Drive PVIN with a 2.7 V to 5.5 V power source. A ceramic bypass capacitor of 2.2 F or greater is required on this pin to the nearest PGND plane. Power Source Input. AVIN is the supply for the ADP2102 internal circuitry. This pin can be connected in three different ways. For noise reduction, place an external RC filter between PVIN and AVIN. The recommended values for the external RC filter are 10 and 0.1 F, respectively. This configuration can be used for all loads. For light-to-medium loads up to 300 mA, the AVIN pin and the PVIN pin can be shorted together. For light-to-heavy loads (greater than 300 mA), bypass the AVIN pin with a 1 pF to 0.01 F capacitor to the nearest PGND plane. Do not short the AVIN and PVIN pins when using only a bypass capacitor. Rev. B | Page 5 of 24 ADP2102 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, L = 2.2 H, CIN = 2.2 F, COUT = 4.7 F, unless otherwise noted. 1.22 100 TA = 25C TA = 25C 95 80 VIN = 3.6V VIN = 4.5V 75 MODE = PSM L = 2.2H CIN = 2.2F COUT = 10F 65 60 1 10 100 LOAD CURRENT (mA) 1000 1.20 VIN = 3.6V 1.19 1.18 06631-004 70 VIN = 2.7V VIN = 4.5V 0 Figure 4. Efficiency vs. Load Current (VOUT = 1.2 V) 100 200 300 400 LOAD CURRENT (mA) 500 Figure 7. Output Voltage Accuracy (VOUT = 1.2 V) 1.52 100 TA = 25C 95 TA = 25C VIN = 2.7V OUTPUT VOLTAGE (V) VIN = 3.6V 85 VIN = 4.5V 80 75 70 MODE = PSM L = 2.2H CIN = 2.2F COUT = 10F 65 1 10 100 LOAD CURRENT (mA) 1000 1.51 VIN = 2.7V VIN = 3.6V 1.50 1.49 VIN = 4.5V 1.48 06631-005 EFFICIENCY (%) 90 60 600 06631-007 85 1.21 0 Figure 5. Efficiency vs. Load Current (VOUT = 1.5 V) 100 200 300 400 LOAD CURRENT (mA) 500 600 06631-020 EFFICIENCY (%) OUTPUT VOLTAGE (V) VIN = 2.7V 90 Figure 8. Output Voltage Accuracy (VOUT = 1.5 V) 1.82 100 TA = 25C TA = 25C 95 OUTPUT VOLTAGE (V) VIN = 2.7V 85 VIN = 4.5V 80 VIN = 3.6V 70 MODE = PSM L = 2.2H CIN = 2.2F COUT = 10F 65 60 1 10 100 LOAD CURRENT (mA) 1000 1.81 VIN = 2.7V 1.80 VIN = 3.6V 1.79 VIN = 4.5V 1.78 Figure 6. Efficiency vs. Load Current (VOUT = 1.8 V) 0 100 200 300 400 LOAD CURRENT (mA) 500 Figure 9. Output Voltage Accuracy (VOUT = 1.8 V) Rev. B | Page 6 of 24 600 06631-009 75 06631-006 EFFICIENCY (%) 90 ADP2102 100 1.53 TA = 25C CFF = 6.8pF TA = 25C 1.52 VIN = 4.5V OUTPUT VOLTAGE (V) EFFICIENCY (%) 95 VIN = 5.0V 90 VIN = 5.5V 85 PSM 1.51 1.50 CCM 1.49 10 100 LOAD CURRENT (mA) 1000 1.48 06631-050 1 Figure 10. Efficiency vs. Load Current (VOUT = 3.3 V) 0 100 200 300 400 LOAD CURRENT (mA) 500 600 06631-013 MODE = PSM 80 Figure 13. Output Voltage vs. Load Current (VOUT = 1.5 V) 1.84 95 TA = 25C PSM 90 TA = 25C 1.83 OUTPUT VOLTAGE (V) EFFICIENCY (%) 85 80 75 70 CCM 65 1.82 PSM 1.81 CCM 1.80 60 1.79 100 LOAD CURRENT (mA) 1k 1.78 06631-026 50 10 Figure 11. PSM vs. CCM Efficiency (VOUT = 1.8 V) 0 100 200 300 400 LOAD CURRENT (mA) 500 600 06631-017 55 Figure 14. Output Voltage vs. Load Current (VOUT = 1.8 V) 1.22 1.23 TA = 25C 1.22 OUTPUT VOLTAGE (V) PSM 1.20 CCM ILOAD = 0mA ILOAD = 300mA 1.21 ILOAD = 600mA 1.20 1.19 1.18 0 100 200 300 400 LOAD CURRENT (mA) 500 600 1.18 -45 Figure 12. Output Voltage vs. Load Current (VOUT = 1.2 V) -25 -5 15 35 TEMPERATURE (C) 55 75 Figure 15. Output Voltage vs. Temperature (VOUT = 1.2 V) Rev. B | Page 7 of 24 06631-046 1.19 06631-011 OUTPUT VOLTAGE (V) 1.21 ADP2102 85 1.52 +85C 1.49 ILOAD = 0mA ILOAD = 300mA ILOAD = 600mA 1.48 1.47 -15 10 35 TEMPERATURE (C) 60 85 75 -40C 70 65 60 2.7 06631-047 1.46 -40 +25C Figure 16. Output Voltage vs. Temperature (VOUT = 1.5 V) 3.0 3.3 3.6 3.9 4.2 4.5 INPUT VOLTAGE (V) 4.8 5.1 06631-045 1.50 80 QUIESCENT CURRENT (A) OUTPUT VOLTAGE (V) 1.51 5.4 Figure 19. Quiescent Current vs. Input Voltage 1.81 77 ILOAD = 0mA 76 OUTPUT VOLTAGE (V) QUIESCENT CURRENT (A) ILOAD = 300mA 1.80 1.79 ILOAD = 600mA 1.78 1.77 75 74 73 72 -15 10 35 TEMPERATURE (C) 60 85 70 -40 06631-048 1.76 -40 Figure 17. Output Voltage vs. Temperature (VOUT = 1.8 V) -20 0 20 40 60 TEMPERATURE (C) 80 100 120 06631-053 71 Figure 20. Quiescent Current vs. Temperature 3.40 0.8005 VIN = 3.6V 0.8000 FEEDBACK VOLTAGE (V) +85C 3.32 +25C 3.28 -40C 3.24 0.7995 0.7990 0.7985 0.7980 0.7975 3.20 0 100 200 300 400 LOAD CURRENT (mA) 500 600 0.7965 -50 Figure 18. Output Voltage Accuracy (VOUT = 3.3 V) 0 50 TEMPERATURE (C) Figure 21. Feedback Voltage vs. Temperature Rev. B | Page 8 of 24 100 06631-021 0.7970 06631-049 OUTPUT VOLTAGE (V) 3.36 ADP2102 4.5 400 350 1.2V 1V 0.8V 1.25V 3.0 2.5 1.375V 1.5V 1.8V 2.0 1.5 250 200 150 100 NMOS SWITCH 100 1.875V 0 PMOS SWITCH 300 50 200 300 400 LOAD CURRENT (mA) 500 600 0 -40 Figure 22. Switching Frequency vs. Load Current -20 0 20 40 60 TEMPERATURE (C) 80 100 06631-054 3.5 SWITCH ON RESISTANCE (m) 4.0 06631-051 SWITCHING FREQUENCY (MHz) TA = 25C 120 Figure 25. Switch On Resistance vs. Temperature 1.08 T TA = 25C TA = 25C 1.07 CH4: LX 4 1.05 1.04 CH1: IL 1.03 1 CH2: V OUT 1.02 1.01 3.0 3.3 3.6 3.9 4.2 4.5 4.8 INPUT VOLTAGE (V) 5.1 5.4 5.7 06631-029 1.00 2.7 2 CH1 500mA BW CH2 2.00V CH4 2.00V Figure 23. Valley Current Limit BW M 1.00s A CH4 2.76V BW T 51.00% 06631-014 CURRENT LIMIT (A) 1.06 Figure 26. PSM Mode Operation at Very Light Loads (10 mA) 400 T TA = 25C TA = 25C PSM 300 PMOS SWITCH CCM CH1: V OUT PSM 1 250 200 150 NMOS SWITCH CH3: IL 100 50 3.0 3.3 3.6 3.9 4.2 4.5 INPUT VOLTAGE (V) 4.8 5.1 Figure 24. Switch On Resistance vs. Input Voltage 5.4 CH1 50.0mV BW CH3 50.0mA BW M 100s A CH3 86.0mA 06631-022 0 2.7 3 06631-027 SWITCH ON RESISTANCE (m) 350 Figure 27. PSM Mode Entry--Exit Operation (10 mA to 50 mA to 10 mA) Rev. B | Page 9 of 24 ADP2102 T 180 TA = 25C TA = 25C 160 CH4: LX VOUT = 1.5V PSM THRESHOLD (mA) 140 4 CH1: IL 1 CH2: V OUT 120 VOUT = 1.375V 100 80 60 40 2 20 M 10.0s A CH4 2.72V B W T 51.00% 0 2.5 06631-015 BW Figure 28. PSM Mode Operation at Light Loads (75 mA) T 3.0 5.0 5.5 Figure 31. Typical PSM Threshold vs. Input Voltage T TA = 25C CH1: IL 3.5 4.0 4.5 INPUT VOLTAGE (V) TA = 25C CH1: VOUT (AC) 1 CH3: LX 1 3 CH4: VOUT CH2: I LOAD (0mA TO 300mA) 4 M 200ns A CH1 388mA BW T -4.00000ns CH1 50.0mV 06631-016 CH1 200mA BW BW CH3 2.00V CH4 2.00V CH2 200mA M 100s A CH2 220mA T 23.60% Figure 29. CCM Mode Operation at Medium/Heavy Loads (0.3 A) T VIN = 3.6V VOUT = 1.5V ILOAD = 0mA - 75mA - 0mA BW 06631-023 2 Figure 32. Load Transient Response (VOUT = 1.2 V) T TA = 25C TA = 25C CH1: LX CH1: V OUT (AC) 1 1 CH3: VOUT 75mA 3 CH2: IL CH2: ILOAD (0mA TO 300mA) BW CH2 100mA M 200s A CH2 BW 82.0mA CH1 50.0mV Figure 30. Light Load Behavior BW CH2 200mA M 100s A CH2 236mA Figure 33. Load Transient Response (VOUT = 1.5 V) Rev. B | Page 10 of 24 06631-024 CH1 2.00V CH3 1.00V 2 0mA 0mA 06631-031 2 06631-028 L = 2.2H CH1 500mA BW CH2 2.00V CH4 2.00V ADP2102 T T TA = 25C TA = 25C CH1: V OUT (AC) 1 CH1: V OUT (AC) 1 CH3: VIN (3.6V TO 4.2V STEP) CH2: ILOAD (0mA TO 300mA) B W CH2 200mA M 100s T A CH2 264mA -300.000s 06631-025 3 CH1 50.0mV CH1 50.0mV CH3 1.00V Figure 34. Load Transient Response (VOUT = 1.8 V) T B M 40.0s W A CH3 3.70V B W 06631-044 2 Figure 37. Line Transient Response (VOUT = 1.8 V) T TA = 25C TA = 25C CH4: EN CH1: VOUT (AC) 1 4 CH1: LX 1 CH3: VIN (3V TO 4V STEP) CH2: V OUT BW M 200s A CH3 3.74V BW 2 CH1 200mA BW CH2 1.00V CH4 2.00V A CH3 2.00V BW T 14.60% Figure 38. Start-Up and Shutdown Waveform Figure 35. Line Transient Response (VOUT = 1.2 V) T M 20.0ms BW 06631-019 CH1 50.0mV CH3 1.00V 06631-032 3 T TA = 25C TA = 25C CH1: VIN CH1: VOUT (AC) 1 1 CH2: V OUT 2 CH3: VIN (3V TO 4V STEP) CH3: LX CH1 50.0mV CH3 1.00V BW M 100s A CH3 BW 3.72V BW CH1 2.00V CH2 500mV CH3 200mA BW BW M 400s A CH1 T 27.60% Figure 39. Light Load Start-Up Waveform Figure 36. Line Transient Response (VOUT = 1.5 V) Rev. B | Page 11 of 24 1.40V 06631-030 3 06631-035 3 ADP2102 T TA = 25C TA = 25C CH1: LX CH1: EN 1 1 CH2: V OUT 3 CH2: VOUT 2 CH4: IL CH3: IL B W M 2.00ms A CH2 350mV T 6.600% 06631-033 B W CH2 500mV CH1 2.00V CH3 200mA BW CH1 5.00V CH3 1.00V Figure 40. Heavy Load Start-Up Waveform T B B M 1.00s W W CH4 500mA A CH3 440mV B W 06631-018 4 3 Figure 42. Short-Circuit Response at Output VIN = 3.6V VOUT = 1.375V COUT = 4.7F ILOAD = 100mA TA = 25C CH4: V OUT (AC) T TA = 25C 4 CH4: VOUT L = 2.2H CIN = 2.2F COUT = 4.7F CH1: LX 4 3 CH3: IL BW CH4 20.00mV M 2.00s A CH1 4.20V BW T 51.00% CH3 200mA BW CH4 500mV M 100s A CH4 BW T 43.40% Figure 41. PSM Mode Ripple (VIN = 3.6 V, Load = 50 mA) Figure 43. Soft Start Waveform Rev. B | Page 12 of 24 680mV 06631-055 CH1 2.00V 06631-034 1 ADP2102 THEORY OF OPERATION The ADP2102 is a high frequency, synchronous step-down, dc-to-dc converter optimized for battery-powered, portable applications. It is based on constant on-time current-mode control architecture with voltage feed forward to null frequency variation with line voltage, creating a pseudofixed frequency. This type of control allows generation of very low output voltages at a higher switching frequency and offers a very fast load and line transient response with minimal external component count and size. The ADP2102 provides features such as undervoltage lockout, thermal shutdown, and short-circuit protection. Equating Equation 1 and Equation 2 gives fSW = 1/K (3) where K is an internally set on-time scale factor constant resulting in a constant switching frequency. As shown in Equation 1, the steady state switching frequency is theoretically independent of both the input and output voltages to a first order. This means the loop switches at a nearly constant frequency until a load step occurs. CONTROL SCHEME When a load step occurs, the constant on-time control loop responds by modulating the off time up or down to quickly return to regulation. This momentary frequency variation results in a faster load transient response than a fixed frequency current-mode control loop of similar bandwidth with a similar external filter inductor and capacitor. This is an advantage of a constant on-time control scheme. The ADP2102 high-side power switch on-time is determined by a one-shot timer whose pulse width is directly proportional to the output voltage and inversely proportional to the input or line voltage. Another one-shot timer sets a minimum off time to allow for inductor valley current sensing. Resistive voltage losses in the high-side and low-side power switches, package parasitics, inductor DCR, and board parasitic resistance cause the loop to compensate by reducing the off time and, therefore, increase the switching frequency with increasing load current. The constant on-time, one-shot timer is triggered at the rising edge of EN and, subsequently, when the low-side power switch current is below the valley current limit threshold and the minimum off-time one-shot timer has timed out. A minimum off-time constraint is introduced to allow inductor valley current sensing on the synchronous switch. While the constant on-time is asserted, the high-side power switch is turned on. This causes the inductor current to ramp positively. After the constant on-time has completed, the highside power switch turns off and the low-side power switch turns on. This causes the inductor current to ramp negatively until the sensed current flowing in this switch has reached valley current limit. At this point, the low-side power switch turns off and a new cycle begins with the high-side switch turning on, provided that the minimum off-time one shot has timed out. When the MODE pin is high, the ADP2102 operates in forced continuous conduction mode (CCM). In this mode, irrespective of the load current, the inductor current stays continuous, and CCM is the preferred mode of operation for low noise applications. During this mode, the switching frequency stays close to 3 MHz typical. In this mode, efficiency is lower at light loads, compared to the power save mode, but the output voltage ripple is minimized. The ADP2102 uses valley current-mode control, which helps to prevent minimum on-time limitations at very low output voltages. This allows high frequency operation, resulting in low filter inductor and capacitor values. CONSTANT ON-TIME TIMER The constant on-time timer sets the high-side switch on-time. This fast, low jitter, adjustable one shot varies the on-time in response to input voltage for a given output voltage. The highside switch on-time is inversely proportional to the input voltage and directly proportional to the output voltage. tON = K(VOUT/VIN) (1) The duty cycle for a buck converter operating in continuous conduction mode (CCM) is given by D = VOUT/VIN and, by definition, D = tON/(tON + tOFF). Therefore, equating the duty cycle terms of VOUT/VIN and tON/(tON + tOFF) gives tON = VOUT/(VIN x fSW) (2) FORCED CONTINUOUS CONDUCTION MODE POWER SAVE MODE When the MODE pin is low, the ADP2102 operates in power save mode (PSM). In this mode, at light load currents, the part automatically goes into reduced frequency operation where some pulses are skipped to increase efficiency while remaining in regulation. At light loads, a zero-crossing comparator truncates the low-side switch on-time when the inductor current becomes negative. In this condition, the part works in discontinuous conduction mode (DCM). The threshold between CCM and DCM is approximately ILOAD (skip) = (VIN - VOUT ) x VOUT 2 x L x VIN x f SW (4) There is a first-order dependency of this threshold on the internally set on-time scale factor indicated in Equation 3. For higher load currents, the inductor current does not cross zero threshold. The device switches to the continuous conduction mode, and the frequency is fixed to the nominal value. Rev. B | Page 13 of 24 ADP2102 As a result of this auto mode control technique, losses are minimized at light loads, improving system efficiency. When the load current is further increased such that the lower peak is above the current limit threshold, the off time is lengthened to allow the current to decrease to this threshold before the next on-time begins. The PSM reverse current comparator controls the entry and exit into forced continuous conduction mode. Some minor jitter is normal during transition from DCM to CCM with loads at approximately 100 mA typical, and it has no adverse impact on regulation. Both VOUT and the switching frequency are reduced as the circuit operates in constant current mode. The load current (IOCL) under these conditions is equal to the current limit threshold plus half the ripple current, as shown in Equation 5 and in Figure 44. SYNCHRONOUS RECTIFICATION IOCL = IVALLEY + IL/2 In addition to the P-channel MOSFET switch, the ADP2102 includes an integrated N-channel MOSFET synchronous rectifier. The synchronous rectifier improves efficiency, especially at low output voltages, and reduces cost and board space by eliminating the need for an external rectifier. (5) DC CURRENT LIMIT = MAX LOAD IOCL INDUCTOR CURRENT The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off time through sensing of the voltage drop across the on resistance of the synchronous rectifier switch. The detection threshold is 1 A typical. I VALLEY CURRENT LIMIT TIME Figure 44. Valley Current Limit Figure 45 illustrates the inductor current waveform during normal operation and during current limit. The output current, IOUT, is the average of the inductor ripple current waveform. The low-to-medium load current waveform illustrates the continuous conduction mode operation with peak and valley inductor currents below the current limit threshold. When the load current is increased, the ripple waveform maintains the same amplitude and frequency because the current falls below the current limit threshold at the valley of the ripple waveform. As the current falls below the threshold during the normal offtime of each cycle, the start of each on-time is not delayed, and the circuit output voltage is regulated at the correct value. The ripple current is calculated using Equation 6. IL = VOUT x (VIN - VOUT ) (6) VIN x f SW x L The ADP2102 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode. Under negative current limit conditions, both the highside and low-side switches are disabled. IPEAK IOCL CURRENT LIMIT THRESHOLD IVALLEY IOUT I MEDIUM LOAD CURRENT HIGH LOAD CURRENT NORMAL OPERATION Figure 45. Inductor Current--Current Limit Operation Rev. B | Page 14 of 24 CURRENT LIMIT 06631-037 INDUCTOR CURRENT 06631-036 CURRENT LIMIT ADP2102 SOFT START UNDERVOLTAGE LOCKOUT The ADP2102 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, therefore limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. The undervoltage lockout circuit prevents the device from operating incorrectly at low input voltages. It prevents the converter from turning on the main switch and the synchronous switch under undefined conditions and, therefore, prevents deep discharge of the battery supply. ENABLE THERMAL SHUTDOWN The device starts operation with soft start when the EN pin is toggled from logic low to logic high. Pulling the EN pin low forces the device into shutdown mode, with a typical shutdown current of 0.01 A. In shutdown mode, both the high-side and low-side power switches are turned off, the internal resistor feedback divider is disconnected, and the entire control circuitry is switched off. For proper operation, the device is in shutdown mode when voltage applied to this pin is less than 0.4 V and enabled when voltage applied is greater than 1.3 V. This pin must not be left floating. When the junction temperature, TJ, exceeds 150C typical, the device goes into thermal shutdown. In this mode, the highside and low-side power switches are off. The device resumes operation when the junction temperature again falls below 135C typical. AVIN MODE PVIN 8 1 7 THERMAL SHUTDOWN UVLO BANDGAP REFERENCE MIN OFF-TIMER EN 2 S RISEDETECT Q R NONOVERLAPPING DRIVERS 6 LX ON-TIME TIMER REGULATION COMPARATOR FB/OUT 3 R 5 PGND R CURRENT SENSE AMPLIFIER INTERNAL COMPENSATION REVERSE CURRENT COMPARATOR 06631-038 AGND 4 ERROR AMPLIFIER FIXED ADJUSTABLE Figure 46. Internal Block Diagram Rev. B | Page 15 of 24 ADP2102 APPLICATIONS INFORMATION The external component selection for the ADP2102 applications circuit, as shown in Figure 2, is driven by the load requirement and begins with the selection of Inductor L. Once the inductor is chosen, CIN and COUT can be selected. In principle, different types of capacitors can be considered, but for battery-powered applications, the best choice is a multilayer ceramic capacitor, due to its small size and equivalent series resistance (ESR). INDUCTOR SELECTION It is recommended that the PVIN pin be bypassed with a 2.2 F or larger ceramic input capacitor. The size of the input capacitor can be increased without any limit for better input voltage filtering. X5R or X7R dielectrics are recommended, with a voltage rating of 6.3 V or 10 V. Y5U and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. The high switching frequency of the ADP2102 allows for minimal output voltage ripple, even with small inductors. Inductor sizing is a trade-off between efficiency and transient response. A small inductor leads to a larger inductor current ripple that provides excellent transient response but degrades efficiency. Due to the high switching frequency of the ADP2102, multilayer ceramic inductors can be used for an overall smaller solution size. Shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (EMI). As a guideline, the inductor peak-to-peak current ripple, IL, is typically set to 1/3 of the maximum load current for optimal transient response and efficiency. IL = VOUT x (VIN - VOUT ) LIDEAL = VIN x f SW x L I LOAD (MAX ) 3 (7) VOUT x (VIN - VOUT ) VIN x f SW x 0.3 x I LOAD ( MAX ) where fSW is the switching frequency. Finally, it is important that the inductor be capable of handling the maximum peak inductor current, IPK, determined by the following equation: IPK = ILOAD(MAX) + IL/2 (8) The dc current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Table 5 shows some typical surface mount inductors that work well in ADP2102 applications. VIN The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. For a given loop crossover frequency (the frequency at which the loop gain drops to 0 dB), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. The ADP2102 is designed to operate with small ceramic capacitors that have low ESR and equivalent series inductance (ESL) and are thus comfortably able to meet tight output voltage ripple specifications. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. When choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. If ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. The rms ripple current is calculated as VOUT = IL x (ESR + 1/ (8 x COUT x fSW)) (9) The input capacitor reduces input voltage ripple caused by the switch currents on the PVIN pin. Place the input capacitor as close as possible to the PVIN pin. V x (VIN _ MAX - VOUT ) 1 x OUT 2 3 L x f SW x VIN _ MAX (10) At nominal load currents, the converter operates in forced continuous conduction mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor. The input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. The rms input current flowing through the input capacitor is, at maximum, IOUT/2. Select an input capacitor capable of withstanding the rms input current for the maximum load current in the application to be used. VOUT x (VIN - VOUT ) OUTPUT CAPACITOR SELECTION Irms(COUT) = INPUT CAPACITOR SELECTION Irms = IOUTMAX x In applications with greater than 300 mA load current, a ceramic bypass capacitor of 0.01 F is recommended on the AVIN pin for better regulation performance. (11) The largest voltage ripple occurs at the highest input voltage, VIN. At light load currents, the converter operates in power save mode, and the output voltage ripple is dependent on the output capacitor value. The ADP2102 control loop is stable with a ceramic output capacitor of 2.2 F. For better transient performance, a 10 F ceramic capacitor is recommended at the output. Table 6 lists input and output MLCC capacitors recommended for ADP2102 applications. Page 16 of 24 ADP2102 Table 5. Recommended Inductor Selection Manufacturer FDK Corporation TDK Murata Coilcraft, Inc. Taiyo Yuden Series MIPF2520D MLP2520S2R2L LQM2HPN2R2MJ0 LPS3015-222ML NR3010T2R2M Value (H) 2.2 2.2 2.2 2.2 2.2 DCR () 0.08 0.08 0.13 0.11 0.10 Current Rating (mA) 1300 1300 1000 1500 1100 Size (L x W x H) (mm) 2.5 x 2.0 x 1.0 2.5 x 2.0 x 1.0 2.5 x 2.0 x 1.1 2.9 x 2.9 x 1.5 3.0 x 3.0 x 1.0 Vishay Table 6. Recommended Input and Output Capacitor Selection Capacitor 2.2 F 6.3 V X5R 0603 4.7 F 6.3 V X5R 0603 10 F 6.3 V X5R 0603 0.01 F 25 V X7R 0402 1 pF 50 V X7R 0402 6.8 pF 25 V X7R 0402 Murata GRM188R60J225K Taiyo Yuden JMK107BJ225KA TDK C1608X5R0J225M GRM188R60J475K JMK107BJ475KA C1608X5R0J475M GRM188R60J106M JMK107BJ106MA C2012X5R0J106M GRM155R71E103KA01D TMK105BJ103KV-F C1005X7R1E103K GJM1554C1H1R0JB01C VJ0402A1R2CXACW1BC VJ0402A6R8KXAA TYPICAL APPLICATIONS CIRCUITS VIN INPUT VOLTAGE = 2.7V TO 5.5V ADP2102-FXD 1 2 3 4 MODE AVIN EN PVIN FB/OUT AGND LX PGND 8 7 VOUT 6 5 L1 2.2H COUT 2.2F CIN 2.2F OUTPUT VOLTAGE = 0.8V TO 1.875V 06631-039 GND Figure 47. ADP2102-FXD (0 mA ILOAD 300 mA) VIN INPUT VOLTAGE = 2.7V TO 5.5V ADP2102-FXD 2 3 4 MODE AVIN EN PVIN FB/OUT AGND LX PGND 8 7 6 VOUT L1 2.2H OUTPUT VOLTAGE = 0.8V TO 1.875V 5 CBP 0.01F COUT 4.7F CIN 2.2F GND 06631-008 1 Figure 48. ADP2102-FXD (0 mA ILOAD 600 mA) Rev. B | Page 17 of 24 ADP2102 VIN INPUT VOLTAGE = 2.7V TO 5.5V ADP2102-ADJ 1 2 3 4 MODE AVIN EN PVIN FB/OUT AGND LX PGND 8 7 6 VOUT L1 2.2H 5 COUT 4.7F CIN 2.2F OUTPUT VOLTAGE = 0.8V TO 3.3V GND CFF * R1 R2 06631-040 NOTE *CFF IS NEEDED FOR ADJUSTABLE VOUT > 1.875V ONLY. SEE TABLE 7 FOR ADJUSTABLE VOUT CONFIGURATIONS. Figure 49. ADP2102-ADJ (0 mA ILOAD 300 mA) VIN INPUT VOLTAGE = 2.7V TO 5.5V ADP2102-ADJ 1 2 3 4 MODE AVIN EN PVIN FB/OUT AGND LX PGND 8 7 6 VOUT L1 2.2H OUTPUT VOLTAGE = 0.8V TO 3.3V 5 CBP 0.01F COUT 4.7F CIN 2.2F GND CFF * R1 NOTE *CFF IS NEEDED FOR ADJUSTABLE VOUT > 1.875V ONLY. SEE TABLE 7 FOR ADJUSTABLE VOUT CONFIGURATIONS. Figure 50. ADP2102-ADJ (0 mA ILOAD 600 mA) Rev. B | Page 18 of 24 06631-012 R2 ADP2102 SETTING THE OUTPUT VOLTAGE Table 7. ADP2102-ADJ Configurations for VOUT The output voltage of the ADP2102-ADJ is externally set by a resistive voltage divider from the output voltage to FB. The ratio of the resistive voltage divider sets the output voltage, and the absolute value of those resistors sets the divider string current. For lower divider string currents, the small 10 nA (50 nA maximum) FB bias current should be taken into account when calculating resistor values. The FB bias current can be ignored for a higher divider string current, but doing so degrades the efficiency at very light loads. VOUT (V) 0.8 1.0 1.2 1.25 1.375 1.5 1.8 1.875 2.0 2.5 3.0 3.3 For the ADP2102-ADJ, the equation for output voltage selection is VOUT = VFB (1 + R1/R2) (12) where: VOUT is the output voltage. VFB is the feedback voltage, 0.8 V. R1 is the feedback resistor from VOUT to FB. R2 is the feedback resistor from FB to GND. (13) For example, in a 5 V to 3.3 V application, if a 4.7 F capacitor is used at the output, a 6.8 pF feed-forward capacitor is recommended. The output capacitor value dictates the loop crossover frequency, fCO. For an output capacitor of 4.7 F, the loop crossover frequency is 150 kHz. The high frequency zero created by CFF and R1 can be very important for transient load applications. Capacitor CFF provides phase lead and functions as a speed-up capacitor to output voltage changes, so it tends to short out R1 and improve the high frequency response. This zero tends to produce a positive-going bump in the phase plot. Ideally, the peak of this bump is centered over the crossover frequency of the loop. The R1 and CFF zero is located at fZ = 1/(2 x R1 x CFF) R2 (k) 80.6 100 100 100 100 100 100 100 100 100 100 100 CFF (pF) None None None None None None None None 15 10 8.2 6.8 L (H) 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 CIN (F) 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 COUT (F) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 EFFICIENCY CONSIDERATIONS For any adjustable output voltage greater than 1.875 V, a feedforward capacitor must be added across R1 for better transient performance and stability. The formula for calculation of C1 is CFF = 1/(2 x R1 x fCO/2) R1 (k) 1 20 49.9 56.2 71.5 88.7 124 133 150 215 274 316 Efficiency is defined as the ratio of output power to input power. The high efficiency of the ADP2102 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package that reduces thermal constraints. In addition, high efficiency delivers the maximum output power for the given input power, extending battery life in portable applications. Following are the four major sources of power loss in dc-to-dc converters like the ADP2102: * * * * Power Switch Conduction Losses Power switch conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (RDS(ON)) associated with them. The amount of power loss can be approximated by (14) The ADP2102-xx (where xx represents the fixed output voltage) includes the resistive voltage divider internally, reducing the external circuitry required. For improved load regulation, connect the FB/OUT to the output voltage as close as possible to the load. For more information about the ADP2102-ADJ configurations for VOUT, see Table 7. Power switch conduction losses Inductor losses Switching losses Transition losses PSW_COND = (RDS (ON)_P x D + RDS (ON)_N x (1 - D)) x IOUT2 (15) where D = VOUT/VIN. The internal resistance of the power switches increases with temperature but decreases with higher input voltage. Figure 24 in the Typical Performance Characteristics section shows the change in RDS (ON) vs. input voltage, and Figure 25 shows the change in RDS (ON) vs. temperature for both power devices. Rev. B | Page 19 of 24 ADP2102 Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the ADP2102 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. The total amount of inductor power loss can be calculated by 2 OUT PL = DCR x I + Core Losses (16) Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge Q from the input supply to the gate and then from the gate to ground. The amount of power loss can be calculated by PSW = (CGATE_P + CGATE_N) x VIN2 x fSW (17) where: CGATE_P is the gate capacitance of the internal high-side switch. CGATE_N is the gate capacitance of the internal low-side switch. fSW is the switching frequency. Transition Losses Transition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of an LX node transition, the power switch provides all the inductor current. The source to drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with load current and input voltage and occur twice for each switching cycle. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to power dissipation, shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to power dissipation in it. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is defined as the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = JA x PD (20) where: TR is the rise in temperature of the package. JA is the thermal resistance from the junction of the die to the ambient temperature of the package. PD is the power dissipation in the package. DESIGN EXAMPLE The calculations in this section provide only a rough estimate and are no substitute for bench evaluation. Consider an application where the ADP2102 is used to step down from 3.6 V to 1.8 V with an input voltage range of 2.7 V to 4.2 V. VOUT = 1.8 V @ 600 mA Pulsed Load = 300 mA VIN = 2.7 V to 4.2 V (3.6 V typical) fSW = 3 MHz (typical) TA = 85C The amount of power loss can be calculated by PTRAN = VIN/2 x IOUT x (tR + tF) x fSW (19) (18) Inductor where: tR is the rise time of the LX node. tF is the fall time of the LX node. IL = THERMAL CONSIDERATIONS L= In most applications, the ADP2102 does not dissipate a lot of heat, due to its high efficiency. However, in applications with maximum loads at high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is great enough that it may cause the junction temperature of the die to exceed the maximum junction temperature of 125C. Once the junction temperature exceeds 150C, the converter goes into thermal shutdown. It recovers only after the junction temperature has decreased to below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. VOUT x (VIN - VOUT ) VIN x f SW x L VOUT x (1 - VOUT / VINMAX ) f SW x 0.3 x I LOAD ( MAX ) I LOAD (MAX ) 3 = = 0.6/3 = 200 mA 1.8 x (1 - 1.8 / 4.2) (3 x 106 x 0.3 x 0.6) 1.90 H Choose a 2.2 H inductor for this application. Rev. B | Page 20 of 24 IPK = ILOAD(MAX) + IL/2 = 0.6 + 0.2/2 = 0.7 A PL = IOUTMAX2 x DCR = (0.6 A)2 x 0.08 (FDK MIPF2520D) = 29 mW = ADP2102 Output Capacitor Input Capacitor For transient applications, assume a droop of 0.1 V. Typically, it takes two to three cycles for the output to settle from a load transient because the capacitor alone supplies the load current until the loop responds. Assume an input ripple of 27 mV based on 1% of VIN_MIN. For ceramic capacitors, the typical ESR is from 5 m to 15 m. CIN = Under these conditions, a minimum required output capacitance is calculated as follows: COUT_MIN = 3 x I LOAD VDROOP x f SW = 3 x 0. 3 0.1 x 3 x 106 1 = 2.2 F (0.027/ 0.6 - 0.005) x 4 x 3 x106 = 3 F Irms = IOUT/2 = 0.3 A rms Choose a 4.7 F capacitor for this application. PCIN = Irms2 x ESR = (0.3)2 x 0.005 = 450 W For an instantaneous step decrease in load current, the output capacitor required to limit the output voltage overshoot (VOS) during a full load to no load transient must be determined. This transient requires the excess energy stored in the output inductor to be absorbed by the output capacitor with a limited overshoot in the output voltage. Losses PSW_COND = (RDS (ON)_P x D + RDS (ON)_N x (1 - D)) x IOUT2 = (0.310 x 0.5 + 0.145 x 0.5) x (0.6)2 = 82 mW PTRAN = (VIN/2) x IOUT x (tR + tF) x fSW = (3.6/2) x 0.6 x (5 ns + 5 ns) x 3 x 106 = 32.4 mW PSW = (CGATE_P + CGATE_N) x VIN2 x fSW = (200 pF) x (3.6)2 x 3 x 106 = 7.8 mW Assuming an overshoot of 50 mV for a full load transient, COUT = L x IOUT 2 (VOUT + VOS )2 - VOUT 2 = 2.2 H x (0.6)2 (1.85)2 - (1.8)2 = 4.33 F PL = DCR x IOUT2 = 0.08 x (0.6)2 = 28.8 mW PLOSS = PSW_COND + PTRAN + PSW + PL = 82 mW + 32.4 mW + 7.8 mW + 28.8 mW = 151 mW Choose a 4.7 F capacitor for this application. Irms = 1 2 3 1 2 3 x x VOUT x (VIN _ MAX - VOUT ) L x f SW x VIN _ MAX 1.8 x (4.2 - 1.8) 2.2 x 10-6 x 3 x 106 x 4.2 1 = (VIN / I OUT - ESR) x 4 x f SW TJMAX = TA + JA = PLOSS = 85C + 54C/W x 151 mW = 93.15C = 45 mA rms PLOSS is well below the junction temperature maximum of 125C. PCOUT = Irms2 x ESR = (0.045)2 x 0.005 = 10.12 W Rev. B | Page 21 of 24 ADP2102 CIRCUIT BOARD LAYOUT RECOMMENDATIONS * Good circuit board layout is essential in obtaining the best performance from the ADP2102. Poor circuit layout degrades the output ripple and regulation, as well as the EMI and electromagnetic compatibility performance. Figure 52 and Figure 53 show the ideal circuit board layout for the typical applications circuit shown in Figure 48. Use this layout to achieve the highest performance. Refer to the following guidelines for optimum layout: * * * Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. In addition, connect the ground references of power components, such as input and output capacitors, to power ground. Connect both ground planes to the exposed pad of the ADP2102. Place the input capacitor as close to the PVIN pin as possible and connect the other end to the closest power ground plane. For low noise and better transient performance, a filter is recommended between PVIN and AVIN. Place the 0.1 F, 10 low-pass input filter between the AVIN pin and the PVIN pin, as close to AVIN as possible; or the AVIN pin can be bypassed with a 1 pF capacitor to the nearest GND plane. * Ensure that the high current loops are as short and as wide as possible. Make the high current path from CIN through L, COUT, and the PGND plane back to CIN as short as possible. To accomplish this, ensure that the input and output capacitors share a common PGND plane. In addition, make the high current path from the PGND pin through L and COUT back to the PGND plane as short as possible. To do this, ensure that the PGND pin of the ADP2102 is tied to the PGND plane as close as possible to the input and output capacitors. Place the feedback resistor divider network as close as possible to the FB pin to prevent noise pickup. Try to minimize the length of trace connecting the top of the feedback resistor divider to the output while keeping away from the high current traces and the switch node (LX) that can lead to noise pickup. To reduce noise pickup, place an analog ground plane on either side of the FB trace and make it as small as possible to reduce the parasitic capacitance pickup. RECOMMENDED LAYOUT VIN PGND MODE 9 mm CBP CIN EN VOUT COUT FB/OUT 8 mm L1 INDUCTOR 06631-041 AGND ADP2102 Figure 51. Recommended PCB Layout of the ADP2102-FXD Rev. B | Page 22 of 24 ADP2102 VIN PGND MODE CBP EN CIN COUT VOUT FB/OUT ADP2102 L1 INDUCTOR 06631-042 AGND Figure 52. Recommended Layout of the Top Layer of the ADP2102-FXD Application Board VIN MODE PGND EN VOUT AGND 06631-043 FB/OUT Figure 53. Recommended Layout of the Bottom Layer of the ADP2102-FXD Application Board Rev. B | Page 23 of 24 ADP2102 OUTLINE DIMENSIONS 3.25 3.00 SQ 2.75 0.60 MAX 5 TOP VIEW PIN 1 INDICATOR 2.95 2.75 SQ 2.55 8 12 MAX (BOTTOM VIEW) 1 1.89 1.74 1.59 PIN 1 INDICATOR 0.05 MAX 0.01 NOM 0.30 0.23 0.18 0.20 REF 061507-B SEATING PLANE 0.50 0.40 0.30 0.70 MAX 0.65 TYP 1.60 1.45 1.30 EXPOSED PAD 4 0.90 MAX 0.85 NOM 0.50 BSC 0.60 MAX Figure 54. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model ADP2102YCPZ-0.8-R71 ADP2102YCPZ-1.0-R71 ADP2102YCPZ-1.2-R71 ADP2102YCPZ-1.25R71 ADP2102YCPZ-1.37R71 ADP2102YCPZ-1.5-R71 ADP2102YCPZ-1.8-R71 ADP2102YCPZ-1.87R71 ADP2102YCPZ-1-R71 ADP2102YCPZ-2-R71 ADP2102YCPZ-3-R71 ADP2102YCPZ-4-R71 ADP2102-0.8-EVALZ1 ADP2102-1.0-EVALZ1 ADP2102-1.2-EVALZ1 ADP2102-1.25-EVALZ1 ADP2102-1.375-EVALZ1 ADP2102-1.5-EVALZ1 ADP2102-1.8-EVALZ1 ADP2102-1.875EVALZ1 ADP2102-1-EVALZ1 ADP2102-2-EVALZ1 ADP2102-3-EVALZ1 ADP2102-4-EVALZ1 Output Current (mA) 600 600 600 600 600 600 600 600 600 600 600 600 Temperature Range3 -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Output Voltage 0.8 V 1.0 V 1.2 V 1.25 V 1.375 V 1.5 V 1.8 V 1.875 V 0.8 V to 1.2 V 1.2 V to 1.5 V 1.5 V to 1.875 V 2.5 V to 3.3 V2 Fixed Output 0.8 V Fixed Output 1.0 V Fixed Output 1.2 V Fixed Output 1.25 V Fixed Output 1.375 V Fixed Output 1.5 V Fixed Output 1.8 V Fixed Output 1.875 V Adjustable Output 0.8 V to 1.2 V Adjustable Output 1.2 V to 1.5 V Adjustable Output 1.5 V to1.875 V Adjustable Output 2.5 V to 3.3 V 1 Z = RoHS Compliant Part. 2.5 V to 3.3 V adjustable output voltage option is from 4.5 V < VIN < 5.5 V only. 3 Operating junction temperature range: -40C to +125C. 2 (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06631-0-9/07(B) Rev. B | Page 24 of 24 Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD 8-Lead LFCSP_VD Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Package Option CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 Branding L5T L5U L5V L5W L5X L5Y L5Z L60 L6K L6L L6M L6N Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADP2102-2-EVALZ ADP2102-1.0-EVALZ ADP2102-1.25-EVALZ ADP2102-1.2-EVALZ ADP2102-1.8-EVALZ ADP2102-1-EVALZ ADP2102-4-EVALZ ADP2102-1.375EVALZ ADP2102-3-EVALZ ADP2102-0.8-EVALZ ADP2102YCPZ-3-R7 ADP2102-1.5-EVALZ ADP2102YCPZ-1.2-R7 ADP2102-1.875EVALZ ADP2102YCPZ-4-R7