AT24C04-W1827T2 - Atmel Corporation

Features

•Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

•Automotive Temperature Range –40°C to 125°C

•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),

1024 x 8 (8K) or 2048 x 8 (16K)

•Two-wire Serial Interface

•Schmitt Trigger, Filtered Inputs for Noise Suppression

•Bidirectional Data Transfer Protocol

•400 kHz Compatibility

•Write Protect Pin for Hardware Data Protection

•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes

•Partial Page Writes are Allowed

•Self-timed Write Cycle (5 ms max)

•High-reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

•8-lead JEDEC SOIC and 8-lead TSSOP Packages

Description

The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial

electrically erasable and programmable read-only memory (EEPROM) organized as

128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many

automotive applications where low-power and low-voltage operation are essential.

The AT24C01A/02/04/08A/16A is available in space-saving 8-lead JEDEC SOIC and

8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition,

the entire family is available in 2.7V (2.7V to 5.5V) versions.

Table 1. Pin Configurations

Pin Name Function

A0 − A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

Two-wire

Automotive

Temperature

Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

16K (2048 x 8)

AT24C01A(1)

AT24C02(2)

AT24C04

AT24C08A

AT24C16A

5092D–SEEPR–4/07

Notes: 1. AT24C01A not recom-

mended for new

design; please refer to

AT24C01B Automotive

datasheet.

2. AT24C02 not recom-

mended for new

design; please refer to

AT24C02B Automo-

tive datasheet.

8-lead SOIC

GND

VCC

SCL

SDA

8-lead TSSOP

GND

VCC

SCL

SDA

2AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Figure 1. Block Diagram

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open-

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device

address inputs that are hard wired for the AT24C01A and the AT24C02. As many as

eight 1K/2K devices may be addressed on a single bus system (device addressing is

discussed in detail under the Device Addressing section).

The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K

devices may be addressed on a single bus system. The A0 pin is a no connect.

Absolute Maximum Ratings

Operating Temperature......................................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K

devices may be addressed on a single bus system. The A0 and A1 pins are no

connects.

The AT24C16A does not use the device address pins, which limits the number of

devices on a single bus to one. The A0, A1 and A2 pins are no connects.

WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that

provides hardware data protection. The Write Protect pin allows normal read/write oper-

ations when connected to ground (GND). When the Write Protect pin is connected to

VCC, the write protection feature is enabled and operates as shown in the following

table.

Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,

the 1K requires a 7-bit data word address for random word addressing.

AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,

the 2K requires an 8-bit data word address for random word addressing.

AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,

the 4K requires a 9-bit data word address for random word addressing.

AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes

each, the 8K requires a 10-bit data word address for random word addressing.

AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes

each, the 16K requires an 11-bit data word address for random word addressing.

Table 2. Write Protect

WP Pin

Status

Part of the Array Protected

24C01A 24C02 24C04 24C08A 24C16A

At VCC Full (1K) Array Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array

At GND Normal Read/Write Operations

4AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Table 3. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Table 4. DC Characteristics

Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 2.7 5.5 V

ICC Supply Current VCC = 5.0V Read at 100 kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V Write at 100 kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA

ISB2 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) −0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: 1. This parameter is characterized and is not 100% tested (TA = 25°C).

2. This parameter is characterized.

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see to

Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (see to Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (see Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from

the EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has

received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode

which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the

completion of any internal operations.

Table 5. AC Characteristics

Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted)

Symbol Parameter

AT24C01A/02/04/08A/16A

UnitsMin Max

fSCL Clock Frequency, SCL 400 kHz

tLOW Clock Pulse Width Low 1.2 µs

tHIGH Clock Pulse Width High 0.6 µs

tINoise Suppression Time(1) 50 ns

tAA Clock Low to Data Out Valid 0.1 0.9 µs

tBUF

Time the bus must be free before

a new transmission can start(2) 1.2 µs

tHD.STA Start Hold Time 0.6 µs

tSU.STA Start Set-up Time 0.6 µs

tHD.DAT Data In Hold Time 0 µs

tSU.DAT Data In Set-up Time 100 ns

tRInputs Rise Time(2) 300 ns

tFInputs Fall Time(2) 300 ns

tSU.STO Stop Set-up Time 0.6 µs

tDH Data Out Hold Time 50 ns

tWR Write Cycle Time 5 ms

Endurance(2) 5.0V, 25°C, Page Mode 1M Write Cycles

6AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

MEMORY RESET: After an interruption in protocol, power loss or system reset, any

two-wire part can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Figure 4. Data Validity

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

SDA

SCL

START STOP

8AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word

following a start condition to enable the chip for a read or write operation (see to Figure

7 on page 9).

The device address word consists of a mandatory “1”, “0” sequence for the first four

most significant bits as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.

These 3 bits must compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a

memory page address bit. The two device address bits must compare to their corre-

sponding hardwired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next two bits being for

memory page addressing. The A2 bit must compare to its corresponding hardwired

input pin. The A1 and A0 pins are no connect.

The 16K does not use any device address bits but instead the three bits are used for

memory page addressing. These page addressing bits on the 4K, 8K and 16K devices

should be considered the most significant bits of the data word address which follows.

The A0, A1 and A2 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is

not made, the chip will return to a standby state.

Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a “0” and then clock in the first 8-bit data word. Following receipt

of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as

a microcontroller, must terminate the write sequence with a stop condition. At this time

the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All

inputs are disabled during this write cycle and the EEPROM will not respond until the

write is complete (see Figure 8 on page 10).

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K

and 16K devices are capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send

a stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to seven

(1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”

after each data word received. The microcontroller must terminate the page write

sequence with a stop condition (see Figure 9 on page 10).

The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally

incremented following the receipt of each data word. The higher data word address bits

are not incremented, retaining the memory page row location. When the word address,

internally generated, reaches the page boundary, the following byte is placed at the

beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data

words are transmitted to the EEPROM, the data word address will “roll over” and previ-

ous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

ing a start condition followed by the device address word. The read/write bit is

representative of the operation desired. Only if the internal write cycle has completed

will the EEPROM respond with a “0”, allowing the read or write sequence to continue.

Read Operations Read operations are initiated the same way as write operations with the exception that

the read/write select bit in the device address word is set to “1”. There are three read

operations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the

last address accessed during the last read or write operation, incremented by one. This

address stays valid between operations as long as the chip power is maintained. The

address “roll over” during read is from the last byte of the last memory page to the first

byte of the first page. The address “roll over” during write is from the last byte of the cur-

rent page to the first byte of the same page.

Once the device address with the read/write select bit set to “1” is clocked in and

acknowledged by the EEPROM, the current address data word is serially clocked out.

The microcontroller does not respond with an input “0” but does generate a following

stop condition (see Figure 10 on page 10).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the

data word address. Once the device address word and data word address are clocked

in and acknowledged by the EEPROM, the microcontroller must generate another start

condition. The microcontroller now initiates a current address read by sending a device

address with the read/write select bit high. The EEPROM acknowledges the device

address and serially clocks out the data word. The microcontroller does not respond

with a “0” but does generate a following stop condition (see Figure 11 on page 11).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or

a random address read. After the microcontroller receives a data word, it responds with

an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to

increment the data word address and serially clock out sequential data words. When the

memory address limit is reached, the data word address will “roll over” and the sequen-

tial read will continue. The sequential read operation is terminated when the

microcontroller does not respond with a “0” but does generate a following stop condition

(see Figure 12 on page 11).

Figure 7. Device Address

MSB

10 AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Figure 8. Byte Write

Figure 9. Page Write

(* = DON’T CARE bit for 1K)

Figure 10. Current Address Read

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Figure 11. Random Read

(* = DON’T CARE bit for 1K)

Figure 12. Sequential Read

12 AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: 1. This device is not recommended for new design. Please refer to AT24C01B Automotive datasheet.

AT24C01A Ordering Information(1)

Ordering Code Package Operation Range

AT24C01A-10SQ-2.7

AT24C01A-10TQ-2.7

8S1

8A2

Lead-free/Halogen-free/Automotive

Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

−2.7 Low-voltage (2.7V to 5.5V)

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: 1. This device is not recommended for new design. Please refer to AT24C02B Automotive datasheet.

AT24C02 Ordering Information(1)

Ordering Code Package Operation Range

AT24C02N-10SQ-2.7

AT24C02-10TQ-2.7

8S1

8A2

Lead-free/Halogen-free/Automotive

Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

−2.7 Low-voltage (2.7V to 5.5V)

14 AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

AT24C04 Ordering Information

Ordering Code Package Operation Range

AT24C04N-10SQ-2.7

AT24C04-10TQ-2.7

8S1

8A2

Lead-free/Halogen-free/Automotive

Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

−2.7 Low-voltage (2.7V to 5.5V)

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables

(Table 4 on page 4 and Table 5 on page 5).

AT24C08A Ordering Information

Ordering Code Package Operation Range

AT24C08AN-10SQ-2.7

AT24C08A-10TQ-2.7

8S1

8A2

Lead-free/Halogen-free/

Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

−2.7 Low Voltage (2.7V to 5.5V)

16 AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables

(Table 4 on page 4 and Table 5 on page 5).

AT24C16A Ordering Information

Ordering Code Package Operation Range

AT24C16AN-10SQ-2.7

AT24C16A-10TQ-2.7

8S1

8A2

Lead-free/Halogen-free/

Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)

Options

−2.7 Low Voltage (2.7V to 5.5V)

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Packaging Information

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 B

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0˚ – 8˚

∅

Top View

End View

Side View

18 AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

8A2 – TSSOP

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

Revision History

Doc. Rev. Date Comments

5092D 4/2007 Added ‘Not recommended for new design’ notes to AT24C01A and

AT24C02 on pages 1, 12 and 13.

5092C 2/2007 Implemented revision history.

Removed PDIP offering and parts.

Added ‘AT24C02 Not Recommended for New Design’ note to page

Printed on recycled paper.

5092D–SEEPR–4/07

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

Atmel Corporation Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Regional Headquarters

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Memory

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Literature Requests

www.atmel.com/literature

Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.