CY7C1326
PRELIMINARY
4
Introduction
Functional Overview
All synchrono us inp uts pass th rou gh input r egiste rs con trol led
by the rising edge of the clock. All data outputs pass through
outpu t regist ers control le d by the ri sing edge of the cloc k. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device). A two-bit on-chip wraparound burst counter captures
the first addr ess in a burst sequence and automatically incre-
ments the address for the rest of the burst access.
The CY7C132 6 supports secondary cache in systems utiliz ing
either a linear or interl eaved burst sequence. The int erleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst seque nce. The burst order is user selectab le, and is de-
termined by sampling the MODE inpu t. Accesses can be initi-
ated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input.
Byte write operations are qual ified with the Byte Write Enable
(BWE) and Byte Write Select (BW[0-1]) inputs. A Global Write
Enable (GW) overrides al l byte writ e inputs an d writ es data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circ uitry.
Three synchronous chip selects (CE1, CE2, CE3) and an asyn-
chronous output enable (OE) provide for easy bank selecti on
and output three-state control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE 2, CE3 ar e all ass erted activ e, and ( 3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs
(A0–A16) is store d into the addr ess advancemen t logi c and th e
Address Register while being presented to the memory core.
The cor res ponding data is allo we d to pro pagate t o t he input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.5 ns (166-MHz device) if OE is active
LO W. The only ex cept ion occur s when the SRAM is emergin g
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the fi rst cycle of the access, the output s are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at cl ock r ise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Ini tiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asser t ed LOW, and (2)
CE1, CE 2, CE3 a re all a sserted act iv e. The add res s prese nte d
to A0–A16 is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, BW0, and BW1) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
comp lete . If GW is asserted LO W on the second clock rise , th e
data presented to t he DQ0–DQ15 and DP inputs is writ ten int o
the corresponding address location in th e RAM co re. If GW is
HIGH, then the write operation is controlled by BWE and
BW[1:0] signals. The CY7C1326 provides byte write capability
that i s descri bed in t he Write Cycle Desc ripti ons tab l e. As sert-
ing the Byte Write Enable input (BWE) wi th th e se lected B y te
Write (BW0, BW1) input w ill selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will rem ain unalter ed. A synchronous self-timed write mecha-
nism has been provided to simplify the wr ite operations.
Because the CY7C1326 is a common I/O device, the Output
Enabl e (OE) must be deasse rted HIGH b efore pre senting dat a
to the DQ0–DQ15 and DP inputs. Doing so will thre e -s tat e the
output drivers. As a safety precaution, DQ0–DQ15 and DP are
automatically three-stated whene ver a wri te cycle is detected,
regardless of the state of OE.
Single Write Acce sses Ini ti ated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, C E2, CE 3 are all asser ted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW0, BW1) are asser ted active to conduct a write
to the desired b yte(s). ADSC triggered write accesses requir e
a single clock cycle to complete. The address presented to
A0–A16 is loaded into the address register and the address
advan cement l ogic while be ing deli vered to t he RAM core . The
ADV input is i gnored during this cycle. If a global write is con-
ducted, the data pres ented to the DQ 0–DQ15 and DP are writ -
ten into the corresponding address location in the RAM core.
If a b yte write i s conducted, only the s elected b ytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1326 is a common I/O device, the Output
Enabl e (OE) must be deasse rted HIGH b efore pre senting dat a
to the DQ0–DQ15 and DP inputs. Doing so will thre e -s tat e the
output drivers. As a safety precaution, DQ0–DQ15 and DP are
automatically three-stated whene ver a wri te cycle is detected,
regardless of the state of OE.
Burst Se quences
The CY7C1326 pr ov ides a tw o-bit wrapar ound c ounter, fed b y
A0 and A1, t hat imple ments either an interleave d or linear burst
sequence . The inte rleaved b urst sequen ce i s des ign ed speci f-
ically to support Intel Pentium applications. The linear burst
sequence is designed to suppor t processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input .
Asser ting ADV LOW at clock rise wil l aut om atically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00