fax id: 1106 PRELIMINARY CY7C1326 128K x 18 Synchronous-Pipelined Cache RAM Features Functional Description * Low (1.65 mW) standby power (f=0, L version) The CY7C1326 is a 3.3V 128K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. * Supports 100-MHz bus for Pentium(R) and PowerPCTM operations with zero wait states All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. * Fully registered inputs and outputs for pipelined operation * 128K x 18 common I/O architecture * Single 3.3V power supply * Fast clock-to-output times -- 3.5 ns (for 166-MHz device) The CY7C1326 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the processor address strobe (ADSP) or the controller address strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. -- 4.0 ns (for 133-MHz device) -- 4.5 ns (for 117-MHz device) -- 5.5 ns (for 100-MHz device) * User-selectable burst counter supporting Intel(R) Pentium interleaved or linear burst sequences * Separate processor and controller address strobes Byte write operations are qualified with the two Byte Write Select (BW[0:1]) inputs. A Global Write Enable (GW) overrides the byte write inputs and writes data to both bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. * Synchronous self-timed writes * Asynchronous output enable * JEDEC-standard 100-pin TQFP pinout Three synchronous chip selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. * "ZZ" Sleep Mode option and Stop Clock option Logic Block Diagram (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[16:0] GW Q 17 15 ADDRESS CE REGISTER D 15 17 128KX18 MEMORY ARRAY BWE BW1 D DQ[15:8],DP[1]Q BYTEWRITE REGISTERS BW0 D DQ[7:0],DP[0] Q BYTEWRITE REGISTERS CE1 CE2 CE3 18 18 D ENABLE Q CE REGISTER CLK D Q ENABLE DELAY REGISTER CLK OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[15:0] DP[1:0] Intel and Pentium are trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 August 24, 1998 PRELIMINARY CY7C1326 Pin Configuration 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE 1 CE 2 NC NC BWS1 BWS0 CE 3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Lead TQFP NC NC NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VDDQ VSS NC DP0 DQ7 DQ6 VSS VDDQ DQ5 DQ4 VSS NC VDD ZZ DQ3 DQ2 VDDQ VSS DQ1 DQ0 NC NC VSS VDDQ NC NC NC BYTE0 NC MODE A5 A4 A3 A2 A1 A0 DNU DNU VSS VDD DNU DNU A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 BYTE1 VDDQ VSS NC NC DQ8 DQ9 VSS VDDQ DQ10 DQ11 NC VDD NC VSS DQ12 DQ13 VDDQ VSS DQ14 DQ15 DP 1 NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Selection Guide 7C1326-166 7C1326-133 7C1326-117 7C1326-100 Maximum Access Time (ns) 3.5 4.0 4.5 5.5 Maximum Operating Current (mA) 420 375 350 325 Maximum Standby Current (mA) 2.0 2.0 2.0 2.0 2 PRELIMINARY CY7C1326 Pin Definitions Pin Number 49-44, 81,82, 99, 100, 32-37 94-93 Name A[16:0] I/O InputSynchronous BW[1:0] 88 GW InputSynchronous InputSynchronous 87 BWE 89 CLK 98 CE1 InputSynchronous 97 CE2 92 CE3 86 OE InputSynchronous InputSynchronous InputAsynchronous 83 ADV 84 ADSP 85 ADSC InputSynchronous 64 ZZ InputAsynchronous I/OSynchronous 29, 28, DQ[15:0], 25-22, 19, DP[1:0] 18,13,12, 9-6, 3, 2, 79, 78, 75-72, 69, 68, 63, 62 59-56, 53, 52 15, 41, 65, 91 VDD InputSynchronous Input-Clock InputSynchronous InputSynchronous Power Supply 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 31 VSS VDDQ MODE InputStatic 1, 14, 16, 30, 38, 39, 42, 43, 49, 50, 51, 66, 80 NC - VSSQ Ground I/O Power Supply I/O Ground Description Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A 0 and A 1 feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A [16:0] is captured in the address registers. A0 and A 1 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A [16:0] is captured in the address registers. A0 and A 1 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. Selects burst order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. No Connects. 3 PRELIMINARY CY7C1326 HIGH, then the write operation is controlled by BWE and BW[1:0] signals. The CY7C1326 provides byte write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW0, BW1) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz device). A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Because the CY7C1326 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ0-DQ15 and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ0-DQ15 and DP are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. The CY7C1326 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW0, BW1) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A0-A16 is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ0-DQ15 and DP are written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[0-1]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous chip selects (CE1, CE 2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A0-A16) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Because the CY7C1326 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ0-DQ15 and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ0-DQ15 and DP are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1326 provides a two-bit wraparound counter, fed by A0 and A1, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Single Write Accesses Initiated by ADSP Interleaved Burst Sequence This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A0-A16 is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, BW0, and BW1) and ADV inputs are ignored during this first cycle. First Address ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ0-DQ15 and DP inputs is written into the corresponding address location in the RAM core. If GW is 4 Second Address Third Address Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 PRELIMINARY CY7C1326 Sleep Mode Linear Burst Sequence First Address Second Address Third Address The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE 1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Cycle Descriptions[1,2,3] Next Cycle Add. Used ZZ CE3 CE2 CE1 ADSP ADSC ADV OE DQ Write Unselected None L X X 1 X 0 X X Hi-Z X Unselected None L 1 X 0 0 X X X Hi-Z X Unselected None L X 0 0 0 X X X Hi-Z X Unselected None L 1 X 0 1 0 X X Hi-Z X Unselected None L X 0 0 1 0 X X Hi-Z X Begin Read External L 0 1 0 0 X X X Hi-Z X Begin Read External L 0 1 0 1 0 X X Hi-Z read Continue Read Next L X X X 1 1 0 1 Hi-Z read Continue Read Next L X X X 1 1 0 0 DQ read Continue Read Next L X X 1 X 1 0 1 Hi-Z read Continue Read Next L X X 1 X 1 0 0 DQ read Suspend Read Current L X X X 1 1 1 1 Hi-Z read Suspend Read Current L X X X 1 1 1 0 DQ read Suspend Read Current L X X 1 X 1 1 1 Hi-Z read Suspend Read Current L X X 1 X 1 1 0 DQ read Begin Write Current L X X X 1 1 1 X Hi-Z write Begin Write Current L X X 1 X 1 1 X Hi-Z write Begin Write External L 0 1 0 1 0 X X Hi-Z write Continue Write Next L X X X 1 1 0 X Hi-Z write Continue Write Next L X X 1 X 1 0 X Hi-Z write Suspend Write Current L X X X 1 1 1 X Hi-Z write Suspend Write Current L X X 1 X 1 1 X Hi-Z write ZZ "sleep" None H X X X X X X X Hi-Z X Notes: 1. X=Don't Care, 1=HIGH, 0=LOW. 2. Write is defined by BWE, BW[1:0], and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5 PRELIMINARY CY7C1326 Write Cycle Descriptions[1,2,3] Function GW BWE BW1 BW0 Read 1 1 X X Read 1 0 1 1 Write Byte 0 - DQ[7:0], DP[0] 1 0 1 0 Write Byte 1 - DQ[15:8], DP[1] 1 0 0 1 Write Both Bytes 1 0 0 0 Write Both Bytes 0 X X X Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied .................................................. -55C to +125C Operating Range Supply Voltage on VDD Relative to GND .........-0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[4] .....................................-0.5V to VDDQ + 0.5V Com'l DC Input Voltage ..................................-0.5V to VDDQ + 0.5V [4] Notes: 4. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 5. TA is the "instant on" case temperature 6 Ambient Temperature[5] VDD 0C to +70C 3.3V -5%/+10% PRELIMINARY CY7C1326 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VCC Power Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 3.135 3.6 V VOH Output HIGH Voltage VDD = Min., IOH = -4.0 mA VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.4 [7] VIL Input LOW Voltage IX Input Load Current except ZZ and MODE GND V I VDDQ Input Current of MODE Input = VSS V 0.4 V 2.0 VDDQ + 0.3V V -0.3 0.8 V -5 5 A A -30 Input = VDDQ Input Current of ZZ -5 -5 IOZ Output Leakage Current GND V I VDDQ, Output Disabled ICC VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CS Power-Down Current--TTL Inputs ISB2 Max. V DD, Device Deselected, VIN VIH or VIN V IL f = fMAX = 1/tCYC Automatic CS Max. V DD, Device Deselected, Power-Down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 ISB3 Automatic CS Max. VDD, Device Deselected, or Power-Down VIN 0.3V or VIN > VDDQ - 0.3V Current--CMOS Inputs f = fMAX = 1/tCYC ISB4 Automatic CS Power-Down Current--TTL Inputs A 5 Input = VSS Input = VDDQ A 30 A 5 A 6-ns cycle, 166 MHz 420 mA 7.5-ns cycle, 133 MHz 375 mA 8.5-ns cycle, 117 MHz 350 mA 10-ns cycle, 100 MHz 325 mA 6-ns cycle, 166 MHz 35 mA 7.5-ns cycle, 133 MHz 30 mA 8.5-ns cycle, 117 MHz 25 mA 10-ns cycle, 100 MHz 25 mA 2.5 mA L Version 500 A 6-ns cycle, 166 MHz 10 mA 7.5-ns cycle, 133 MHz 10 mA 8.5-ns cycle, 117 MHz 10 mA 10-ns cycle, 100 MHz 10 mA 18 mA Max. V DD, Device Deselected, VIN VIH or VIN V IL,f = 0 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min ICCZZ Snooze mode standby current ZZ > VDD - 0.2V 3 mA ICCZZ (L Version) Snooze mode standby current ZZ > VDD - 0.2V 800 A tZZS Device operation to ZZ ZZ > VDD - 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V 2tCYC 7 Max Unit ns PRELIMINARY CY7C1326 Capacitance[6] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V Max. Unit 6 pF 8 pF 8 pF AC Test Loads and Waveforms R=317 3.3V OUTPUT OUTPUT Z0 =50 RL =50 ALL INPUT PULSES 3.0V 5 pF R=351 GND VL = 1.5V (a) INCLUDING JIG AND SCOPE (b) Note: 6. Tested initially and after any design or process changes that may affect these parameters. 7. Input waveform should have a slew rate of 1V/ns. 8 [7] PRELIMINARY CY7C1326 Switching Characteristics Over the Operating Range[8,9,10] -166 Parameter Description tCYC Clock Cycle Time tCH Min. -133 Max. Min. -117 Max. Min. -100 Max. Min. Max. Unit 6 7.5 8.5 10 ns Clock HIGH 1.7 1.9 2.5 3.5 ns tCL Clock LOW 1.7 1.9 2.5 3.5 ns tAS Address Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 2.0 2.0 2.0 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES BWE, GW, BW[1:0] Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tWEH BWE, GW, BW[1:0] Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2.0 2.5 2.5 2.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCES Chip Select Set-Up 2.0 2.5 2.5 2.5 ns tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCHZ Clock to High-Z [9, 10] Clock to Low-Z tEOHZ OE HIGH to Output High-Z[9, 10] tEOV 0 OE LOW to Output Low-Z OE LOW to Output Valid 4 3.5 [9, 10] tCLZ tEOLZ 3.5 [9, 10] 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 5.5 3.5 3.5 0 [9] 4.5 0 3.5 ns ns ns 3.5 ns 6 ns 3.5 ns Notes: 8. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL /IOH and load capacitance. Shown in (a) and (b) of AC test loads. 9. t CHZ, t CLZ, tEOV, t EOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 10. At any given voltage and temperature, tEOHZ is less than tEOLZ and t CHZ is less than tCLZ. 9 PRELIMINARY CY7C1326 Switching Waveforms Write Cycle Timing Single Write Burst Write Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC tADVS tADH ADV tAS ADD tADVH WD1 WD3 WD2 tAH GW tWH tWS WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE 2 CE2 CE3 tCES tCEH OE tDH tDS DataIn High-Z 1a 1a 2a 2b 2c 2d WE is the combination of BWE & BWx to define a write cycle (see Write Cycle Descriptions table). = UNDEFINED = DON'T CARE 10 3a High-Z PRELIMINARY CY7C1326 Switching Waveforms (continued) Read Cycle Timing Single Read tCYC Burst Read Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE tCEH tDOE tEOHZ tDOH DataOut tCO 1a 1a 2a 2b 2c 2c 2d 3a tCLZ tCHZ WE is the combination of BWE & BWx to define a write cycle (see Write Cycle Descriptions table). = DON'T CARE = UNDEFINED 11 PRELIMINARY CY7C1326 Switching Waveforms (continued) Read/Write Cycle Timing Single Read tCYC Single Write Unselected Burst Read tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC tADVS tADH ADV tAS ADD tADVH RD1 WD2 RD3 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 CE2 tCES tCEH CE3 tCES tDOE tCEH OE tEOHZ DataIn/Out tEOLZ tCO 1a 1a Out 2a In tDS See Note. 2a Out tDH 3a Out tDOH 3b Out WE is the combination of BWE & BWx to define a write cycle (see Write Cycle Descriptions table). = DON'T CARE = UNDEFINED Note: Write data forwarded to outputs on read immediately following a write. 12 3c Out 3d Out tCHZ PRELIMINARY CY7C1326 Switching Waveforms (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD C B A E D F G H tADH tADS ADSP ADSC ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data Q(A) In/Out Q(B) Q(C) D (E) Q(D) D (F) D (G) D (H) D(C) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWS[1:0] and GW to define a write cycle (see Write Cycle Descriptions table). CE is the combination of CE 2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON'T CARE 13 = UNDEFINED PRELIMINARY CY7C1326 Switching Waveforms (continued) ZZ Mode Timing [11,12] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ ICC tZZS ICC(active) ICCZZ tZZREC I/Os Three-state Note: 11. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device. 12. I/Os are in three-state when exiting ZZ sleep mode. 14 PRELIMINARY CY7C1326 Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 166 CY7C1326-166AC A101 100-Lead Thin Quad Flat Pack Commercial 166 CY7C1326L-166AC A101 100-Lead Thin Quad Flat Pack Commercial 133 CY7C1326-133AC A101 100-Lead Thin Quad Flat Pack Commercial 133 CY7C1326L-133AC A101 100-Lead Thin Quad Flat Pack Commercial 117 CY7C1326-117AC A101 100-Lead Thin Quad Flat Pack Commercial 117 CY7C1326L-117AC A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1326-100AC A101 100-Lead Thin Quad Flat Pack Commercial 100 CY7C1326L-100AC A101 100-Lead Thin Quad Flat Pack Commercial Document #: 38-00720 Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.