X28HC64
1
64K X28HC64 8K x 8 Bit
5 Volt, Byte Alterable E2PROM
© Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
3857-3.0 2/24/99 T1/C0/D0 EW
FEATURES
•70ns Access Time
•Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or VPP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
•Low Power CMOS
—40 mA Active Current Max.
—200 µA Standby Current Max.
•Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32µs Typical
•Software Data Protection
•End of Write Detection
—DATA Polling
—Toggle Bit
PIN CONFIGURATIONS
3857 FHD F03
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4321323130
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
X28HC64
LCC
PLCC
A7
A12
NC
NC
VCC
WE
NC
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3857 ILL F22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28HC64
A3
A4
A5
A6
A7
A12
NC
NC
VCC
NC
WE
NC
A8
A9
A11
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
TSOP
3857 FHD F02.1
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
X28HC64
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
•High Reliability
—Endurance: 1 Million Cycles
—Data Retention: 100 Years
•JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and enabling
the entire memory to be typically written in 0.25 seconds.
The X28HC64 also features DATA Polling and Toggle Bit
Polling, two methods providing early end of write detec-
tion. In addition, the X28HC64 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PGA
X28HC64
11I/O010
A014
VSS
9A18A2
7A36A4
5A52A12 28
VCC
12
I/O113
I/O215
I/O3
4A63A71NC
16
I/O4
20
CE
22
OE
24
A9
17
I/O5
27
WE
19
I/O7
21
A10
23
A11
25
A8
18
I/O6
26
NC
BOTTOM VIEW
3857 FHD F04
2
X28HC64
PIN DESCRIPTIONS
Addresses (A0–A12)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28HC64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
PIN NAMES
Symbol Description
A0–A12 Address Inputs
I/O0–I/O7Data Input/Output
WE Write Enable
CE Chip Enable
OE Output Enable
VCC +5V
VSS Ground
NC No Connect 3857 PGM T01
3857 FHD F01
X BUFFERS
LA TCHES AND
DECODER
I/O BUFFERS
AND LATCHES
Y BUFFERS
LA TCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
65,536-BIT
E2PROM
ARRAY
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
VCC
VSS
A0–A12
ADDRESS
INPUTS
WE
FUNCTIONAL DIAGRAM
X28HC64
3
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC64 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either CE or WE, which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
2ms.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28HC64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each succes-
sive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28HC64,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O7 (i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O6 will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Figure 1. Status Bit Assignment
3857 FHD F11
5TBDP 43210I/O
RESERVED
TOGGLE BIT
DATA POLLING
4
X28HC64
DATA Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
3857 FHD F13
WRITE DATA
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO7
COMPARE?
READY
NO
YES
WRITES
COMPLETE? NO
YES
Figure 3. DATA Polling Software Flow
DATA POLLING I/O7
Figure 2. DATA Polling Bus Sequence
3857 FHD F12
CE
OE
WE
I/O7X28HC64
READY
LAST
WRITE
HIGH Z VOL
VIH
A0–A12 An An An An An An
VOH
An
X28HC64
5
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
3857 FHD F15
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
READY
COMPARE
OK?
NO
YES
LAST WRITE
3857 FHD F14
CE
OE
WE
I/O6X28HC64
READY
VOH
VOL
LAST
WRITE
HIGH Z
* Beginning and ending state of I/O6 will vary.
**
6
X28HC64
HARDWARE DATA PROTECTION
The X28HC64 provides two hardware features that
protect nonvolatile data from inadvertent writes.
• Default VCC Sense—All write functions are inhibited
when VCC is 3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC64 offers a software controlled data protec-
tion feature. The X28HC64 is shipped from Xicor with
the software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once VCC was stable.
The X28HC64 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28HC64
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data. Once the page load cycle has been completed, the
device will automatically be returned to the data pro-
tected state.
X28HC64
7
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
3857 FHD F16
Figure 7. Write Sequence for
Software Data Protection Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used, the X28HC64 will automatically dis-
able further writes unless another command is issued to
deactivate it. If no further commands are issued the
X28HC64 will be write protected during power-down
and after any subsequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3857 FHD F17
CE
WE
(VCC)
WRITE
PROTECTED
VCC
0V
DATA
ADDR AA
1555 55
0AAA A0
1555
≤tBLC MAX
WRITES
OK
BYTE
OR
PAGE
tWC
WRITE LAST
BYTE TO
LAST ADDRESS
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA A0
TO ADDRESS
1555
WRITE DATA XX
TO ANY
ADDRESS
AFTER tWC
RE-ENTERS DATA
PROTECTED STATE
WRITE DATA AA
TO ADDRESS
1555
BYTE/PAGE
LOAD ENABLED
OPTIONAL BYTE
OR PAGE WRITE
ALLOWED
8
X28HC64
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
Figure 9. Software Sequence to
Deactivate Software Data Protection In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an E2PROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After tWC,
the X28HC64 will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
3857 ILL F18.2
CE
WE
STANDARD
OPERATING
MODE
Vcc
DATA
ADDR AA
1555 55
0AAA 80
1555 ≥tWC
AA
1555 55
0AAA 20
1555
WRITE DATA 55
TO ADDRESS
0AAA
3857 ILL F19.2
WRITE DATA 55
TO ADDRESS
0AAA
WRITE DATA 80
T O ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
WRITE DATA 20
T O ADDRESS
1555
WRITE DATA AA
TO ADDRESS
1555
X28HC64
9
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
Because the X28HC64 has two power modes, standby
and active, proper decoupling of the memory array is of
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
quency ceramic capacitor be used between VCC and
VSS at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for each
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Normalized ICC(RD) by Temperature
Over Frequency Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.2
0.8
0.4
0.6
0.2
1.0
01020
- 55°C
+ 25°C
ICC RD
NORMALIZED (mA)
FREQUENCY (MHz)
3857 FHD F20.1
+ 125°C
5.5 VCC 1.4
1.2
0.8
0.4
0.6
0.2
1.0
01020
ICC RD
NORMALIZED (mA)
FREQUENCY (MHz)
3857 FHD F21.1
4.5 VCC
5.0 VCC
5.5 VCC
10
X28HC64
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
X28HC64 ..................................... –10°C to +85°C
X28HC64I, X28HC64M ............. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS .......................................–1V to +7V
D.C. Output Current .............................................5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C +70°C
Industrial –40°C +85°C
Military –55°C +125°C
3857 PGM T02.1
Supply Voltage Limits
X28HC64 5V ±10%
3857 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Typ.(1) Max. Units Test Conditions
ICC VCC Current (Active) 15 40 mA CE = OE = VIL, WE = VIH, All
(TTL Inputs) I/O’s = Open, Address Inputs =
TTL Levels @ f = 10 MHz
ISB1 VCC Current (Standby) 1 2 mA CE = VIH, OE = VIL
(TTL Inputs) All I/O’s = Open, Other Inputs = VIH
ISB2 VCC Current (Standby) 100 200 µA CE = VCC – 0.3V, OE = GND
(CMOS Inputs) All I/O’s = Open, Other Inputs =
VCC – 0.3V
ILI Input Leakage Current ±10 µA VIN = VSS to VCC
ILO Output Leakage Current ±10 µA VOUT = VSS to VCC, CE = VIH
VlL(2) Input LOW Voltage –1 0.8 V
VIH(2) Input HIGH Voltage 2 VCC + 1 V
VOL Output LOW Voltage 0.4 V IOL = 5mA
VOH Output HIGH Voltage 2.4 V IOH = –5mA 3857 PGM T04.2
Notes: (1) Typical values are for TA = 25°C and nominal supply voltage
(2) VIL min. and VIH max. are for reference only and are not tested.
X28HC64
11
ENDURANCE AND DATA RETENTION
Parameter Min. Max. Unit
Minimum Endurance 100,000 Cycles
Data Retention 100 Years
3857 PGM T05.3
POWER-UP TIMING
Symbol Parameter Typ. (1) Units
tPUR(3) Power-up to Read Operation 100 µs
tPUW(3) Power-up to Write Operation 5 ms 3857 PGM T06
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol Parameter Max. Units Test Conditions
CI/O(3) Input/Output Capacitance 10 pF VI/O = 0V
CIN(3) Input Capacitance 6 pF VIN = 0V
3857 PGM T07.1
A.C. CONDITIONS OF TEST
Input Pulse Levels 0V to 3V
Input Rise and
Fall Times 5ns
Input and Output
Timing Levels 1.5V
3857 PGM T08.1
MODE SELECTION
CE OE WE Mode I/O Power
L L H Read DOUT Active
L H L Write DIN Active
H X X Standby and High Z Standby
Write Inhibit
X L X Write Inhibit — —
X X H Write Inhibit — —
3857 PGM T09
Note: (3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
3857 FHD F22.3
5V
1.92KΩ
30pF
OUTPUT
1.37KΩ
12
X28HC64
Read Cycle Limits
X28HC64-70 X28HC64-90 X28HC64-12
–55°C to +125°C –55°C to +125°C –55°C to +125°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tRC Read Cycle Time 70 90 120 ns
tCE Chip Enable Access Time 70 90 120 ns
tAA Address Access Time 70 90 120 ns
tOE Output Enable Access Time 35 40 50 ns
tLZ(4) CE LOW to Active Output 0 0 0 ns
tOLZ(4) OE LOW to Active Output 0 0 0 ns
tHZ(4) CE HIGH to High Z Output 30 30 30 ns
tOHZ(4) OE HIGH to High Z Output 30 30 30 ns
tOH Output Hold from 0 0 0 ns
Address Change 3857 PGM T10.1
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read Cycle
3857 FHD F05
Notes: (4) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the
point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
tCE
tRC
ADDRESS
CE
OE
WE
DATA VALID DATA VALID
tOE
tLZ
tOLZ
tOH
tAA
tHZ
tOHZ
DATA I/O
VIH
HIGH Z
X28HC64
13
WRITE CYCLE LIMITS
Symbol Parameter Min. Typ.(1) Max. Units
tWC(5) Write Cycle Time 2 5 ms
tAS Address Setup Time 0 ns
tAH Address Hold Time 50 ns
tCS Write Setup Time 0 ns
tCH Write Hold Time 0 ns
tCW CE Pulse Width 50 ns
tOES OE HIGH Setup Time 0 ns
tOEH OE HIGH Hold Time 0 ns
tWP WE Pulse Width 50 ns
tWPH(6) WE HIGH Recovery 50 ns
tDV(6) Data Valid 1 µs
tDS Data Setup 50 ns
tDH Data Hold 0 ns
tDW(6) Delay to Next Write 10 µs
tBLC Byte Load Cycle 0.15 100 µs
3857 PGM T11.2
WE Controlled Write Cycle
3857 FHD F06
Notes: (5) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
(6) tWPH and tDW are periodically sampled and not 100% tested.
ADDRESS
tAS
tWC
tAH
tOES
tDV
tDS tDH
tOEH
CE
WE
OE
DATA IN
DATA OUT HIGH Z
DATA VALID
tCS tCH
tWP
14
X28HC64
CE Controlled Write Cycle
3857 FHD F07
Page Write Cycle
3857 FHD F08
Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
ADDRESS
tAS
tOEH
tWC
tAH
tOES
tCS
tDV
tDS tDH
tCH
CE
WE
OE
DATA IN
DATA OUT HIGH Z
tCW
DATA VALID
WE
OE
(7)
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
tWP
tWPH
tBLC
tWC
CE
ADDRESS *
(8)
I/O
*For each successive write within the page write operation, A6–A12 should be the same or
writes to an unknown address could occur.
LAST BYTE
X28HC64
15
DATA Polling Timing Diagram(9)
3857 FHD F09
CE
OE
WE
I/O6
tOES
tDW
tWC
tOEH
HIGH Z *
*
* I/O6 beginning and ending state will vary, depending upon actual tWC.
ADDRESS An
DIN=X DOUT=X DOUT=X
tWC
tOEH tOES
An An
CE
WE
OE
I/O7
tDW
Toggle Bit Timing Diagram(9)
3857 FHD F10
Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
16
X28HC64
0.020 (0.51)
0.016 (0.41)
0.150 (3.81)
0.125 (3.17)
0.610 (15.49)
0.590 (14.99)
0.110 (2.79)
0.090 (2.29)
1.460 (37.08)
1.400 (35.56)
1.300 (33.02)
REF.
PIN 1 INDEX
0.160 (4.06)
0.125 (3.17)
0.030 (0.76)
0.015 (0.38)
3926 FHD F04
PIN 1
SEATING
PLANE
0.062 (1.57)
0.050 (1.27)
0.550 (13.97)
0.510 (12.95)
0.085 (2.16)
0.040 (1.02)
0°
15°
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
TYP. 0.010 (0.25)
PACKAGING INFORMATION
X28HC64
17
PACKAGING INFORMATION
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
1.30 (33.02)
REF.
0.026 (0.66)
0.014 (0.36)
TYP. 0.018 (0.46)
0.225 (5.72)
0.140 (3.56)
0.060 (1.52)
0.015 (0.38)
3926 FHD F08
PIN 1
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.070 (1.78)
0.030 (0.76)
TYP. 0.055 (1.40)
0.610 (15.49)
0.500 (12.70)
0.100 (2.54)
0.035 (0.89)
TYP. 0.010 (0.25) 0°
15°
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
1.490 (37.85)
1.435 (36.45)
18
X28HC64
PACKAGING INFORMATION
0.021 (0.53)
0.013 (0.33)
0.420 (10.67)
0.050 (1.27) TYP.
TYP. 0.017 (0.43)0.045 (1.14) x 45°
0.300 (7.62)
REF.
0.453 (11.51)
0.447 (11.35)
TYP. 0.450 (11.43)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
PIN 1
0.400
(10.16)REF.
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
3° TYP.
0.048 (1.22)
0.042 (1.07)
0.140 (3.56)
0.100 (2.45)
TYP. 0.136 (3.45)
0.095 (2.41)
0.060 (1.52)
—
0.015 (0.38)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
3926 FHD F13
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
X28HC64
19
0.2980 (7.5692)
0.2920 (7.4168) 0.4160 (10.5664)
0.3980 (10.1092)
0.0192 (0.4877)
0.0138 (0.3505)
0.0160 (0.4064)
0.0100 (0.2540)
0.050 (1.270)
BSC
0.7080 (17.9832)
0.7020 (17.8308)
0.0110 (0.2794)
0.0040 (0.1016)
0.1040 (2.6416)
0.0940 (2.3876)
0.0350 (0.8890)
0.0160 (0.4064)
0.0125 (0.3175)
0.0090 (0.2311)
0° – 8°
X 45°
3926 FHD F17
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3. BACK EJECTOR PIN MARKED “KOREA”
4. CONTROLLING DIMENSION: INCHES (MM)
SEATING PLANE
BASE PLANE
PACKAGING INFORMATION
20
X28HC64
0.150 (3.81) BSC
0.300 (7.62)
BSC
0.458 (11.63)
––
0.458 (11.63)
0.442 (11.22)
PIN 1
0.400 (10.16)
BSC
0.560 (14.22)
0.540 (13.71)
3926 FHD F14
0.020 (0.51) x 45° REF.
0.095 (2.41)
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.040 (1.02) x 45° REF.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.028 (0.71)
0.022 (0.56)
(32) PLCS.
0.200 (5.08)
BSC
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
0.120 (3.05)
0.060 (1.52)
PIN 1 INDEX CORDER
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
PACKAGING INFORMATION
X28HC64
21
PACKAGING INFORMATION
0.561 (14.25)
0.541 (13.75)
3926 FHD F15
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.020
0.016
12 13 15 17 18
11 10 14 16 19
9 8 20 21
7 6 22 23
5 2 28 24 25
4312726
TYP. 0.100
ALL LEADS 0.080
0.070 4 CORNERS
PIN 1 INDEX
0.660 (16.76)
0.640 (16.26)
0.100
0.080
0.072
0.061
0.185 (4.70)
0.175 (4.44)
0.050
0.008
A
A
A
A
NOTE: LEADS 4,12,18 & 26
0.080
0.070
22
X28HC64
PACKAGING INFORMATION
3926 FHD F16
28-LEAD CERAMIC FLAT PACK
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
0.740 (18.80)
MAX.
0.019 (0.48)
0.015 (0.38)
0.050 (1.27) BSC
0.045 (1.14) MAX.
PIN 1 INDEX
128
0.130 (3.30)
0.090 (2.29)
0.045 (1.14)
0.025 (0.66)
0.180 (4.57)
MIN.
0.006 (0.15)
0.003 (0.08)
0.030 (0.76)
MIN.
0.370 (9.40)
0.250 (6.35)
TYP. 0.300 2 PLCS.
0.440 (11.18)
MAX.
X28HC64
23
PACKAGING INFORMATION
3926 ILL F38.1
8.02 (0.315)
7.98 (0.314)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
0.26 (0.010)
0.14 (0.006)
0.50 (0.0197) BSC
0.58 (0.023)
0.42 (0.017) 14.15 (0.557)
13.83 (0.544)
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
SEATING
PLANE
SEE NOTE 2
SEE NOTE 2
0.50 ± 0.04
(0.0197 ± 0.0016)
0.30 ± 0.05
(0.012 ± 0.002)
14.80 ± 0.05
(0.583 ± 0.002)
1.30 ± 0.05
(0.051 ± 0.002)
0.17 (0.007)
0.03 (0.001)
TYPICAL
32 PLACES 15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
SOLDER PADS
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
24
X28HC64
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
ORDERING INFORMATION
Device Access Time
–70 = 70ns
–90 = 90ns
–12 = 120ns
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
S = 28-Lead Plastic SOIC
E = 32-Pad LCC
K = 28-Lead Pin Grid Array
F = 28-Lead Flat Pack
T = 32-Lead TSOP
X28HC64 X X -X
