ADC3511/ADC3711 National Semiconductor PRELIMINARY ADC3511 31,,-Digit Microprocessor Compatible A/D Converter ADC3711 3%/,-Digit Microprocessor Compatible A/D Converter General Description The ADC3511 and ADC3711 (MM74C937, MM74C938-1) monolithic A/D converter circuits are manufactured using standard complementary MOS (CMOS) technology. A pulse modulation analog-to-digital conversion technique is used and requires no external precision components. In addition, this technique allows the use of a reference voltage that is the same polarity as the input voltage. One 5V (TTL) power supply is required. Operating with an isolated supply allows the conversion of positive as well as negative voltages. The sign of the input voltage is automati- cally determined and indicated on the sign pin. If the power supply is not isolated, only one polarity of voltage may be converted. The conversion rate is set by an internal oscillator. The fre- quency of the oscillator can be set by an external RC net- work or the oscillator can be driven from an external fre- quency source. When using the external RC network, a square wave output is available. The ADC3511 and ADC3711 have been designed to pro- vide addressed BCD data and are intended for use with microprocessors and other digital systems. BCD digits are selected on demand via 2 Digit Select (DO, D1) inputs. Digit Select inputs are latched by a low-to-high transition on the Digit Latch Enable (DLE) input and will remain latched as long as DLE remains high. A start conversion input and a conversion complete cutput are included on both the ADG3511 and the ADC3711. Features uw Operates from single 5V supply @ ADC35114 converts 0 to +1999 counts ADC3711 converts 0 to +3989 counts Addressed BCD outputs No external precision components necessary Easily interfaced to microprocessors or other digital systems Medium speed200 ms/conversion TTL compatible Internal clock set with RC network or driven externally Overtlow indicated by hex EEEE output reading as well as an overflow output g ADC3511 equivalent to MM74C937 @ ADC3711 equivalent to MM74C938-1 Applications mw Low cost analog-to-digital converter @ Eliminate analog multiplexing by using remote A/D converters @ Convert analog transducers (temperature, pressure, dis- placement, etc.) to digital transducers Connection Diagram Dual-In-Line Package Vec 4 ) 24 2! ANALOG Veg -~4 23 oo 2 J 22 Vg5 aa zt a OVERFLOW #u. 20 CONVERSION COMPLETE pa DLE START CONVERSION 4 ee tour SIGN 4 te fm VFSLTER + pe Vaer vn) HS eat Order Number ADC3511CCN vl or ADC3711CCN im p34 NS Package N24A veg tt 3. ANALOG GND TOP VIEW TUH/5678~1 3-250Absolute Maximum Ratings (note 1) If Milltary/Aerospace specified devices are required, Absolute Maximum Voc 6.5V please contact the National Semiconductor Sales Storage Temperature Range 65C to + 150C Office/ Distributors for availability and specifications. Lead Temp. (Soldering, 10 seconds) 260C Voitage at Any Pin 0.3V to Voc +0.3V ESD Susceptibility (Note 5) TBD V Operating Temperature Range (Ta) 40C to + 85C Package Dissipation at Ts, = 25C 500 mw Operating Vcc Range 4.5V to 6.0V DC Electrical Characteristics aocas5110c, apc371100 4.75N <Vccs5.25V, 40C<T,< +885C, unlass otherwise specified. Symbol Parameter Conditions Min Typ Max Units (Note 2) Vinq) Logical '1" Input Voltage Voc1.5 Vv (Except fin) VIN(O) Logical 0 Input Voltage 1.5 Vv {Except fipy) VIN(1) Logical 1 Input Voltage Voc 0.6 Vv (fin) Vino) Logical 0 Input Voltage 0.6 Vv (fin) Voutt) Logical 1 Output Voltage Ip =9360 pA Voc0.4 Vv {Except 20, 21, 22, 23) Vouta) Logical 1 Output Voltage lo=360 pA Voc 1.0 Vv (20, 21, 22, 23) Vourio) Logicat 0 Output Voltage Ilo=1.6 mA 0.4 Vv iN) Logical 1 Input Current Vin= Voc 0.005 1.0 pA (SC, DLE, DO, D1) lino) Logical 0 Input Current Vin = OV 1.0 0.005 pA (SC, DLE, BO, D1) loc Supply Current Ail Outputs Open 0.5 5.0 mA AC Electrical Characteristics aoc35110c, anc3711c Voc= 5V; Ta=25C, C_ =50 pF; t;=ts= 20 ns; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units (Note 2) fosc Oscillator Frequency 0.6/RC Hz fin Clock Frequency 100 640 kHz fconv Conversion Rate ADG35110C fin/64,512 conversions/sec ADC37110C fin 129,024 conversions/sec tscpw Start Conversion Pulse Width 200 DG ns todo, tod Propagation Delay DLE=0V 2.0 5.0 ps DO, 01, to 20, 21, 22, 23 tpdo> tods Propagation Delay 2.0 5.0 BS DLE to 20, 21, 22, 23 {SET-UP Set-Up Time tHOLD = 0 ns 100 200 ns DO, D1, to DLE tpwoLe Minimum Pulse Width 100 200 ns Digit Latch Enable (Low) 3-261 LL ZEOOV/LLSEOaVADC3511/ADC3711 Converter Characteristics apc35110, aDC37116C 4.75<Vcc<5.25V; 40C<Ta< + 85C, fe = 5 conv./sec (ADC3511CC); 2.5 conv./sec (ADC3711CC); unless otherwise specified. Typ Symbol Parameter Conditions Min (Note 2) Max Units Non-Linearity Vin = 0-2V Full Scale 0.05 +0.025 +0.05 % of Full-Scale Vin = 0-200 mV Full Scaie (Note 3) Quantization Error -1 +0 Counts Offset Error Vin=0V -0.5 +1.0 +3.0 mV (Note 4) Rollover Error 0 +0 Counts Vin+> VIN Analog Input Current Ta=25C 5 +1 +5 nA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its spacified operating conditions. Note 2: All typicals are given for Ta = 25C. Note 3: For the ADC3511CC: full-scale= 1898 counts; therefore 0.025% of full-scale=1/, count and 0.05% of full-scala=1 count. For the ADC3711CC: full scale= 3999 counts; therefore 0.025% of full-scale= 1 count and 0.05% of full-scale= 2 count. Note 4: For full-scale = 2.000: 1 mV=1 count for the ADC3511CC; 1 m=2 counts for the ADC3711CC. Note 5: Human body model, 100 pF discharged through a 1.59 resistor. Block Diagram ADC3511 3 1,-Digit A/D (*ADC3711 3 34-Digit A/D) 31/2 (3. 3/4)-DIGIT LATCH START CONV ROM BCD OECODER FREQIN DIGITAL TIMING AND CONTROL 2p co 16 FREQ OUT secooen) | LATCH OLE COMPARATOR TIMING OVERFLOW RON GND P vgs OVERFLOW CONV COMPLETE SIGN *VAEF DIGITAL Vog ANALOG Vice VEILTER Vin COMPARATOR swe Vin ~VREF Vee TL/H/5678-2 3-252by Applications Information 8 THEORY OF OPERATION a A schematic for the analog loop is shown in Figure 1. The The DC value of this pulse train is: = output of SW1 is either at Vper or zero volts, depending on ton > the state of the D flip-flop. If Q is at a high level, Vout = VREF;_, = Vrer (duty cycle) o Vear=, i _ ss unit. ton + torr OUT= Vrer and if Q is at a low level Vout =OV. This volt ' . Pa age is then applied to the low pass filter comprised of R1 The lowpass filter will pass the DC value and then: ~ and C1. The output of this filter, Vep, is connected to the Vep=Vrer (duty cycle) = negative input of the comparator, where it is compared to Since the closed loop system will always force Vez to equal the analog input voltage, Vix. The output of the comparator Vin. we can then say that: is connected to. the D input of the D flip-flop. information is =Veg=V then transferred from the D input to the Q@ and Q outputs on Vin= Vre=Vrer (duty cycle) the positive edge of clock. This loop forms an oscillator or whose duty cycle is precisely related to the analog input ViN = voltage, Vin. VREF {duty cycle) An example will demonstrate this relationship. Assume the The duty cycle is logically ANDed with the input frequency input voltage is equal to 0.500V. If the Q output of the D flip- fix. The resultant frequency f equals: flop is high than Vouz will equal Var (2.000V) and Vea will f= (duty cycle) x (fin) charge toward 2V with a time constant equal to R1C1. At F fi lated b t 14 time d some time Veg will exceed 0.500V and the comparator out- i sind w 's on or ne a > The coun n ontai od a time er put will switch to OV. At the next clock rising edge the Q ermin COURSE nO. . The count contained in counter output of the D flip-flop will switch to ground, causing Vout no. 1 is then: to switch to OV. At this time, Veg will start discharging (count) = _ (duty cycle) x (fin) toward OV with a time constant R1C1. When Veg is less (f\y)/N (fin)/N than 0.5V the comparator output will switch high. On the VIN rising edge of the next clock the Q output of the D flip-flop = Vere xN will switch high and the process will repeat. There exists at REF the output of SW1 a square wave pulse train with positive For the ADC3511 N= 2000. amplitudes Vaer and negative amplitude OV. For the ADC3711 N=4000. Vind COMPARATOR D a -o> swt Rs 0 FLIP. FLOP As VREF tL. , f oF [| COUNTER NO. 1 (=) RESET y ) COUNTER NO. 2 (=2N) | TL/H/5678-3 Vin= Vee = Vrer X (duty cycle) t= (duty cycle) x fin _t _ {duty cycle) x fy = Vine Count in counter no. 1 = {hn)/N (hind/N VREF xN FIGURE 1. Analog Loop Schematic Pulse Modulation A/D Converter 3-253ADC3511/ADC3711 Applications Information (continued) GENERAL INFORMATION The timing diagram, shown in Figure 2, gives operation for the free running mode. Free running operation is obtained by connecting the Start Conversion input to logic 1 (Vcc). In this mode the analog input is continuously converted and the digit latches are updated at a rate equal to 64,512 x 1/fiy for tha ADC3511, or 129,024 for the ADC3711. The rising edge of the Conversion Compiete output indi- cates that new information has been transferred from the internal counter to the digit latches. This information will re- main in the digit latches until the next low-to-high transition of the Conversion Complete output. A iogic 1 will be main- tained on the Conversion Complete output for a time equal to 64X1/fjy on the ADC3511, or 128X1/fiy on the ADC3711. Figure 3 gives the operation using the Start Conversion in- put. It is important to note that the Start Conversion input and Conversion Complete output do not influence the actual analog-to-digital conversion in any way. Internally the ADG3511 and ADC93711 are always continuously converting the analog voltage present at their inputs. The Start Conver- sion input is used to control the transfer of information from the internal counter to the digit latches. An RS latch on the Start Conversion input allows a broad range of input pulse widths to be used on this signal. As shown in Figure 3, the Conversion Complete output goes to a logic 0 on the rising edge of the Start Conversion pulse and goes to a logic 1 some time later when tha new con- version is transferred from the internal counter to the dis- play latch. Since the Start Conversion pulse can occur at any time during the conversion cycle, the amount of time from Start Conversion to Conversion Complete will vary. The maximum time is 64,512 < 1/fiy (129,024 < 1/fin for the ADC3711) and the minimum time is 256 X 1/fin (512 x 1/4) for tha ADC371 1). SYSTEM DESIGN CONSIDERATIONS The ADC3511 and ADC3711 have reduced the problem of high resolution, high accuracy analog-to-digital conversion to nearly the favel of simplicity, economy, and compactness usually associated with digital logic circuitry. However, they are truly high precision analog devices, and require the same kind of design considerations given to all analog cir- cuits. While great care has been taken in the design of the ADC3511 and ADC3711 to make their application as easy as possible, in order to utilize them to their full performance potential, good grounding, power supply distribution, decou- pling, and regulation techniques should be exercised. 64,512 x Win (129,028 x 1/f)y) 64,000 x 1/fyy (128,000 x 1/fjy) CONVERSION CYCLE (INTERNAL SIGNAL) 84,256 x 1/f\y 1128 542 x Wty) ei oI (128A) CONVERSION COMPLETE { 4 / NEW CONVERSION CONVERSION ENDS STARTS FIGURE 2. Conversion Cycle Timing Diagram for Free Running Operation (Times Shown In Parentheses are for the ADC3711) CONVERSION CYCLE (INTERNAL SIGNAL) stant 71 asd PLE U U CONVERSIO CONVERSION * 4 compcere | _ t TL/H/5678-4 FIGURE 3. Conversion Cycle Timing Diagram Operating with Start Conversion InputTruth Table DIGIT SELECT INPUTS SELECTED DIGIT DLE Di Do L L L Digit 0 (LSD) L L H Digit 1 L H L Digit 2 L H H Digit 3 (MSD) H X X Unchanged L = tow logic level H = high logic level X = irrelevant logic level The value of the Selected Digit is presented at the 29, 22, 21 and 20 outputs in BCD format. Note 1: If the value of a digit changes while it is selected, that change wil be reflected at the outputs. Note 2: An overflow condition will be indicated by a high level on the OVERFLOW output (pin 5) and E18 in all digits. Nete 3: The sign of the input voltage, when these devices ara operated in the bipolar made, is indicated by tha SIGN output (pin 8). A high level indicates a positive voltage, a low level a negative. Timing Diagrams Vec DLE GND Vee 00, of GND PHL PLA Von 23, 22,21 20 GND Typical Applications Figure 4 shows the ADC3511 and ADC3711 connected to convert 0 to +2.000 volts full scale operating from a non- isolated power supply. (Note that the ADC3511 converts 0 to +1999 counts full scale, while the ADC3711 converts 0 to +3999 counts full scale.) In this configuration the SIGN output (pin 8) should be ignored. Higher voltages can, of course, be converted by placing fixed dividers in the inputs, while lower voltages can be converted by placing fixed di- viders in the feedback loop, as shown in Figure 6. Figures & and 6 show systems operating with isolated sup- plies that will convert both polarities of inputs. 66 Hz com- mon-mode noise can become a problem in these config- TL/H/5678-5 urations, so shielded transformers have been shown in the figures. The necessity for, and the type of shielding needed depends on the performance requirements, and the actual applications. The filter capacitors connected to Veg (pin 12) and Vritter (pin 11} should be of a low leakage variety. In tha exampies shawn every 1.0 nA of leakage will cause approximately 0.1 MV error (1.0 109A x 100 kN. =0.1 mV). If the currents in both capacitors are exactly equal however, little arror will result since the source impedances driving both capacitors are approximately matched. 3-255 LLZE0dV/LLSEOdY(a79g |INZ SHOA OO0'Z + S}UNOD BEGE + a/v NB5IG-"% ) B[BIS [IN SUOA OOO'S + SIUNOD 666l + a/v uSIG-% "P FUND! 3-256 8-829S/H/1L aq ONS WHOIS ano > reps SHIH fg \' / c 3L0N USS F mui 'Y F GION sive soyoedes ebeyee| MO] - SION %OL F ssopowdwo ily = SION poyioeds es!wueyjO ssejUn 9,4 F , pue eM 1, SIOISise) Ify ?L LON wez 2 < annoyo r-T4 r 7 SO 1VNY a4, ro | 4 zMS (+)NI | ms $<T | | q <= 3108 | | | | Las (INIA | aveva > | wot | ]o t d3YQ UAL, Nila 4OOL | isnray | [ | wy nals pi3s40 J | 1nd, NOISH3AND2 LUVLS 31L374W09 | [ a0 NOISH3ANO9 | oa MO1443A0 _ z 3 | [ a (aueczavy =F 3 o01seoay = { ne | 5S, ze Cc & | I o% 33, SO 1VNY e - JONAH 3SIY AZ a 2 30a0) it td @ = _ AS > a z | 6 aA l vv y Vv Oo 31000 1G gz 2 22 gz 2 eee a. m = Zz e.:] << a - m 3 z = me So zz Luwis > LL Z00V/LLSEO0VADC3511/ADC3711 (2189S JIN4 SOA OO0'Z F S}UNOD 666E F 'a/V 16Id-% ) a]B9S |IN4 SOA 00'S F SYUNOD G66! F a/v NBIG-% s AUNDIA 9-8295/H/TL \ / 310" sive annoys rr 7 7 DOTWNY | ww | zs GNI, Aa (284 ZY + Ly l= D001 419 USEF = Cy cy a0N | LMS INI, NWA (-) Ni, uly aE Typical Applications (continued) sopoedes ofeyeo] MO] - SION % 01 FSIOWOEdED [Ny Z SION payioeds esiwueyjo ssqjun G7 PUB HEM 7%, SIOISISEN || 3]. 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