w Programmable Delay Units T? LL Interfaced senies:; PDU-713 data Way delay = devices a : aa 140 440 abo Features: MAX. on @ Digitally programmable in & delay steps. oe 010 . }+-.820 MAX. os 290 g@ Fits standard 14 pins DIP socket. MAX. 020 Input & outputs fully TTL interfaced & buffered. ibe > Hm Two (2) separate outputs; inverting & non-inverting. _ @ Precise and stable delays. | | | | | | | 020 m@ 10 7TL fan-out capability Equal Spaces @ .100 = .800 Specifications: coe : . ODRESS @ Input signal requirement: TTL fagic. poor # Output fan-out: TTL Schottky loads. +02 4 = Delay variation: Monotonic in one direction. @ Total programmed delay tolerance: 5% or 1 __ 10] 9{ al 6 ns whichever is greater. f ~ 7 # Inherent delay (Too): 14 ns on pin at typical oi4 411s on pin 5 Veco ";}_x 4 # Propagation delay: ' 4| L DELAY OUT Ot a _ Address to output (Tsva) ~ 12 ns typ. N BIGITA Poo GUT Enable to quiput (Tsue) = 12 ns typ. Grpo4 x | # Operating temperature: O to 70C. L 4 g Temperature coefficient: 100 PPM/C, a B Supply voltage Vee: 5VDG 5% nn m Power dissipation: 740 mw max. Incremental Part Dalay Total Selay* TRUTH TABLE Number Por Step Change Address (Bit Na.). pelay (r5) (ns) Enable a | ? 1 Out 1 = High PDU-743-.5 Bd a8 o 0 0 0 Ta o= Low PDOU-713-1 1 4 Q 0 0) ] Th = Dont care PRU Tides a "4 14 o Q 1 0 T: Ti Reference of POU-713-3 a oo 48 21 oO 0 1 \ T inherent debay of PDU-7413-5 5 og 45 circuit. PDLILT13.10 1 o- 0 70 o 1 0 0 Ts TiteT= Multiplier of PDU-713-15 48 405 0 1 0 1 T. incremental - Q ' 1 0 Ts. dalay, PDU-743-20 fo 00 15 140 0 1 1 1 T POU-743-40 4p 20 2aD p b 4 0 POU-719-50 oo 2 2.5 350 3 Mt. Prospect Avenue, | G4 "This delay value does nat include Ty delay. Clitton, New Jersey 07013 = (201) 773-2299 m@ FAX (201) 773-9672 @ TWX 710-989-7008