AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 DESCRIPTION The HCPL-3700 voltage/current threshold detection optocoupler consists of an AlGaAs LED connected to a threshold sensing input buffer IC which are optically coupled to a high gain darlington output. The input buffer chip is capable of controlling threshold levels over a wide range of input voltages with a single resistor. The output is TTL and CMOS compatible. FEATURES TRUTH TABLE * * * * (Positive Logic) AC or DC input Programmable sense voltage Logic level compatibility Threshold guaranteed over temperature (0C to 70C) * OptoplanarTM construction for high common mode immunity * UL recognized (file # E90700) APPLICATIONS * * * * * * Low voltage detection 5 V to 240 V AC/DC voltage sensing Relay contact monitor Current sensing AC/DC Microprocessor Interface POWER Industrial controls Input Output H L L H 8 1 8 1 A 0.1 F bypass capacitor must be connected between pins 8 and 5. AC RX HCPL-3700 GND 1 ABSOLUTE MAXIMUM RATINGS 8 LOGIC 1 1 8 VCC DC+ 2 7 NC DC- 3 6 VO AC 4 5 GND GND 2 (No derating required up to 70C) Parameter Symbol Value Units Storage Temperature TSTG -55 to +125 C Operating Temperature TOPR -40 to +85 C Lead Solder Temperature TSOL 260 for 10 sec C EMITTER Input Current Average 50 (MAX) Surge 3 ms, 120 Hz Pulse Rate Transient 10 s, 120 Hz Pulse Rate Input Voltage (Pins 2-3) IIN 140 (MAX) mA 500 (MAX) VIN -0.5 (MIN) V Input Power Dissipation (Note 1) PIN 230 (MAX) mW Total Package Power Dissipation (Note 2) PT 305 (MAX) mW IO 30 (MAX) mA VCC -0.5 to 20 V DETECTOR Output Current (Average) Supply Voltage (Pins 8-5) Output Voltage (Pins 6-5) Output Power Dissipation (Note 3) (Note 4) VO -0.5 to 20 V PO 210 (MAX) mW 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 ELECTRICAL CHARACTERISTICS Parameter (TA = 0C to 70C Unless otherwise specified) Test Conditions Input Threshold Current DC (Pins 2,3) Input Threshold Voltage AC (Pins 1,4) Hysteresis Input Clamp Voltage Input Current Bridge Diode Forward Voltage Logic Low Output Voltage Logic High Output Current Logic Low Supply Current Logic High Supply Current Input Capacitance (VIN = VTH+, VCC = 4.5 V) (VO = 0.4 V, IO ! 4.2 mA) (Note 5) (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO ! 4.2 mA) (VIN = V2 - V3, Pins 1 & 4 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO " 100 A) (VIN = #V1 - V4#) (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 0.4 V) (Note 5) (IO ! 4.2 mA) (VIN = #V1 - V4#) (Pins 2 & 3 Open) (VCC = 4.5 V, VO = 2.4 V) (Note 5) (IO " 100 A) (IHYS = ITH+ - ITH-) (VHYS = VTH+ - VTH-) (VIHC1 = V2 - V3, V3 = GND) (IIN = 10 mA, Pins 1 & 4 Connected to Pin 3) (VIHC2 = #V1 - V4#) (#IIN# = 10 mA) (Pins 2 & 3 Open) (VIHC3 = V2 - V3, V3 = GND) (IIN = 15 mA; Pins 1 & 4 Open) (VILC = V2 - V3, V3 = GND) (IIN = -10 mA) (VIN = V2 - V3 = 5.0 V) (Pins 1 & 4 Open) (IIN = 3 mA) (IIN = 3 mA) (VCC = 4.5 V; IOL = 4.2 mA) (Note 5) (Note 5) (VOH = VCC = 18 V) (V2 - V3 = 5.0 V; VO = Open) (VCC = 5 V) (VCC = 18 V; VO = Open) (f = 1 MHz; VIN = 0V) (Pins 2 & 3, Pins 1 & 4 Open) Symbol Min Typ Max Unit ITH+ 1.96 2.4 3.11 mA ITH- 1.00 1.2 1.62 mA VTH+ 3.35 3.8 4.05 V VTH- 2.01 2.5 2.86 V VTH+ 4.23 5.0 5.50 V VTH- 2.87 3.7 4.20 V IHYS VHYS 1.2 1.3 mA V VIHC1 5.4 6.3 6.6 V VIHC2 6.1 7.0 7.3 V VIHC3 12.5 13.4 V VILC -0.75 IIN 3.0 3.7 VD1,2 VD3,4 0.65 0.65 VOL 0.04 IOH V 4.4 mA V V 0.4 V 100 A ICCL 1.0 4 mA ICCH 0.01 4 A CIN 50 pF 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Operating Temperature Operating Frequency Symbol Min Max Units VCC 2 18 V TA 0 70 C f 0 4 kHz SWITCHING CHARACTERISTICS (TA = 25C, VCC = 5 V Unless otherwise specified) AC Characteristics Test Conditions Propagation Delay Time (RL = 4.7 k$, CL = 30 pF) (to Output Low Level) (Note 6) Propagation Delay Time (RL = 4.7 k$, CL = 30 pF) (to Output High Level) (Note 6) Symbol Min Typ Max Unit TPHL 6.0 15 s TPLH 25.0 40 s Output Rise Time (10-90%) (RL = 4.7 k$, CL = 30 pF) tr 45 s Output Fall Time (90-10%) (RL = 4.7 k$, CL = 30 pF) tf 0.5 s #CMH# 4000 V/s #CML# 600 V/s Common Mode Transient Immunity (at Output High Level) (IIN = 0 mA,RL = 4.7 k$) (VO min = 2.0 V, VCM = 1400 V) (Notes 7,8) Common Mode Transient Immunity (IN = 3.11 mA,RL = 4.7 k$) (at Output Low Level) (VO max = 0.8 V, VCM = 140 V) (Notes 7,8) PACKAGE CHARACTERISTICS Characteristics (TA = 0C to 70C Unless otherwise specified) Test Conditions Symbol Min VISO 2500 Typ Max Unit (Relative humidity < 50%) Withstand Insulation Voltage (TA = 25C, t = 1 min) VRMS (Notes 9,10) Resistance (input to output) (Note 9) (VIO = 500 Vdc) RI-O 1012 $ Capacitance (input to output) (f = 1 MHz, VIO = 0 Vdc) CI-O 0.6 pF 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 NOTES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Derate linearly above 70C free-air temperature at a rate of 1.8 mW/C. Derate linearly above 70C free-air temperature at a rate of 2.5 mW/C. Derate linearly above 70C free-air temperature at a rate of 0.6 mA/C. Derate linearly above 70C free-air temperature at a rate of 1.9 mW/C. Logic low output level at pin 6 occurs when VIN!VTH+ and when VIN%VTH- once VIN exceeds VTH+. Logic high output level at pin 6 occurs when VIN"VTH- and when VIN&VTH+ once VIN decreases below VTH-. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 s rise time) to the 1.5 V level on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output pulse. (Refer to Fig. 9) Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO%2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO&0.8 V). (Refer to Fig.10) In applications where dVcm/dt may exceed 50,000 V/s (Such as static discharge), a series resistor, RCC, should be included to protect the detector chip from destructive surge currents. The recommended value for RCC is 240 $ per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240 $. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. The 2500 VRMS/1 min. capability is validated by a 3.0 kVRMS/1 sec. dielectric voltage withstand test. AC voltage is instantaneous voltage. All typicals at TA = 25C, VCC = 5 V unless otherwise specified. 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 Fig. 2 Input Current vs. Input Voltage 4.0 50 3.5 45 DC (Pins 1,2 shorted together pins 3,4 shorted together) 40 IIN - INPUT CURRENT (mA) 3.0 2.5 2.0 1.5 1.0 30 25 20 15 10 5 0 0.5 AC (pins 2 & 3 Open) -5 0.0 -10 6 8 10 12 14 16 18 20 0 2 4 VCC - OPERATING SUPPLY VOLTAGE (V) 8 10 12 14 Fig. 4 Current Threshold/Voltage Threshold vs. Temperature Fig. 3 Input Current/Low Level Output Voltage vs. Temperature 120 4.2 3.2 4.0 110 4.0 3.0 3.8 100 3.6 90 IIN VIN = 5.0 V (PINS 2 and 3) VCC = 5.0 V 3.4 3.2 80 70 3.0 60 2.8 50 2.6 40 VOL VCC = 5.0 V IOL = 4.2 mA 2.4 2.2 30 20 2.0 1.8 -40 10 -20 0 25 45 VTH(DC) - VOLTAGE THRESHOLD (V) 4.2 VOL (mV) Input Current, IIN (mA) 6 VIN - INPUT VOLTAGE (V) 2.8 VTH+ 3.6 2.6 3.4 2.4 3.2 2.2 ITH+ 3.0 2.0 2.8 1.8 2.6 1.6 VTH- 2.4 1.4 2.2 1.2 ITH- 2.0 1.0 1.8 0 85 65 3.8 ITH(DC) - CURRENT THRESHOLD (mA) 4 0.8 -40 -20 0 25 45 65 85 TA - TEMPERATURE (C) TA - TEMPERATURE (C) Fig. 5 Propagation Delay vs. Temperature Fig. 6 Rise and Fall Time vs. Temperature 70 100 0.8 90 60 0.7 Tf 80 0.6 50 Tr - RISE TIME (s) TP - PROPAGATION DELAY (s) DC (Pins 1 & 4 Open) 35 40 TPLH 30 TPHL 20 70 0.5 60 50 0.4 40 0.3 30 Tf - FALL TIME (s) ICCL - LOGIC LOW SUPPLY CURRENT (mA) Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage 0.2 20 10 Tr 0.1 10 0 -60 -40 -20 0 20 40 TA - TEMPERATURE (C) 60 80 100 0 -40 0.0 -20 0 25 45 65 85 TA - TEMPERATURE (C) 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 Fig. 7 Logic High Supply Current vs. Temperature V+/V- -EXTERNAL THRESHOLD VOLTAGE (V) Fig. 8 External Threshold Characteristics V+/V- vs. Rx ICCH - LOGIC HIGH SUPPLY CURRENT (nA) 1000 VCC = 18 V VO = OPEN IIN = 0 mA 100 10 1 -60 -40 -20 0 20 40 TA - TEMPERATURE (C) 60 80 100 300 V- (AC) V+ (AC) 250 200 V+ (DC) 150 100 V- (DC) 50 0 0 40 80 120 160 200 240 RX - EXTERNAL SERIES RESISTOR (K$) 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 +5V 5V 1 AC Pulse Generator tr = 5ns Z O= 50 $ VCC 8 2 DC+ 3 DC4 AC 7 VO .1uf bypass 2.5V Input (VIN) RL 0V t PHL Output 6 t PLH (VO) VO Output (VO ) GND 5 90% 10 % 90% 10 % 1.5 V VOL tr tf VIN Pulse Amplitude = 5 V Pulse Width = 1 ms f = 100 Hz Tr = T f = 1.0 s (10 - 90%) Fig. 9. Switching Test Circuit VCM H I IN RCC* 1 AC A B 2 DC+ 3 DC- VFF 4 AC VCM L +5V VCC 8 7 VO .1uf bypass RL VCM (VO) GND 5 CL** + 5V CM H VO Switching Pos. (A) I IN = 0 mA VO (Min) VCM - 5V Output 6 * SEE NOTE 8 Pulse Gen VO (Max) ** CL IS 30 pF, WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE VO Switching Pos. (B) I IN = 3.11 mA VOL CM L Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 Package Dimensions (Through Hole) Package Dimensions (Surface Mount) 0.390 (9.91) 0.370 (9.40) PIN 1 ID. 4 4 3 2 3 2 1 1 PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 5 6 7 0.270 (6.86) 0.250 (6.35) 8 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 5 0.070 (1.78) 0.045 (1.14) 6 7 8 0.300 (7.62) TYP 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.115 (2.92) 0.020 (0.51) MIN 0.020 (0.51) MIN 0.016 (0.41) 0.008 (0.20) 0.154 (3.90) 0.120 (3.05) 0.045 [1.14] 0.022 (0.56) 0.016 (0.41) 0.022 (0.56) 0.016 (0.41) 15 MAX 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP 0.300 (7.62) TYP 0.100 (2.54) TYP 0.315 (8.00) MIN 0.405 (10.30) MIN Lead Coplanarity : 0.004 (0.10) MAX Package Dimensions (0.4"Lead Spacing) 4 3 2 1 PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 5 6 7 8 SEATING PLANE 0.390 (9.91) 0.370 (9.40) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.115 (2.92) 0.004 (0.10) MIN 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) NOTE 0 to15 0.016 (0.40) 0.008 (0.20) 0.100 (2.54) TYP All dimensions are in inches (millimeters) 0.400 (10.16) TYP 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER HCPL-3700 ORDERING INFORMATION Option Order Entry Identifier Description R2 .R2 Opto Plus Reliability Conditioning S .S Surface Mount Lead Bend SD * .SD Surface Mount; Tape and reel SDL * .SDL Surface Mount; Tape and reel W .W 0.4" Lead Spacing QT Carrier Tape Specifications ("D" Taping Orientation) 12.0 0.1 4.90 0.20 4.0 0.1 0.30 0.05 4.0 0.1 O1.55 0.05 1.75 0.10 7.5 0.1 16.0 0.3 13.2 0.2 10.30 0.20 0.1 MAX 10.30 0.20 O1.6 0.1 User Direction of Feed Corporate Headquarters QT Optoelectronics 610 North Mary Avenue Sunnyvale, CA 94086 (408) 720-1440 Phone (408) 720-0848 Fax North American Sales QT Optoelectronics 16775 Addison Rd.,Suite 200 Addison, TX 75001 (972) 447-1300 Phone (972) 447-0784 Fax European Sales Quality Technologies Deutschland GmbH Max-Huber-Strasse 8 D-85737 Ismaning, Germany 49 [0] 89/96.30.51 Phone 49 [0] 89/96.54.74 Fax European Sales QT Optoelectronics "Le Levant" 2, rue du Nouveau Bercy F-94277-CHARENTON-LE PONT Cedex FRANCE 33 [0] 1.45.18.78.78 Phone 33 [0] 1.43.75.77.57 Fax Asia/Pacific Sales QT Optoelectronics B613, 6th Floor East Wing, Wisma Tractors Jalan SS16/1, Subang Jaya 47500 Petaling Jaya Selangor Darul Eshan, Malaysia 603/735-2417 Phone 603/736-3382 Fax European Sales Quality Technologies (U.K) Ltd. 10, Prebendal Court, Oxford Road Aylesbury, Buckinghamshire HP19-3EY United Kingdom 44 [0] 1296/30.44.99 Phone 44 [0] 1296/39.24.32 Fax 10/22/99 200003A AC/DC TO LOGIC INTERFACE OPTOCOUPLER DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. (c) 2000 Fairchild Semiconductor Corporation 10/22/99 200003A