1 MHz to 10 GHz, 45 dB
Log Detector/Controller
Data Sheet
AD8319
Rev. C Document Feedback
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FEATURES
Wide bandwidth: 1 MHz to 10 GHz
High accuracy: ±1.0 dB over temperature
45 dB dynamic range up to 8 GHz
Stability over temperature: ±0.5 dB
Low noise measurement/controller output VOUT
Pulse response time (fall/rise): 6 ns/10 ns
Small footprint: 2 mm × 3 mm LFCSP
Supply operation: 3.0 V to 5.5 V @ 22 mA
Fabricated using high speed SiGe process
APPLICATIONS
RF transmitter PA setpoint controls and level monitoring
Power monitoring in radiolink transmitters
RSSI measurement in base stations, WLANs, WiMAX,
and radars
FUNCTIONAL BLOCK DIAGRAM
GAIN
BIAS SLOPE
DET DET DET DET
INHI
INLO
I V VOUT
I V VSET
CLPF
TADJVPOS
COMM
05705-001
Figure 1.
GENERAL DESCRIPTION
The AD8319 is a demodulating logarithmic amplifier, capable
of accurately converting an RF input signal to a corresponding
decibel-scaled output. It employs the progressive compression
technique over a cascaded amplifier chain, each stage of which
is equipped with a detector cell. The device can be used in either
measurement or controller modes. The AD8319 maintains
accurate log conformance for signals of 1 MHz to 8 GHz and
provides useful operation to 10 GHz. The input dynamic range
is typically 45 dB (re: 50 Ω) with error less than ±3 dB. The
AD8319 has 6 ns/10 ns (fall time/rise time) response time that
enables RF burst detection to a pulse rate of beyond 50 MHz.
The device provides unprecedented logarithmic intercept stability
vs. ambient temperature conditions. A supply of 3.0 V to 5.5 V
is required to power the device. Current consumption is typically
22 mA, and it decreases to 200 µA when the device is disabled.
The AD8319 can be configured to provide a control voltage to
a power amplifier or a measurement output from the VOUT
pin. Because the output can be used for controller applications,
special attention was paid to minimize wideband noise. In this
mode, the setpoint control voltage is applied to the VSET pin.
The feedback loop through an RF amplifier is closed via VOUT,
the output of which regulates the output of the amplifier to a
magnitude corresponding to VSET. The AD8319 provides 0 V to
(VPOS − 0.1 V) output capability at the VOUT pin, suitable for
controller applications. As a measurement device, VOUT is
externally connected to VSET to produce an output voltage,
VOUT, that is a decreasing linear-in-dB function of the RF input
signal amplitude.
The logarithmic slope is −22 mV/dB, determined by the VSET
interface. The intercept is 15 dBm (re: 50 Ω, CW input) using
the INHI input. These parameters are very stable against supply
and temperature variations.
The AD8319 is fabricated on a SiGe bipolar IC process and is
available in a 2 mm × 3 mm, 8-lead LFCSP for an operating
temperature range of −40°C to +85°C.
AD8319 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Using the AD8319 .......................................................................... 11
Basic Connections ...................................................................... 11
Input Signal Coupling ................................................................ 11
Output Interface ......................................................................... 11
Setpoint Interface ....................................................................... 11
Temperature Compensation of Output Voltage ..................... 12
Measurement Mode ................................................................... 12
Setting the Output Slope in Measurement Mode .................. 13
Controller Mode ......................................................................... 13
Output Filtering .......................................................................... 15
Operation Beyond 8 GHz.......................................................... 16
Evaluation Board ............................................................................ 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/13—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 18
4/08—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Changes to Theory of Operation Section .................................... 10
Changes to Figure 22 and Setpoint Interface Section ................ 11
3/07—Rev. 0 to Rev. A
Changes to Figure 9 .......................................................................... 8
Changes to Figure 22 and Setpoint Interface Section ................ 11
Changes to Measurement Mode Section ..................................... 12
Changes to Layout .......................................................................... 16
Changes to Layout .......................................................................... 17
Updated Outline Dimensions ....................................................... 18
10/05—Revision 0: Initial Version
Data Sheet AD8319
Rev. C | Page 3 of 20
SPECIFICATIONS
VPOS = 3 V, CLPF = 1000 pF, TA = 25°C, 52.3 Ω termination resistor at INHI, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
SIGNAL INPUT INTERFACE INHI (Pin 1)
Specified Frequency Range 0.001 10 GHz
DC Common-Mode Voltage VPOS − 0.6 V
MEASUREMENT MODE VOUT (Pin 5) shorted to VSET (Pin 4),
sinusoidal input signal
f = 900 MHz RTADJ = 18 kΩ
Input Impedance 1500||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < T
A
< +85°C
dB
Maximum Input Level ±1 dB error −3 dBm
Minimum Input Level ±1 dB error −43 dBm
Slope1 −25 −22 −19.5 mV/dB
Intercept1 12 15 21 dBm
Output Voltage: High Power In
P
IN
= −10 dBm
V
Output Voltage: Low Power In
P
IN
= −40 dBm
V
f = 1.9 GHz RTADJ = 8 kΩ
Input Impedance 950||0.38 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level
±1 dB error
dBm
Minimum Input Level ±1 dB error −44 dBm
Slope1 −25 −22 −19.5 mV/dB
Intercept1 10 13 20 dBm
Output Voltage: High Power In PIN = −10 dBm 0.53 V
Output Voltage: Low Power In
P
IN
= −35 dBm
V
f = 2.2 GHz RTADJ = 8 kΩ
Input Impedance 810||0.39 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level
±1 dB error
dBm
Minimum Input Level ±1 dB error −45 dBm
Slope1 −22 mV/dB
Intercept1 13 dBm
Output Voltage: High Power In PIN = −10 dBm 0.5 V
Output Voltage: Low Power In PIN = −35 dBm 1.18 V
f = 3.6 GHz
R
TADJ
= 8 kΩ
Input Impedance 300||0.33 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 36 dB
Maximum Input Level ±1 dB error −6 dBm
Minimum Input Level
±1 dB error
dBm
Slope1 −22 mV/dB
Intercept1 10 dBm
Output Voltage: High Power In PIN = −10 dBm 0.46 V
Output Voltage: Low Power In PIN = −40 dBm 1.14 V
AD8319 Data Sheet
Rev. C | Page 4 of 20
Parameter Conditions Min Typ Max Unit
f = 5.8 GHz RTADJ = 500 Ω
Input Impedance 110||0.05 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 40 dB
Maximum Input Level ±1 dB error −3 dBm
Minimum Input Level ±1 dB error −43 dBm
Slope1 −22 mV/dB
Intercept1 15 dBm
Output Voltage: High Power In PIN = −10 dBm 0.57 V
Output Voltage: Low Power In
P
IN
= −40 dBm
V
f = 8.0 GHz RTADJ = open
Input Impedance 28||0.79 Ω||pF
±1 dB Dynamic Range TA = 25°C 40 dB
−40°C < TA < +85°C 31 dB
Maximum Input Level ±1 dB error −1 dBm
Minimum Input Level ±1 dB error −41 dBm
Slope2 −22 mV/dB
Intercept2 20 dBm
Output Voltage: High Power In PIN = −10 dBm 0.67 V
Output Voltage: Low Power In PIN = −40 dBm 1.34 V
OUTPUT INTERFACE VOUT (Pin 5)
Voltage Swing VSET = 0 V; RFIN = open VPOS − 0.1 V
VSET = 1.5 V; RFIN = open 10 mV
Output Current Drive VSET = 0 V; RFIN = open 10 mA
Small Signal Bandwidth RFIN = −10 dBm; from CLPF to VOUT 140 MHz
Output Noise RFIN = 2.2 GHz, −10 dBm, fNOISE = 100 kHz,
CLPF = open
90 nV/√Hz
Fall Time Input level = no signal to −10 dBm, 90% to 10%;
CLPF = 8 pF
18 ns
Input level = no signal to −10 dBm, 90% to 10%;
CLPF = open; ROUT = 150 Ω
ns
Rise Time Input level = −10 dBm to no signal, 10% to 90%;
CLPF = 8 pF
20 ns
Input level = −10 dBm to no signal, 10% to 90%;
CLPF = open; ROUT = 150 Ω
10 ns
Video Bandwidth (or Envelope Bandwidth) 50 MHz
VSET INTERFACE VSET (Pin 4)
Nominal Input Range RFIN = 0 dBm; measurement mode 0.35 V
RFIN = −40 dBm; measurement mode 1.23 V
Logarithmic Scale Factor −45 dB/V
Input Resistance RFIN = −20 dBm; controller mode; VSET = 1 V 40 kΩ
TADJ INTERFACE TADJ (Pin 6)
Input Resistance TADJ = 0.9 V, sourcing 50 µA 40 kΩ
Disable Threshold Voltage TADJ = open VPOS − 0.4 V
POWER INTERFACE VPOS (Pin 7)
Supply Voltage 3.0 5.5 V
Quiescent Current 18 22 30 mA
vs. Temperature −40°C ≤ TA ≤ +85°C 60 µA/°C
Disable Current TADJ = VPOS 200 µA
1 Slope and intercept are determined by calculating the best fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency.
2 Slope and intercept are determined by calculating the best fit line between the power levels of −34 dBm and −16 dBm at 8.0 GHz.
Data Sheet AD8319
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage: VPOS 5.7 V
VSET Voltage
0 to VPOS
Input Power (Single-Ended, re: 50 Ω) 12 dBm
Internal Power Dissipation 0.73 W
θJA 55°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD8319 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05705-002
1INHI
2COMM
3CLPF
4VSET
8INLO
7 VPOS
6TADJ
5VOUT
AD8319
TOP VI EW
(No t t o Scal e)
NOTES
1. THE P AD IS I NTERNAL LY CO NNE CTED T O
COM M ; S OLDE R TO A LOW IM P E DANCE
GROUND PL ANE .
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 INHI RF Input. Nominal input range of −50 dBm to 0 dBm, re: 50 Ω; ac-coupled RF input.
2 COMM Device Common. Connect this pin to a low impedance ground plane.
3 CLPF Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth.
In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator.
4 VSET Setpoint Control Input for Controller Mode or Feedback Input for Measurement Mode.
5 VOUT Measurement and Controller Output. In measurement mode, VOUT provides a decreasing linear-in-dB
representation of the RF input signal amplitude. In controller mode, VOUT is used to control the gain of a VGA or
VVA with a positive gain sense (increasing voltage increases gain).
6 TADJ Temperature Compensation Adjustment. Frequency dependent temperature compensation is set by connecting
a ground referenced resistor to this pin.
7 VPOS Positive Supply Voltage, 3.0 V to 5.5 V.
8 INLO RF Common for INHI. AC-coupled RF common.
EPAD The pad is internally connected to COMM; solder to a low impedance ground plane.
Data Sheet AD8319
Rev. C | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS = 3 V; T = 25°C, −40°C, +85°C; CLPF = 1000 pF; unless otherwise noted. Black: 25°C; Blue: −40°C; Red: +85°C. Error is calculated by
using the best fit line between PIN = −40 dBm and PIN = −10 dBm at the specified input frequency, unless otherwise noted.
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-003
Figure 3. VOUT and Log Conformance Error vs.
Input Amplitude at 900 MHz, RTADJ = 18 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(dBm)
05705-004
Figure 4. VOUT and Log Conformance Error vs.
Input Amplitude at 1.9 GHz, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
VOUT (V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
PIN (dBm)
05705-005
Figure 5. VOUT and Log Conformance Error vs.
Input Amplitude at 2.2 GHz, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
VOUT (V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
PIN (dBm)
05705-006
Figure 6. VOUT and Log Conformance Error vs.
Input Amplitude at 3.6 GHz, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-007
Figure 7. VOUT and Log Conformance Error vs.
Input Amplitude at 5.8 GHz, RTADJ = 500 Ω
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-008
Figure 8. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
RTADJ = Open, Error Calculated from PIN = −34 dBm to PIN = −16 dBm
AD8319 Data Sheet
Rev. C | Page 8 of 20
05705-009
V
OUT
(V)
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
0.75
ERROR (dB)
–2.0
–1.5
–1.0
0
0.5
1.0
1.5
2.0
–0.5
P
IN
(d Bm)
100–10–20
–30–40–50–60
Figure 9. VOUT and Log Conformance Error vs. Input Amplitude at 900 MHz,
Multiple Devices, RTADJ = 18 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-010
Figure 10. VOUT and Log Conformance Error vs. Input Amplitude at 1.9 GHz,
Multiple Devices, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-011
Figure 11. VOUT and Log Conformance Error vs. Input Amplitude at 2.2 GHz,
Multiple Devices, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
VOUT (V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
PIN (dBm)
05705-012
Figure 12. VOUT and Log Conformance Error vs. Input Amplitude at 3.6 GHz,
Multiple Devices, RTADJ = 8 kΩ
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-013
Figure 13. VOUT and Log Conformance Error vs. Input Amplitude at 5.8 GHz,
Multiple Devices, RTADJ = 500 Ω
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
–2.0
–1.5
0
0.5
1.0
1.5
2.0
ERRO R ( dB)
–0.5
–1.0
–60 –50 –40 –30 –20 –10 010
P
IN
(d Bm)
05705-014
Figure 14. VOUT and Log Conformance Error vs. Input Amplitude at 8.0 GHz,
Multiple Devices, RTADJ = Open, Error Calculated from
PIN = −34 dBm to PIN = −16 dBm
Data Sheet AD8319
Rev. C | Page 9 of 20
0
j2
j1
–j1
–j2
j0.5
–j0.5
j0.2
–j0.2
0.2 0.5 1 2
8000MHz
10000MHz 5800MHz
3600MHz
2200MHz
1900MHz
900MHz
100MHz
START FRE QUENCY = 0.05GHz
STOP F RE QUENCY = 10GHz
05705-015
Figure 15. Input Impedance vs. Frequency; No Termination Resistor on INHI
(Impedance De-Embedded to Input Pins), Z0 = 50 Ω
500mV
05705-016
M2.00µs A CH1 420V
T 29.60%
Ch1
1
∆ : 1.53V
@ : 1.53V
Figure 16. Power On/Off Response Time; VP = 3.0 V;
Input AC-Coupling Capacitors = 10 pF; CLPF = Open
200mV
05705-017
M20.0ns A CH1 1.04V
T 72.40%
Ch1
1
CH1 RIS E
9.949ns
CH1 FALL
6.032ns
Figure 17. VOUT Pulse Response Time; Pulsed RF Input 0.1 GHz, −10 dBm;
CLPF = Open; RLOAD = 150 Ω
05705-018
1k 10k 100k 1M
10
100
1k
10k
10M
NOISE SPECTRAL DENSITY (nV/ Hz)
0dBm
RF OFF
FRE QUENCY ( Hz )
–60dBm
–10dBm
–40dBm
–20dBm
Figure 18. Noise Spectral Density of Output vs. Frequency; CLPF = Open
05705-019
1k 10k 100k 1M
10
100
1k
10k
10M
NOISE SPECTRAL DENSITY (nV/ Hz)
FRE QUENCY ( Hz )
Figure 19. Noise Spectral Density of Output Buffer vs. Frequency (from CLPF
to VOUT); CLPF = 0.1 µF
0
0.25
0.50
1.00
1.25
1.50
1.75
2.00
V
OUT
(V)
0.75
ERRO R ( dB)
–2.0
–1.5
0
0.5
1.0
1.5
2.0
–0.5
–1.0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10
P
IN
(d Bm)
–60
3.3V
3.0V
3.6V
05705-020
Figure 20. VOUT Stability and Error vs. Supply Voltage at 1.9 GHz
When VPOS Varies by 10%
AD8319 Data Sheet
Rev. C | Page 10 of 20
THEORY OF OPERATION
The AD8319 is a five-stage demodulating logarithmic amplifier,
specifically designed for use in RF measurement and power control
applications at frequencies up to 10 GHz. A block diagram is
shown in Figure 21. Sharing much of its design with the AD8318
logarithmic detector/controller, the AD8319 maintains tight
intercept variability vs. temperature over a 40 dB range. Additional
enhancements over the AD8318, such as reduced RF burst
response time of 6 ns to 10 ns, 22 mA supply current, and
board space requirements of only 2 mm × 3 mm add to the low
cost and high performance benefits found in the AD8319.
GAIN
BIAS SLOPE
DET DET DET DET
INHI
INLO
I V VOUT
VSET
CLPF
TADJ
VPSO
COMM
05705-021
IV
Figure 21. Block Diagram
A fully differential design, using a proprietary, high speed
SiGe process, extends high frequency performance. Input INHI
receives the signal with a low frequency impedance of nominally
500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB
log conformance error is typically 0 dBm (re: 50 Ω). The noise
spectral density referred to the input is 1.15 nV/√Hz, which is
equivalent to a voltage of 118 µV rms in a 10.5 GHz bandwidth
or a noise power of −66 dBm (re: 50 Ω). This noise spectral
density sets the lower limit of the dynamic range. However, the
low end accuracy of the AD8319 is enhanced by specially shaping
the demodulating transfer characteristic to partially compensate
for errors due to internal noise. The common pin, COMM,
provides a quality low impedance connection to the PCB
ground. The package paddle, which is internally connected
to the COMM pin, should also be grounded to the PCB to
reduce thermal impedance from the die to the PCB.
The logarithmic function is approximated in a piecewise fashion
by five cascaded gain stages. (For a detailed explanation of the
logarithm approximation, refer to the AD8307 data sheet.) The
cells have a nominal voltage gain of 9 dB each and a 3 dB
bandwidth of 10.5 GHz. Using precision biasing, the gain is
stabilized over temperature and supply variations. The overall
dc gain is high due to the cascaded nature of the gain stages.
An offset compensation loop is included to correct for offsets
within the cascaded cells. At the output of each of the gain
stages, a square-law detector cell is used to rectify the signal.
The RF signal voltages are converted to a fluctuating differential
current having an average value that increases with signal level.
Along with the five gain stages and detector cells, an additional
detector is included at the input of the AD8319, providing a
40 dB dynamic range in total. After the detector currents are
summed and filtered, the following function is formed at the
summing node:
ID × log10(VIN/VINTERCEPT) (1)
where:
ID is the internally set detector current.
VIN is the input signal voltage.
VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT,
the output voltage would be 0 V, if it were capable of going to 0 V).
Data Sheet AD8319
Rev. C | Page 11 of 20
USING THE AD8319
BASIC CONNECTIONS
The AD8319 is specified for operation up to 10 GHz, as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 µF should be connected close to
this power supply pin.
05705-022
AD8319
1 2 3 4
876 5
SIGNAL
INPUT
NOTES
1. SEE THE TEMPERATURE COMPENSATION OF THE OUTPUT VOLTAGE
SECTION.
2. SEE THE OUTPUT FILTERING SECTION.
R1
52.3Ω
R2
0Ω
R4
0Ω
C2
47nF
C1
47nF
C5
0.1µF
C4
100pF
V
S
(3. 0V TO 5.5V)
INHI
INLO VPOS TADJ VOUT
COMM CLPF VSET
SEE
NOT E 1
V
OUT
SEE
NOT E 2
Figure 22. Basic Connections
The paddle of the LFCSP is internally connected to COMM.
For optimum thermal and electrical performance, the paddle
should be soldered to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below VPOS.
05705-023
VPOS
2kΩ A = 9dB
18.7kΩ 18.7kΩ
CURRENT
Gm
STAGE
INLO
INHI
OFFSET
COMP
5pF 5pF
FIRST
GAIN
STAGE
Figure 23. Input Interface
Although the input can be reactively matched, in general, this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in Figure 22)
combines with the relatively high input impedance to give an
adequate broadband 50 Ω match.
The coupling time constant, 50 × CC/2, forms a high-pass corner
with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where C1 =
C2 = CC. Using the typical value of 47 nF, this high-pass corner
is ~68 kHz. In high frequency applications, fHP should be as
large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This should generally be placed at the generator
side of the coupling capacitors, thereby lowering the required
capacitance value for a given high-pass corner frequency.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal 10 Ω
resistor is placed in series with the output and the VOUT pin.
The rise time of the output is limited mainly by the slew on
CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is
an internal pull-down resistor of 1.6 kΩ. A resistive load at
VOUT is placed in parallel with the internal pull-down resistor
to provide additional discharge current.
05705-024
+
0.8V 1200Ω
400Ω
–
10Ω VOUT
VPOS
CLPF
COMM
Figure 24. Output Interface
To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω,
the AD8319 fall time is <7 ns.
SETPOINT INTERFACE
The VSET input drives the high impedance input (40 kΩ) of an
internal op amp. The VSET voltage appears across the internal
1.5 kΩ resistor to generate ISET. When a portion of VOUT is
applied to VSET, the feedback loop forces
−ID × log10(VIN/VINTERCEPT) = ISET (2)
If VSET = VOUT/2x, ISET = VOUT/(2x × 1.5 kΩ).
The result is
VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)
05705-025
1.5kΩ
ISET
COMM
VSET
V
SET
COMM
20kΩ
20kΩ
Figure 25. VSET Interface
AD8319 Data Sheet
Rev. C | Page 12 of 20
The slope is given by −ID × 2x × 1.5 kΩ = −22 mV/dB × x. For
example, if a resistor divider to ground is used to generate a VSET
voltage of VOUT/2, x = 2. The slope is set to −880 mV/decade or
−44 mV/dB.
TEMPERATURE COMPENSATION OF OUTPUT
VOLTAGE
The primary component of the variation in VOUT vs. temperature,
as the input signal amplitude is held constant is the drift of the
intercept. This drift is also a weak function of the input signal
frequency; therefore, provision is made for optimization of
internal temperature compensation at a given frequency by
providing the TADJ pin.
COMM COMM
I
COMP
V
INTERNAL
TADJ
R
TADJ
05705-026
1.5kΩ
AD8319
Figure 26. TADJ Interface
RTADJ is connected between this pin and ground. The value of
this resistor partially determines the magnitude of an analog
correction coefficient, which is used to reduce intercept drift.
The relationship between output temperature drift and
frequency is not linear and cannot be easily modeled. As a
result, experimentation is required to choose the correct
TADJ resistor. Table 4 shows the recommended values for
some commonly used frequencies.
Table 4. Recommended RTADJ Resistor Values
Frequency Recommended RTADJ
50 MHz 18 kΩ
100 MHz 18 kΩ
900 MHz 18 kΩ
1.8 GHz 8 kΩ
1.9 GHz 8 kΩ
2.2 GHz 8 kΩ
3.6 GHz 8 kΩ
5.3 GHZ
500 Ω
5.8 GHz 500 Ω
8 GHz Open
MEASUREMENT MODE
When the VOUT voltage or a portion of the VOUT voltage is fed
back to the VSET pin, the device operates in measurement
mode. As seen in Figure 27, the AD8319 has an offset voltage,
a negative slope, and a VOUT measurement intercept at the high
end of its input signal range.
0
0.25
0.50
0.75
1.00
1.25
1.50
2.00
V
OUT
(V)
ERRO R ( dB)
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15
P
IN
(d Bm)
05705-027
RANGE FOR
CALCULATION OF
SLOPE AND INTE RCE P T
V
OUT
25°C
ERRO R 25°C
INTERCEPT
1.75
Figure 27. Typical Output Voltage vs. Input Signal
The output voltage vs. input signal voltage of the AD8319 is
linear-in-dB over a multidecade range. The equation for this
function is
VOUT = X × VSLOPE/DEC × log10(VIN/VINTERCEPT) =
X × VSLOPE/dB × 20 × log10(VIN/VINTERCEPT) (3)
where:
X is the feedback factor in VSET = VOUT/X.
VSLOPE/DEC is nominally −440 mV/decade or −22 mV/dB.
VINTERCEPT is the x-axis intercept of the linear-in-dB portion of
the VOUT vs. PIN curve (see Figure 27).
VINTERCEPT is 15 dBm (2 dBV) for a sinusoidal input signal.
An offset voltage, VOFFSET, of 0.35 V is internally added to the
detector signal, so that the minimum value for VOUT is
X × VOFFSET, so for X = 1, minimum VOUT is 0.35 V.
The slope is very stable vs. process and temperature variation.
When base-10 logarithms are used, VSLOPE/DEC represents the
volts/decade. A decade corresponds to 20 dB; VSLOPE/DEC/20 =
VSLOPE/dB represents the slope in volts/dB.
As noted in the Equation 1 and Equation 2, the VOUT voltage has
a negative slope. This is also the correct slope polarity to control
the gain of many power amplifiers in a negative feedback configu-
ration. Because both the slope and intercept vary slightly with
frequency, it is recommended to refer to the Specifications
section for application-specific values for the slope and intercept.
Although demodulating log amps respond to input signal
voltage, not input signal power, it is customary to discuss the
amplitude of high frequency signals in terms of power. In this
case, the characteristic impedance of the system, Z0, must be
known to convert voltages to their corresponding power levels.
Equation 4 to Equation 6 are used to perform this conversion.
P(dBm) = 10 × log10(Vrms2/(Z0 × 1 mW)) (4)
P(dBV) = 20 × log10(Vrms/1 Vrms) (5)
P(dBm) = P(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2) (6)
Data Sheet AD8319
Rev. C | Page 13 of 20
For example, PINTERCEPT for a sinusoidal input signal expressed in
terms of dBm (decibels referred to 1 mW), in a 50 Ω system is
PINTERCEPT(dBm) =
PINTERCEPT(dBV) − 10 × log10(Z0 × 1 mW/1 Vrms2) =
2 dBV − 10 × log10(50×10-3) = 15 dBm (7)
For a square wave input signal in a 200 Ω system
PINTERCEPT = −1 dBV − 10 × log10[(200 Ω × 1 mW/1Vrms2)] =
6 dBm
Further information on the intercept variation dependence upon
waveform can be found in the AD8313 and AD8307 data sheets.
SETTING THE OUTPUT SLOPE IN MEASUREMENT
MODE
To operate in measurement mode, VOUT must be connected to
VSET. Connecting VOUT directly to VSET yields the nominal
logarithmic slope of −22 mV/dB. The output swing corresponding
to the specified input range is then 0.35 V to 1.5 V. The slope
and output swing can be increased by placing a resistor divider
between VOUT and VSET (that is, one resistor from VOUT to
VSET and one resistor from VSET to ground). The input imped-
ance of VSET is 40 kΩ. Slope setting resistors should be kept below
20 kΩ to prevent this input impedance from affecting the
resulting slope. If two equal resistors are used (for example,
10 kΩ/10 kΩ), the slope doubles to −44 mV/dB.
05705-028
VOUT
AD8319
–44mV/dB
VSET
10kΩ
10kΩ
Figure 28. Increasing the Slope
CONTROLLER MODE
The AD8319 provides a controller mode feature at the VOUT
pin. Using VSET for the setpoint voltage, it is possible for the
AD8319 to control subsystems, such as power amplifiers (PAs),
variable gain amplifiers (VGAs), or variable voltage attenuators
(VVAs) that have output power that increases monotonically
with respect to their gain control signal.
To operate in controller mode, the link between VSET and
VOUT is broken. A setpoint voltage is applied to the VSET
input; VOUT is connected to the gain control terminal of the
VGA and the RF input of the detector is connected to the
output of the VGA (usually using a directional coupler and
some additional attenuation). Based on the defined relationship
between VOUT and the RF input signal when the device is in
measurement mode, the AD8319 adjusts the voltage on VOUT
(VOUT is now an error amplifier output) until the level at the
RF input corresponds to the applied VSET. When the AD8319
operates in controller mode, there is no defined relationship
between the VSET and VOUT voltages; VOUT settles to a value that
results in the correct input signal level appearing at INHI/INLO.
For this output power control loop to be stable, a ground-
referenced capacitor must be connected to the CLPF pin. This
capacitor, CFLT, integrates the error signal (in the form of a
current) to set the loop bandwidth and ensure loop stability.
Further details on control loop dynamics can be found in the
AD8315 data sheet.
05705-029
RFIN
VGA/VVA
GAIN
CONTROL
VOLTAGE
DIRECTIONAL
COUPLER
ATTENUATOR
INHI
VSET
INLO
CLPF
VOUT
AD8319
52.3Ω
47nF
C
FLT
47nF
DAC
Figure 29. Controller Mode
Decreasing VSET, which corresponds to demanding a higher
signal from the VGA, increases VOUT. The gain control voltage
of the VGA must have a positive sense. A positive control voltage
to the VGA increases the gain of the device.
AD8319 Data Sheet
Rev. C | Page 14 of 20
INLO
INHI
GAIN
OPLO
OPHI
DIRECTIONAL
COUPLER
ATTENUATOR
VPOS COMM
ADL5330
+5V
+5V
+5
V
COMM
VOUT VPOS
VSET INHI
INLOCLPF
AD8319
LOG AMP
DAC
RF OUTPUT
SIGNAL
4.12kΩ
10kΩ
SETPOINT
VOLTAGE
1nF
47nF
47nF
120nH 120nH
100pF
100pF
100pF
100pF
TADJ
18kΩ
52.3Ω
RF INPUT
SIGNAL
05705-030
Figure 30. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5330
The basic connections for operating the AD8319 in an automatic
gain control (AGC) loop with the ADL5330 are shown in
Figure 30. The ADL5330 is a 10 MHz to 3 GHz VGA. It offers a
large gain control range of 60 dB with ±0.5 dB gain stability.
This configuration is similar to Figure 29.
The gain of the ADL5330 is controlled by the output pin of the
AD8319. This voltage, VOUT, has a range of 0 V to near VPOS. To
avoid overdrive recovery issues, the AD8319 output voltage can
be scaled down using a resistive divider to interface with the 0 V
to 1.4 V gain control range of the ADL5330.
A coupler/attenuation of 21 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8319 (approximately −5 dBm
at 900 MHz).
Figure 31 shows the transfer function of the output power vs.
the VSET voltage over temperature for a 900 MHz sine wave with
an input power of −1.5 dBm. Note that the power control of the
AD8319 has a negative sense. Decreasing VSET, which corresponds
to demanding a higher signal from the ADL5330, increases gain.
The AGC loop is capable of controlling signals of ~40 dB. This
range limitation is due to the dynamic range of the AD8319.
Using a wider dynamic range detector, such as the AD8317,
AD8318, or AD8362, allows for the full 60 dB range of the
ADL5330 to be used. The performance over temperature is
most accurate over the highest power range, where it is generally
most critical. Across the top 40 dB range of output power, the
linear conformance error is well within ±0.5 dB over temperature.
–50
–40
–30
–10
0
10
20
30
OUTPUT POWER (dBm)
–20
–4
–3
0
1
2
3
4
–1
–2
ERROR (dB)
0.20.40.60.81.01.21.4
SETPOINT VOLTAGE (V)
1.31.10.3 0.5 0.7 0.9 1.5 1.6
05705-031
Figure 31. ADL5330 Output Power vs. AD8319 Setpoint Voltage, PIN = −1.5 dBm
Data Sheet AD8319
Rev. C | Page 15 of 20
For the AGC loop to remain in equilibrium, the AD8319 must
track the envelope of the output signal of the ADL5330 and
provide the necessary voltage levels to the gain control input
of the ADL5330. Figure 32 shows an oscilloscope screenshot of
the AGC loop depicted in Figure 30. A 100 MHz sine wave with
50% AM modulation is applied to the ADL5330. The output signal
from the VGA is a constant envelope sine wave with amplitude
corresponding to a setpoint voltage at the AD8319 of 1.3 V.
The gain control response of the AD8319 to the changing input
envelope is also shown.
CH1 200mV A Ch2 1.03V
05705-032
M2.00ms
T 0.00000 s
1
Ch2 200mV
AM MODULATE D INPUT
AD8319 OUTPUT
Ch3 100mVΩ
2
3
ADL5330 OUTP UT
Figure 32. Oscilloscope Screenshot Showing an AM Modulated Input Signal
and the Response from the AD8319
Figure 33 shows the response of the AGC RF output to a pulse
on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop
responds with an RF burst. In this configuration, the input signal to
the ADL5330 is a 1 GHz sine wave at a power level of −15 dBm.
A Ch1 2.60V
T 179.800µ s
AD8319 VSE T PUL S E
ADL5330 OUTP UT
3
1
M10.µsCh1 2.00V
Ch3 50mVΩ
05705-033
T
Figure 33. Oscilloscope Screenshot Showing the
Response Time of the AGC Loop
Response time and the amount of signal integration are
controlled by CFLT. This functionality is analogous to the
feedback capacitor around an integrating amplifier. While it
is possible to use large capacitors for CFLT, in most applications,
values under 1 nF provide sufficient filtering.
Calibration in controller mode is similar to the method used
in measurement mode. A simple two-point calibration can be
done by applying two known VSET voltages or DAC codes and
measuring the output power from the VGA. Slope and intercept
can then be calculated by:
Slope = (VSET1 − VSET2)/(POUT1 − POUT2) (8)
Intercept = POUT1 − VSET1/Slope (9)
VSETx = Slope × (POUTx − Intercept) (10)
More information on the use of the ADL5330 in AGC applications
can be found in the ADL5330 data sheet.
OUTPUT FILTERING
For applications in which maximum video bandwidth and,
consequently, fast rise time are desired, it is essential that the
CLPF pin be left unconnected and free of any stray capacitance.
The nominal output video bandwidth of 50 MHz can be reduced
by connecting a ground-referenced capacitor (CFLT) to the CLPF
pin, as shown in Figure 34. This is generally done to reduce output
ripple (at twice the input frequency for a symmetric input
waveform such as sinusoidal signals).
+4 VOUT
CLPF
AD8319
3.5pF
05705-037
I
LOG
C
FLT
1.5kΩ
Figure 34. Lowering the Postdemodulation Bandwidth
CFLT is selected by
( )
pF3.5
kΩ1.52π
1−
××
=BandwidthVideo
C
FLT
(11)
The video bandwidth should typically be set to a frequency
equal to approximately one-tenth the minimum input frequency.
This ensures that the output ripple of the demodulated log
output, which is at twice the input frequency, is well filtered.
In many log amp applications, it may be necessary to lower the
corner frequency of the postdemodulation filtering to achieve
low output ripple while maintaining a rapid response time to
changes in signal level. An example of a four-pole active filter
is shown in the AD8307 data sheet.
AD8319 Data Sheet
Rev. C | Page 16 of 20
OPERATION BEYOND 8 GHz
The AD8319 is specified for operation up to 8 GHz, but it provides
useful measurement accuracy over a reduced dynamic range of
up to 10 GHz. Figure 35 shows the performance of the AD8319
over temperature at 10 GHz when the device is configured as
shown in Figure 22. Dynamic range is reduced at this frequency,
but the AD8319 does provide 30 dB of measurement range within
±3 dB of linearity error.
05705-038
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–40 –35 –30 –25 –20 –15 –10 –5 05
P
IN
(d Bm)
V
OUT
(V)
–5
–4
–3
–2
–1
0
1
2
3
4
5
ERRO R ( dB)
Figure 35. VOUT and Log Conformance Error vs. Input Amplitude at 10 GHz,
Multiple Devices, RTADJ = Open, CLPF = 1000 pF
Implementing an impedance match for frequencies beyond
8 GHz can improve the sensitivity of the AD8319 and
measurement range.
Operation beyond 10 GHz is possible, but part-to-part
variation, most notably in the intercept, becomes significant.
Data Sheet AD8319
Rev. C | Page 17 of 20
EVALUATION BOARD
AD8319
1234
8 7 6 5
R1
52.3Ω
R7
OPEN
R2
0Ω
C1
C2
C4
C5
47nF
47nF
0.1µF
100pF
VPOS
INHI
INLO VPOS TADJ VOUT
COMM CLPF VSET
05705-034
TADJ
R5
200Ω
R4
OPEN
VOUT_ALT
R3
OPEN
CL
OPEN RL
OPEN
R6
1kΩ
GND
RFIN VSET
VOUT
C3
8.2pF
Figure 36. Evaluation Board Schematic (Rev. A)
Table 5. Evaluation Board (Rev. A) Configuration Options
Component Function Default Conditions
VPOS, GND Supply and Ground Connections. Not applicable
R1, C1, C2 Input Interface.
The 52.3 Ω resistor in Position R1 combines with the internal input impedance of the AD8319 to
give a broadband input impedance of approximately 50 Ω. Capacitor C1 and Capacitor C2 are dc
blocking capacitors. A reactive impedance match can be implemented by replacing R1 with an
inductor and C1 and C2 with appropriately valued capacitors.
R1 = 52.3 Ω (Size 0402)
C1 = 47 nF (Size 0402)
C2 = 47 nF (Size 0402)
R5, R7 Temperature Compensation Interface.
The internal temperature compensation network is optimized for input signals up to 3.6 GHz when
R7 is 10 kΩ. This circuit can be adjusted to optimize performance for other input frequencies
by changing the value of the resistor in Position R7. See Table 4 for specific RTADJ resistor values.
R5 = 200 Ω (Size 0402)
R7 = open (Size 0402)
R2, R3, R4,
R6, RL, CL
Output Interface—Measurement Mode.
In measurement mode, a portion of the output voltage is fed back to the VSET pin via R2. The
magnitude of the slope of the VOUT output voltage response can be increased by reducing the
portion of VOUT that is fed back to VSET. R6 can be used as a back-terminating resistor or as part
of a single-pole, low-pass filter.
R2 = 0 Ω (Size 0402)
R3 = open (Size 0402)
R4 = open (Size 0402)
R6 = 1 kΩ (Size 0402)
RL = CL = open (Size 0402)
R2, R3 Output Interface—Controller Mode.
In this mode, R2 must be open. In controller mode, the AD8319 can control the gain of an
external component. A setpoint voltage is applied to the VSET pin, the value of which corresponds
to the desired RF input signal level applied to the AD8319 RF input. A sample of the RF output
signal from this variable-gain component is selected, typically via a directional coupler, and
applied to AD8319 RF input. The voltage at the VOUT pin is applied to the gain control of the
variable gain element. A control voltage is applied to the VSET pin. The magnitude of the
control voltage can optionally be attenuated via the voltage divider comprising R2 and R3, or a
capacitor can be installed in Position R3 to form a low-pass filter along with R2.
R2 = open (Size 0402)
R3 = open (Size 0402)
C4, C5 Power Supply Decoupling.
The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to
the AD8319 and a 0.1 µF capacitor placed physically close to the power supply input pin.
C4 = 0.1 µF (Size 0603)
C5 = 100 pF (Size 0402)
C3 Filter Capacitor.
The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a
capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall
time of the AD8319 for pulsed input signals. See the Output Filtering section for more details.
C3 = 8.2 pF (Size 0402)
AD8319 Data Sheet
Rev. C | Page 18 of 20
05705-035
Figure 37. Component Side Layout
05705-036
Figure 38. Component Side Silkscreen
Data Sheet AD8319
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
1.89
1.74
1.59
0.50 BSC
0.60
0.45
0.30
0.55
0.40
0.30
0.15
0.10
0.05
0.25
0.20
0.15
BOTT OM VI EW
41
58
3.25
3.00
2.75
1.95
1.75
1.55
2.95
2.75
2.55
PIN 1
INDICATOR
2.25
2.00
1.75
TOP VI E W
0.05 MAX
0.02 NOM
12° MAX
EXPOSEDPAD
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECT IO N OF THI S DATA SHE E T.
03-11-2013-B
Figure 39. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
2 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
AD8319ACPZ-R7 –40°C to +85°C 8-Lead LFCSP_VD CP-8-1 Q2
AD8319ACPZ-R2 –40°C to +85°C 8-Lead LFCSP_VD CP-8-1 Q2
AD8319ACPZ-WP –40°C to +85°C 8-Lead LFCSP_VD, Waffle Pack CP-8-1 Q2
AD8319-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
AD8319 Data Sheet
Rev. C | Page 20 of 20
NOTES
©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05705-0-3/13(C)