LTC2263CUJ-12#PBF - LINEAR TECHNOLOGY

LTC2265-12/

LTC2264-12/LTC2263-12

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TYPICAL APPLICATION

DESCRIPTION

12-Bit, 65Msps/40Msps/

25Msps Low Power Dual ADCs

The LTC

2265-12/LTC2264-12/LTC2263-12 are 2-channel,

simultaneous sampling 12-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals. They

are perfect for demanding communications applications

with AC performance that includes 71dB SNR and 90dB

spurious free dynamic range (SFDR). Ultralow jitter of

0.15psRMS allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 0.3LSBRMS.

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode) or one bit at a time (1-lane mode). The LVDS

drivers have optional internal termination and adjustable

output levels to ensure clean signal integrity.

The ENC+ and ENC– inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An internal clock duty cycle stabilizer

allows high performance at full speed for a wide range of

clock duty cycles.

LTC2265-12, 65Msps,

2-Tone FFT, fIN = 70MHz and 75MHz

FEATURES

APPLICATIONS

n 2-Channel Simultaneous Sampling ADC

n 71dB SNR

n 90dB SFDR

n Low Power: 167mW/112mW/94mW Total

n 83mW/56mW/47mW per Channel

n Single 1.8V Supply

n Serial LVDS Outputs: 1 or 2 Bits per Channel

n Selectable Input Ranges: 1VP-P to 2VP-P

n 800MHz Full Power Bandwidth S/H

n Shutdown and Nap Modes

n Serial SPI Port for Conﬁguration

n Pin Compatible 14-Bit and 12-Bit Versions

n 40-Pin (6mm × 6mm) QFN Package

n Communications

n Cellular Base Stations

n Software Deﬁned Radios

n Portable Medical Imaging

n Multichannel Data Acquisition

n Nondestructive Testing

CH.1

ANALOG

INPUT

CH.2

ANALOG

INPUT

ENCODE

INPUT

226512 TA01

GND OGND

–

S/H

–

S/H

12-BIT

ADC CORE

12-BIT

ADC CORE

PLL

DATA

SERIALIZER

SERIALIZED

LVDS

OUTPUTS

1.8V 1.8V

VDD OVDD

OUT1A

OUT1B

OUT2A

OUT2B

DATA

CLOCK

OUT

FRAME

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

226512 TA02

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltages

VDD, OVDD ................................................–0.3V to 2V

Analog Input Voltage (AIN+, AIN–, PAR/SER,

SENSE) (Note 3) .......................... –0.3V to (VDD + 0.2V)

Digital Input Voltage (ENC+, ENC–, CS,

SDI, SCK) (Note 4) ....................................–0.3V to 3.9V

SDO (Note 4) ............................................–0.3V to 3.9V

Digital Output Voltage ................–0.3V to (OVDD + 0.3V)

Operating Temperature Range

LTC2265C, 2264C, 2263C ........................ 0°C to 70°C

LTC2265I, 2264I, 2263I .......................–40°C to 85°C

Storage Temperature Range ...................–65°C to 150°C

(Notes 1 and 2)

3940 38 37 36 35 34 33 32 31

11 20

12 13 14 15

TOP VIEW

GND

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

16 17 18 19

AIN1+

AIN1–

VCM1

REFH

REFL

VCM2

AIN2+

AIN2–

OUT1B+

OUT1B–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT2A+

OUT2A–

VDD

SENSE

GND

VREF

PAR/SER

SDO

GND

OUT1A+

OUT1A–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT2B–

OUT2B+

TJMAX = 150°C, θJA = 32°C/W

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2265CUJ-12#PBF LTC2265CUJ-12#TRPBF LTC2265UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C

LTC2265IUJ-12#PBF LTC2265IUJ-12#TRPBF LTC2265UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C

LTC2264CUJ-12#PBF LTC2264CUJ-12#TRPBF LTC2264UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C

LTC2264IUJ-12#PBF LTC2264IUJ-12#TRPBF LTC2264UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C

LTC2263CUJ-12#PBF LTC2263CUJ-12#TRPBF LTC2263UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C

LTC2263IUJ-12#PBF LTC2263IUJ-12#TRPBF LTC2263UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

CONVERTER CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

PARAMETER CONDITIONS

LTC2265-12 LTC2264-12 LTC2263-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l12 12 12 Bits

Integral Linearity Error Differential Analog Input (Note 6) l–1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 LSB

Differential Linearity Error Differential Analog Input l–0.5 ±0.1 0.5 –0.4 ±0.1 0.4 –0.5 ±0.1 0.5 LSB

Offset Error (Note 7) l–12 ±3 12 –12 ±3 12 –12 ±3 12 mV

Gain Error Internal Reference

External Reference

–2.4

–0.8

0.6

–2.4

–0.8

0.6

–2.4

–0.8

0.6

%FS

Offset Drift ±20 ±20 ±20 µV/°C

Full-Scale Drift Internal Reference

External Reference

±30

±10

±30

±10

±30

±10

ppm/°C

Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS

Offset Matching ±3 ±3 ±3 mV

Transition Noise External Reference 0.32 0.32 0.32 LSBRMS

ANALOG INPUT

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P

VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) lVCM – 100mV VCM VCM + 100mV V

VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V

IINCM Analog Input Common Mode Current Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

µA

IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l–1 1 µA

IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA

IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz

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LTC2265-12/

LTC2264-12/LTC2263-12

DYNAMIC ACCURACY

The l denotes the speciﬁcations which apply over the full operating temperature range,

otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2265-12 LTC2264-12 LTC2263-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

SNR Signal-to-Noise Ratio 5MHz Input

30MHz Input

70MHz Input

140MHz Input

69.9

70.9

70.6

69.7

70.9

70.8

70.5

69.4

70.5

70.2

dBFS

SFDR Spurious Free Dynamic Range

2nd or 3rd Harmonic

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

Spurious Free Dynamic Range

4th Harmonic or Higher

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

30MHz Input

70MHz Input

140MHz Input

69.6

70.9

70.7

70.3

69.6

70.8

70.7

70.6

70.2

69.2

70.5

70.4

70.3

69.9

dBFS

Crosstalk 10MHz Input –105 –105 –105 dBc

INTERNAL REFERENCE CHARACTERISTICS

The l denotes the speciﬁcations which apply over the

full operating temperature range, otherwise speciﬁcations are at TA = 25°C. AIN = –1dBFS. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V

VCM Output Temperature Drift ±25 ppm/°C

VCM Output Resistance –600µA < IOUT < 1mA 4 Ω

VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V

VREF Output Temperature Drift ±25 ppm/°C

VREF Output Resistance –400µA < IOUT < 1mA 7 Ω

VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

LTC2265-12/

LTC2264-12/LTC2263-12

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DIGITAL INPUTS AND OUTPUTS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODE INPUTS (ENC+, ENC– )

Differential Encode Mode (ENC– Not Tied to GND)

VID Differential Input Voltage (Note 8) l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set (Note 8)

1.1

1.2

1.6

VIN Input Voltage Range ENC+, ENC– to GND l0.2 3.6 V

RIN Input Resistance (See Figure 10) 10 kΩ

CIN Input Capacitance 3.5 pF

Single-Ended Encode Mode (ENC– Tied to GND)

VIH High Level Input Voltage VDD = 1.8V l1.2 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

VIN Input Voltage Range ENC+ to GND l0 3.6 V

RIN Input Resistance (See Figure 11) 30 kΩ

CIN Input Capacitance 3.5 pF

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

VIH High Level Input Voltage VDD = 1.8V l1.3 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

IIN Input Current VIN = 0V to 3.6V l–10 10 µA

CIN Input Capacitance 3 pF

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)

ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω

IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA

COUT Output Capacitance 3 pF

DIGITAL DATA OUTPUTS

VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

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LTC2265-12/

LTC2264-12/LTC2263-12

POWER REQUIREMENTS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS

LTC2265-12 LTC2264-12 LTC2263-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

IVDD Analog Supply Current Sine Wave Input l82 98 52 63 42 50 mA

IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

167

184

175

198

209

232

112

128

121

144

146

169

108

101

124

121

146

PSLEEP Sleep Mode Power 1 1 1 mW

PNAP Nap Mode Power 60 60 60 mW

PDIFFCLK Power Increase with Differential Encode Mode Enabled

(No Increase for Sleep Mode)

20 20 20 mW

TIMING CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2265-12 LTC2264-12 LTC2263-12

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

fSSampling Frequency (Notes 10, 11) l5 65 5 40 5 25 MHz

tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tAP Sample-and-Hold

Acquisition Delay Time

0 0 0 ns

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TIMING CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)

tSER Serial Data Bit Period Two Lanes, 16-Bit Serialization

Two Lanes, 14-Bit Serialization

Two Lanes, 12-Bit Serialization

One Lane, 16-Bit Serialization

One Lane, 14-Bit Serialization

One Lane, 12-Bit Serialization

1 / (8 • fS)

1 / (7 • fS)

1 / (6 • fS)

1 / (16 • fS)

1 / (14 • fS)

1 / (12 • fS)

tFRAME FR to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tDATA DATA to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tPD Propagation Delay (Note 8) l0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s

tROutput Rise Time Data, DCO, FR, 20% to 80% 0.17 ns

tFOutput Fall Time Data, DCO, FR, FR, 20% to 80% 0.17 ns

DCO Cycle-to-Cycle Jitter tSER = 1ns 60 psP-P

Pipeline Latency 6 Cycles

SPI Port Timing (Note 8)

tSCK SCK Period Write Mode

Readback Mode, CSDO = 20pF, RPULLUP = 2k

250

tSCS to SCK Set-Up Time l5 ns

tHSCK to CS Set-Up Time l5 ns

tDS SDI Set-Up Time l5 ns

tDH SDI Hold Time l5 ns

tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l125 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above VDD

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 5: V

= OV

= 1.8V, f

SAMPLE

= 65MHz (LTC2265), 40MHz

(LTC2264), or 25MHz (LTC2263), 2-lane output mode, differential ENC+/

ENC– = 2V

P-P

sine wave, input range = 2V

P-P

with differential drive, unless

otherwise noted.

Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a

best ﬁt straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code ﬂickers between 0000 0000 0000 and 1111 1111 1111 in

2’s complement output mode.

Note 8: Guaranteed by design, not subject to test.

Note 9: V

= OV

= 1.8V, f

SAMPLE

= 65MHz (LTC2265), 40MHz

(LTC2264), or 25MHz (LTC2263), 2-lane output mode, ENC+ = single-

ended 1.8V square wave, ENC– = 0V, input range = 2V

P-P

with differential

drive, unless otherwise noted. The supply current and power dissipation

speciﬁcations are totals for the entire chip, not per channel.

Note 10: Recommended operating conditions.

Note 11: The maximum sampling frequency depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

TIMING DIAGRAMS

2-Lane Output Mode, 16-Bit Serialization

226512 TD01

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 0 D11 D9 D7

D2 D0 DY*

DX*

DY*0 D10 D8 D6 D4 D2 D0 0 D10 D8 D6

tENCH tENCL

tSER

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

226512 TD02

tAP

N + 2

N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-3SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7

D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6

tENCH tENCL

tSER

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

2-Lane Output Mode, 14-Bit Serialization

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TIMING DIAGRAMS

2-Lane Output Mode, 12-Bit Serialization

226512 TD03

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR+

ENC+

DCO+

FR–

OUT#A+

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7

D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6

tENCH tENCL

tSER

226512 TD04

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

OUT#B+, OUT#B– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUT#A–

tFRAME tDATA tSER

tSER

tPD

DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX*DY* 0 0 D11 D10 D9 D8

tENCH tENCL

tSER

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

1-Lane Output Mode, 16-Bit Serialization

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

TIMING DIAGRAMS

1-Lane Output Mode, 14-Bit Serialization

1-Lane Output Mode, 12-Bit Serialization

226512 TD05

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

OUT#B+, OUT#B– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUT#A–

tFRAME tDATA tSER

tSER

tPD

D1 D0 DX* DY* DY*DX*D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8

tENCH tENCL

tSER

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

226512 TD06

tAP

N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUTA+

OUTB+, OUTB– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUTA–

tFRAME tDATA tSER

tSER

tPD

D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9

tENCH tENCL

tSER

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

SPI Port Timing (Readback Mode)

SPI Port Timing (Write Mode)

tStDS

A5 A4 A3 A2 A1 A0 XX

D7 D6 D5 D4 D3 D2 D1 D0

XX XX XX XX XX XX XX

SCK

SDI R/W

SDO HIGH IMPEDANCE

tDH

tDO

tSCK tH

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

226512 TD07

SCK

SDI R/W

SDO HIGH IMPEDANCE

TIMING DIAGRAMS

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2265-12: Integral

Nonlinearity (INL)

LTC2265-12: Differential

Nonlinearity (DNL)

LTC2265-12: 8k Point FFT, fIN = 5MHz

–1dBFS, 65Msps

OUTPUT CODE

–1.0

–0.4

–0.6

–0.8

INL ERROR (LSB)

–0.2

0.2

0.8

0.4

0.6

1.0

1024 2048 3072 4096

226512 G01

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

1024 2048 3072 4096

226512 G02

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

226512 G03

0 10 20 30

LTC2265-12: 8k Point FFT,

fIN = 30MHz, –1dBFS, 65Msps

LTC2265-12: 8k Point FFT,

fIN = 70MHz, –1dBFS, 65Msps

LTC2265-12: 8k Point FFT,

fIN = 140MHz, –1dBFS, 65Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

226512 G04

10 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

226512 G05

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

226512 G06

LTC2265-12: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

65Msps

LTC2265-12: Shorted Input

Histogram

LTC2265-12: SNR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

226512 G07

OUTPUT CODE

2049

2000

10000

8000

6000

4000

COUNT

12000

16000

14000

18000

2051 20522050 2053

226512 G08

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

226512 G09

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

IOVDD vs Sample Rate, 5MHz Sine

Wave Input, –1dBFS

LTC2265-12: SNR vs SENSE,

fIN = 5MHz, –1dBFS

LTC2264-12: Integral Nonlinearity

(INL)

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

1024 2048 3072 4096

226512 G17

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

226512 G18

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

226512 G15

OUTPUT CODE

–1.0

–0.4

–0.6

–0.8

INL ERROR (LSB)

–0.2

0.2

0.4

0.6

0.8

1.0

1024 2048 3072 4096

226512 G16

LTC2264-12: Differential

Nonlinearity (DNL)

LTC2264-12: 8k Point FFT, fIN =

5MHz, –1dBFS, 40Msps

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2265-12: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 65Msps

LTC2265-12: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2265-12: SFDR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

226512 G10

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

226512 G11

dBFS

dBc

INPUT LEVEL(dBFS)

–60

SNR (dBc AND dBFS)

–50 –40 –30 –20 –10 0

226512 G12

dBc

dBFS

SAMPLE RATE (Msps)

IVDD (mA)

0 10 20 30 40 50 60

226512 G13

SAMPLE RATE (Msps)

IOVDD (mA)

0 10 20 30 40 50 60

226512 G14

1-LANE, 1.75mA

2-LANE, 3.5mA

2-LANE, 1.75mA

1-LANE, 3.5mA

LTC2265-12: SNR vs Input Level,

fIN = 70MHz, 2V Range, 65Msps

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2264-12: 8k Point FFT,

fIN = 69MHz, –1dBFS, 40Msps

LTC2264-12: 8k Point FFT,

fIN = 139MHz, –1dBFS, 40Msps

LTC2264-12: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

40Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

226512 G20

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

226512 G21

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

226512 G22

LTC2264-12: Shorted Input

Histogram

LTC2264-12: SNR vs Input

Frequency, –1dBFS, 2V Range,

40Msps

LTC2264-12: SFDR vs Input

Frequency, –1dBFS, 2V Range,

40Msps

OUTPUT CODE

2049

2000

6000

4000

COUNT

8000

16000

14000

12000

10000

18000

2051 20522050 2053

226512 G23

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

226512 G24

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

226512 G25

LTC2264-12: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2264-12: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 40Msps

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

226512 G26

dBFS

dBc

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

226512 G19

LTC2264-12: 8k Point FFT,

fIN = 29MHz, –1dBFS, 40Msps

SAMPLE RATE (Msps)

IVDD (mA)

0 10 20 30 40

226512 G27

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2263-12: Integral Nonlinearity

(INL)

LTC2263-12: Differential

Nonlinearity (DNL)

OUTPUT CODE

–1.0

–0.4

–0.6

–0.8

INL ERROR (LSB)

–0.2

0.4

0.6

0.2

0.8

1.0

1024 2048 3072 4096

226512 G29

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

1024 2048 3072 4096

226512 G30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

226512 G31

LTC2263-12: 8k Point FFT,

fIN = 5MHz, –1dBFS, 25Msps

LTC2263-12: 8k Point FFT,

fIN = 30MHz, –1dBFS, 25Msps

LTC2263-12: 8k Point FFT,

fIN = 70MHz, –1dBFS, 25Msps

LTC2263-12: 8k Point FFT,

fIN = 140MHz, –1dBFS, 25Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

226512 G32

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

226512 G33

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

226512 G34

LTC2263-12: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

25Msps

LTC2263-12: Shorted Input

Histogram

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

226512 G35

OUTPUT CODE

2049

2000

4000

6000

8000

12000

10000

COUNT

14000

16000

18000

2051 20522050 2053

226512 G36

LTC2264-12: SNR vs SENSE,

fIN = 5MHz, –1dBFS

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

226512 G28

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

LTC2263-12: SNR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

226512 G37

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2263-12: SFDR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

226512 G38

LTC2263-12: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 25Msps

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

226512 G39

dBFS

dBc

LTC2263-12: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2263-12: SNR vs SENSE,

fIN = 5MHz, –1dBFS

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31.0

226512 G41

SAMPLE RATE (Msps)

IVDD (mA)

0 5 10 15 20 25

226512 G40

SERIAL DATA RATE (Mbps)

350

300

250

200

150

100

PEAK-TO-PEAK JITTER (ps)

0 200 400 600 800 1000

226512 G42

DCO Cycle-Cycle Jitter vs Serial

Data Rate

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

PIN FUNCTIONS

AIN1+ (Pin 1): Channel 1 Positive Differential Analog

Input.

AIN1– (Pin 2): Channel 1 Negative Differential Analog

Input.

VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal

to VDD/2. VCM should be used to bias the common mode

of the analog inputs of channel 1. Bypass to ground with

a 0.1µF ceramic capacitor.

REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7

with a 2.2µF ceramic capacitor, and to ground with a 0.1µF

ceramic capacitor.

REFL (Pins 6, 7): ADC Low Reference. Bypass to pins 4, 5

with a 2.2µF ceramic capacitor, and to ground with a 0.1µF

ceramic capacitor.

VCM2 (Pin 8): Common Mode Bias Output, Nominally Equal

to VDD/2. VCM should be used to bias the common mode

of the analog inputs of channel 2. Bypass to ground with

a 0.1µF ceramic capacitor.

AIN2+ (Pin 9): Channel 2 Positive Differential Analog

Input.

AIN2– (Pin 10): Channel 2 Negative Differential Analog

Input.

VDD (Pins 11, 12, 39, 40): Analog Power Supply, 1.7V

to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.

Adjacent pins can share a bypass capacitor.

ENC+ (Pin 13): Encode Input. Conversion starts on the

rising edge.

ENC– (Pin 14): Encode Complement Input. Conversion

starts on the falling edge.

CS (Pin 15): In serial programming mode (PAR/SER = 0V),

CS is the serial interface chip select input. When CS is low,

SCK is enabled for shifting data on SDI into the mode

control registers. In parallel programming mode (PAR/SER

= VDD), CS selects 2-lane or 1-lane output mode. CS can

be driven with 1.8V to 3.3V logic.

SCK (Pin 16): In serial programming mode (PAR/SER

= 0V), SCK is the serial interface clock input. In parallel

programming mode (PAR/SER = VDD), SCK selects 3.5mA

or 1.75mA LVDS output currents. SCK can be driven with

1.8V to 3.3V logic.

SDI (Pin 17): In serial programming mode (PAR/SER =

0V), SDI is the serial interface data input. Data on SDI

is clocked into the mode control registers on the rising

edge of SCK. In parallel programming mode (PAR/SER =

VDD), SDI can be used to power down the part. SDI can

be driven with 1.8V to 3.3V logic.

GND (Pins 18, 33, 37, Exposed Pad Pin 41): ADC Power

Ground. The exposed pad must be soldered to the PCB

ground.

OGND (Pin 25): Output Driver Ground. Must be shorted

to the ground plane by a very low inductance path. Use

multiple vias close to the pin.

OVDD (Pin 26): Output Driver Supply, 1.7V to 1.9V. Bypass

to ground with a 0.1µF ceramic capacitor.

SDO (Pin 34): In serial programming mode (PAR/SER

= 0V), SDO is the optional serial interface data output.

Data on SDO is read back from the mode control registers

and can be latched on the falling edge of SCK. SDO is an

open-drain NMOS output that requires an external 2k pull-

up resistor of 1.8V to 3.3V. If readback from the mode

control registers is not needed, the pull-up resistor is not

necessary and SDO can be left unconnected. In parallel

programming mode (PAR/SER = VDD), SDO is an input that

enables internal 100Ω termination resistors on the digital

outputs. When used as an input, SDO can be driven with

1.8V to 3.3V logic through a 1k series resistor.

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

PAR/SER (Pin 35): Programming Mode Selection Pin.

Connect to ground to enable the serial programming

mode. CS, SCK, SDI and SDO become a serial interface

that controls the A/D operating modes. Connect to VDD

to enable parallel programming mode where CS, SCK,

SDI and SDO become parallel logic inputs that control a

reduced set of the A/D operating modes. PAR/SER should

be connected directly to ground or the VDD of the part and

not be driven by a logic signal.

VREF (Pin 36): Reference Voltage Output. Bypass to ground

with a 1µF ceramic capacitor, nominally 1.25V.

SENSE (Pin 38): Reference Programming Pin. Connect-

ing SENSE to VDD selects the internal reference and a

±1V input range. Connecting SENSE to ground selects

the internal reference and a ±0.5V input range. An external

reference between 0.625V and 1.3V applied to SENSE

selects an input range of ±0.8 • VSENSE.

LVDS OUTPUTS

The following pins are differential LVDS outputs. The

output current level is programmable. There is an op-

tional internal 100Ω termination resistor between the

pins of each LVDS output pair.

OUT2B–/OUT2B+, OUT2A–,OUT2A+ (Pins 19/20, 21/22):

Serial Data Outputs for Channel 2. In 1-lane output mode,

only OUT2A–/OUT2A+ are used.

FR–/FR+ (Pin 23/Pin 24): Frame Start Output.

DCO–/DCO+ (Pin 27/Pin 28): Data Clock Output.

OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 29/30, 31/32):

Serial Data Outputs for Channel 1. In 1-lane output mode,

only OUT1A–/OUT1A+ are used.

PIN FUNCTIONS

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

FUNCTIONAL BLOCK DIAGRAM

Figure 1. Functional Block Diagram

PLL

DATA

SERIALIZER

SAMPLE-

AND-HOLD

12-BIT

ADC CORE

CHANNEL 1

ANALOG

INPUT

12-BIT

ADC CORE

CHANNEL 2

ANALOG

INPUT

1.8V

VDD

1.8VENC+ENC–

OVDD

VDD/2

DIFF

REF

AMP

REF

BUF

2.2µF

0.1µF 0.1µF

0.1µF

REFH REFL

RANGE

SELECT

1.25V

REFERENCE

REFH REFL

OUT1A

OUT1B

OUT2A

OUT2B

DATA

CLOCK OUT

FRAME

OGND

VCM1

GND VCM2

0.1µF0.1µF SDOCS

SENSE

VREF

1µF

MODE

CONTROL

REGISTERS

SCKPAR/SER SDI

226512 F01

SAMPLE-

AND-HOLD

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

CONVERTER OPERATION

The LTC2265-12/LTC2264-12/LTC2263-12 are low power,

2-channel, 12-bit, 65Msps/40Msps/25Msps A/D convert-

ers that are powered by a single 1.8V supply. The analog

inputs should be driven differentially. The encode input can

be driven differentially for optimal jitter performance, or

single-ended for lower power consumption. To minimize

the number of data lines, the digital outputs are serial LVDS.

Each channel outputs two bits at a time (2-lane mode) or

one bit at a time (1-lane mode). Many additional features

can be chosen by programming the mode control registers

through a serial SPI port.

ANALOG INPUT

The analog inputs are differential CMOS sample-and-hold

circuits (Figure 2). The inputs should be driven differentially

around a common mode voltage set by the VCM1 or VCM2

output pins, which are nominally VDD/2. For the 2V input

range, the inputs should swing from VCM – 0.5V to VCM

+ 0.5V. There should be a 180° phase difference between

the inputs.

The two channels are simultaneously sampled by a

shared encode circuit (Figure 2).

INPUT DRIVE CIRCUITS

Input Filtering

If possible, there should be an RC lowpass ﬁlter right

at the analog inputs. This lowpass ﬁlter isolates the

drive circuitry from the A/D sample-and-hold switching

and limits wideband noise from the drive circuitry.

Figure 3 shows an example of an input RC ﬁlter. The

RC component values should be chosen based on the

application’s input frequency.

APPLICATIONS INFORMATION

Transformer Coupled Circuits

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

tap is biased with VCM, setting the A/D input at its opti-

mal DC level. At higher input frequencies a transmission

line balun transformer (Figures 4 to 6) has better balance,

resulting in lower A/D distortion.

CSAMPLE

3.5pF

RON

25Ω

RON

25Ω

VDD

LTC2265-12

AIN+

226512 F02

CSAMPLE

3.5pF

VDD

AIN–

ENC–

ENC+

1.2V

10k

1.2V

10k

CPARASITIC

1.8pF

CPARASITIC

1.8pF

10Ω

10Ω

Figure 2. Equivalent Input Circuit. Only One of

the Two Analog Channels Is Shown.

25Ω

25Ω 25Ω

25Ω

50Ω

0.1µF

AIN+

AIN–

12pF

0.1µF

VCM

LTC2265-12

ANALOG

INPUT

0.1µF T1

1:1

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

226512 F03

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

Ampliﬁer Circuits

Figure 7 shows the analog input being driven by a high speed

differential ampliﬁer. The output of the ampliﬁer is AC-

coupled to the A/D so the ampliﬁer’s output common mode

voltage can be optimally set to minimize distortion.

25Ω

50Ω

0.1µF

AIN+

AIN–

4.7pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM MABA-007159-000000

T2: MA/COM MABAES0060

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

226512 F04

LTC2265-12

25Ω

50Ω

0.1µF

AIN+

AIN–

1.8pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1LB

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

226512 F05

LTC2265-12

25Ω

50Ω

0.1µF

2.7nH

AIN+

AIN–

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

226512 F06

LTC2265-12

25Ω

200Ω

0.1µF AIN+

AIN–

12pF

0.1µF

VCM

LTC2265-12

226512 F07

––

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

0.1µF

Figure 5. Recommended Front-End Circuit for Input

Frequencies from 170MHz to 300MHz

Figure 6. Recommended Front-End Circuit for Input

Frequencies Above 300MHz

Figure 4. Recommended Front-End Circuit for Input

Frequencies from 70MHz to 170MHz

Figure 7. Front-End Circuit Using a High Speed

Differential Ampliﬁer

APPLICATIONS INFORMATION

At very high frequencies an RF gain block will often have

lower distortion than a differential ampliﬁer. If the gain

block is single-ended, then a transformer circuit (Figures

4 to 6) should convert the signal to differential before

driving the A/D.

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

Reference

The LTC2265-12/LTC2264-12/LTC2263-12 has an internal

1.25V voltage reference. For a 2V input range using the

internal reference, connect SENSE to VDD. For a 1V input

range using the internal reference, connect SENSE to

ground. For a 2V input range with an external reference,

apply a 1.25V reference voltage to SENSE (Figure 9).

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

will then be 1.6 • VSENSE.

The reference is shared by both ADC channels, so it is

not possible to independently adjust the input range of

individual channels.

The VREF, REFH and REFL pins should be bypassed, as

shown in Figure 8. The 0.1µF capacitor between REFH and

REFL should be as close to the pins as possible (not on

the backside of the circuit board).

APPLICATIONS INFORMATION

VREF

REFH

SENSE

TIE TO VDD FOR 2V RANGE;

TIE TO GND FOR 1V RANGE;

RANGE = 1.6 • VSENSE FOR

0.625V < VSENSE < 1.300V

1.25V

REFL

0.1µF2.2µF

INTERNAL ADC

HIGH REFERENCE

BUFFER

5Ω

0.8x

DIFF AMP

INTERNAL ADC

LOW REFERENCE

1.25V BANDGAP

REFERENCE

0.625V

RANGE

DETECT

AND

CONTROL

1µF

0.1µF

LTC2265-12

226512 F08

Figure 8. Reference Circuit

SENSE

1.25V

EXTERNAL

REFERENCE

1µF

VREF

226512 F09

LTC2265-12

Figure 9. Using an External 1.25V Reference

VDD

LTC2265-12

226512 F10

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

30k

ENC+

ENC–

226512 F11

1.8V TO 3.3V

LTC2265-12

CMOS LOGIC

BUFFER

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

APPLICATIONS INFORMATION

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12 and 13).

The encode inputs are internally biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

above VDD (up to 3.6V), and the common mode range

is from 1.1V to 1.6V. In the differential encode mode,

ENC– should stay at least 200mV above ground to avoid

falsely triggering the single-ended encode mode. For

good jitter performance ENC+ should have fast rise and

fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

encode input. ENC+ can be taken above VDD (up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The

ENC+ threshold is 0.9V. For good jitter performance

ENC+ should have fast rise and fall times.

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

DIGITAL OUTPUTS

The digital outputs of the LTC2265-12/LTC2264-12/

LTC2263-12 are serialized LVDS signals. Each channel

outputs two bits at a time (2-lane mode) or one bit at a

time (1-lane mode). The data can be serialized with 16-,

14-, or 12-bit serialization (see the Timing Diagrams sec-

tion for details).

The output data should be latched on the rising and falling

edges of the data clockout (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversion result begins. In the 2-lane, 14-bit serialization

mode, the frequency of the FR output is halved.

The maximum serial data rate for the data outputs is

1Gbps, so the maximum sample rate of the ADC will de-

pend on the serialization mode as well as the speed grade

of the ADC (see Table 1). The minimum sample rate for

all serialization modes is 5Msps.

50Ω 100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2265-12

226512 F12

ENC–

ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1µF

226512 F13

LTC2265-12

Figure 12. Sinusoidal Encode Drive

Figure 13. PECL or LVDS Encode Drive

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

By default the outputs are standard LVDS levels: a 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

The outputs are powered by OVDD and OGND which are

isolated from the A/D core power and ground.

Programmable LVDS Output Current

The default output driver current is 3.5mA. This current can

be adjusted by control register A2 in serial programming

mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,

3mA, 3.5mA, 4mA and 4.5mA. In parallel programming

mode the SCK pin can select either 3.5mA or 1.75mA.

Optional LVDS Driver Internal Termination

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

be enabled by serially programming mode control register

A2. The internal termination helps absorb any reﬂections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is doubled to maintain the same output voltage swing. In

parallel programming mode the SDO pin enables internal

termination. Internal termination should only be used with

1.75mA, 2.1mA or 2.5mA LVDS output current modes.

Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling

Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12).

SERIALIZATION MODE

MAXIMUM SAMPLING

FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE

2-Lane 16-Bit Serialization 65 4 • fSfS8 • fS

2-Lane 14-Bit Serialization 65 3.5 • fS0.5 • fS7 • fS

2-Lane 12-Bit Serialization 65 3 • fSfS6 • fS

1-Lane 16-Bit Serialization 62.5 8 • fSfS16 • fS

1-Lane 14-Bit Serialization 65 7 • fSfS14 • fS

1-Lane 12-Bit Serialization 65 6 • fSfS12 • fS

APPLICATIONS INFORMATION

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

In addition to the 12 data bits (D11 - D0), two additional

bits (DX and DY) are sent out in the 14-bit and 16-bit

serialization modes. These extra bits are to ensure com-

plete software compatibility with the 14-bit versions of

these A/Ds. During normal operation when the analog

inputs are not overranged, DX and DY are always logic 0.

When the analog inputs are overranged positive, DX and DY

become logic 1. When the analog inputs are overranged

negative, DX and DY become logic 0. DX and DY can also

be controlled by the digital output test pattern. See the

Timing Diagrams section for more information.

Table 2. Output Codes vs Input Voltage

AIN+ – AIN–

(2V RANGE)

D11-D0

(OFFSET BINARY)

D11-D0

(2’s COMPLEMENT)

DX, DY

>+1.000000V

+0.999512V

+0.999024V

1111 1111 1111

1111 1111 1110

0111 1111 1111

0111 1111 1110

+0.000488V

0.000000V

–0.000488V

–0.000976V

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

–0.999512V

–1.000000V

≤–1.000000V

0000 0000 0001

0000 0000 0000

1000 0000 0001

1000 0000 0000

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

APPLICATIONS INFORMATION

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

amplitude.

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The FR and DCO outputs are

not affected. The output randomizer is enabled by serially

programming mode control register A1.

Digital Output Test Pattern

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D11-D0, DX, DY) of all channels to known values. The

digital output test patterns are enabled by serially program-

ming mode control registers A3 and A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement and randomizer.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs, including DCO and FR, are disabled to save

power or enable in-circuit testing. When disabled, the com-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire chip is powered down,

resulting in 1mW power consumption. Sleep mode is

enabled by mode control register A1 (serial program-

ming mode), or by SDI (parallel programming mode).

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on VREF,

REFH and REFL. For the suggested values in Figure 8, the

A/D will stabilize after 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing faster wake-up than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands a very accurate DC

settling, then an additional 50µs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by the mode control

DEVICE PROGRAMMING MODES

The operating modes of the LTC2265-12/LTC2264-12/

LTC2263-12 can be programmed by either a parallel

interface or a simple serial interface. The serial interface

has more ﬂexibility and can program all available modes.

The parallel interface is more limited and can only program

some of the more commonly used modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)

PIN DESCRIPTION

CS 2-Lane/1-Lane Selection Bit

0 = 2-Lane, 16-Bit Serialization Output Mode

1 = 1-Lane, 14-Bit Serialization Output Mode

SCK LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

SDI Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO Internal Termination Selection Bit

0 = Internal Termination Disabled

1 = Internal Termination Enabled

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

APPLICATIONS INFORMATION

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the ﬁrst 16 rising edges of

SCK. Any SCK rising edges after the ﬁrst 16 are ignored.

The data transfer ends when CS is taken high again.

The ﬁrst bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The ﬁnal eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be written

to the register set by the address bits (A6:A0). If the R/W

bit is high, data in the register set by the address bits (A6:

Table 4. Serial Programming Mode Register Map (PAR/SER = GND)

D7 D6 D5 D4 D3 D2 D1 D0

RESET X X X X X X X

Bit 7 RESET Software Reset Bit

0 = Not Used

1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode.

This Bit Is Automatically Set Back to Zero at the End of the SPI Write Command.

The Reset Register is Write Only

Bits 6-0 Unused, Don’t Care Bits.

D7 D6 D5 D4 D3 D2 D1 D0

DCSOFF RAND TWOSCOMP SLEEP NAP_2 X X NAP_1

Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer On

1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.

Bit 6 RAND Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

Bit 5 TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

Bits 4, 3, 0 SLEEP: NAP_2: NAP_1 Sleep/Nap Mode Control Bits

000 = Normal Operation

0X1 = Channel 1 in Nap Mode

01X = Channel 2 in Nap Mode

1XX = Sleep Mode. Both Channels are disabled

Note: Any Combination of Channels Can Be Placed in Nap Mode.

Bits 1, 2 Unused, Don’t Care Bit

A0) will be read back on the SDO pin (see the Timing Dia-

grams section). During a readback command the register

is not updated and data on SDI is ignored.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back through

SDO, an external 2k pull-up resistor is required. If serial

data is only written and readback is not needed, then SDO

can be left ﬂoating and no pull-up resistor is needed. Table

4 shows a map of the mode control registers.

Software Reset

If serial programming is used, the mode control registers

should be programmed as soon as possible after the power

supplies turn on and are stable. The ﬁrst serial command

must be a software reset which will reset all register data bits

to logic 0. To perform a software reset, bit D7 in the reset

command is complete, bit D7 is automatically set back to zero.

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

D7 D6 D5 D4 D3 D2 D1 D0

ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0

Bits 7-5 ILVDS2: ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 4 TERMON LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be

used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.

Bit 3 OUTOFF Output Disable Bit

0 = Digital Outputs are enabled.

1 = Digital Outputs are disabled.

Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits

000 = 2-Lanes, 16-Bit Serialization

001 = 2-Lanes, 14-Bit Serialization

010 = 2-Lanes, 12-Bit Serialization

011 = Not Used

100 = Not Used

101 = 1-Lane, 14-Bit Serialization

110 = 1-Lane, 12-Bit Serialization

111 = 1-Lane, 16-Bit Serialization

D7 D6 D5 D4 D3 D2 D1 D0

OUTTEST X TP11 TP10 TP9 TP8 TP7 TP6

Bit 7 OUTTEST Digital Output Test Pattern Control Bit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Bit 6 Unused, Don’t Care Bit.

Bits 5-0 TP11:TP6 Test Pattern Data Bits (MSB)

TP11:TP6 Set the Test Pattern for Data Bit 11 (MSB) Through Data Bit 6.

D7 D6 D5 D4 D3 D2 D1 D0

TP5 TP4 TP3 TP2 TP1 TP0 TPX TPY

Bits 7-2 TP5:TP0 Test Pattern Data Bits (LSB)

TP5:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).

Bits 1-0 TPX:TPY Set the Test Pattern for Extra Bits DX and DY. These Bits are for Compatibility with the 14-Bit Version of the A/D.

APPLICATIONS INFORMATION

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

GROUNDING AND BYPASSING

The LTC2265-12/LTC2264-12/LTC2263-12 requires a

printed circuit board with a clean unbroken ground plane.

A multilayer board with an internal ground plane in the

ﬁrst layer beneath the ADC is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass

capacitors must be located as close to the pins as possible.

Of particular importance is the 0.1µF capacitor between

REFH and REFL. This capacitor should be on the same

side of the circuit board as the A/D, and as close to the

device as possible (1.5mm or less). Size 0402 ceramic

APPLICATIONS INFORMATION

capacitors are recommended. The larger 2.2µF capacitor

between REFH and REFL can be somewhat further away.

The traces connecting the pins and bypass capacitors must

be kept short and should be made as wide as possible.

The analog inputs, encode signals and digital outputs

should not be routed next to each other. Ground ﬁll and

grounded vias should be used as barriers to isolate these

signals from each other.

HEAT TRANSFER

Most of the heat generated by the LTC2265-12/LTC2264-12/

LTC2263-12 is transferred from the die through the bot-

tom-side Exposed Pad and package leads onto the printed

circuit board. For good electrical and thermal performance,

the Exposed Pad must be soldered to a large grounded

pad on the PC board. This pad should be connected to the

internal ground planes by an array of vias.

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TYPICAL APPLICATIONS

Silkscreen Top Top Side

Inner Layer 2 GND Inner Layer 3

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

TYPICAL APPLICATIONS

Inner Layer 4 Inner Layer 5 Power

Bottom Side Silkscreen Bottom

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TYPICAL APPLICATIONS

LTC2265

1AIN1+

AIN1–

VCM1

REFH

REFL

VCM2

AIN2+

AIN2–

VDD

SENSE

GND

VREF

PAR/SER

SDO

GND

OUT1A+

OUT1A–

3940 38 37 36

SDO

PAR/SER

SENSE

VDD

35 34 33 32 31

C59

0.1µF

C29

0.1µF

C30

0.1µF

2.2µF

0.1µF

OVDD

AIN1

AIN2

226512 TA03

DIGITAL

OUTPUTS

DIGITAL

OUTPUTS

OUT1B+

OUT1B–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT2A+

OUT2A–

C16

0.1µF

1µF

VDD

ENC+

ENC–

SCK

SDI

GND

OUT2B–

OUT2B+

1211

VDD

13 14 15 16 17 18 19 20

0.1µF

SPI BUS

C46

0.1µF

C47

0.1µF

ENCODE

CLOCK

ENCODE

CLOCK

LTC2265 Schematic

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UJ Package

40-Lead (6mm × 6mm) Plastic QFN

(Reference LTC DWG # 05-08-1728)

6.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.45 OR

0.35 × 45°

CHAMFER

0.40 ± 0.10

4039

BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES)

4.42 ± 0.10

4.42 ± 0.05

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UJ40) QFN REV Ø 0406

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ± 0.05

4.50 ± 0.05

(4 SIDES)

5.10 ± 0.05

6.50 ± 0.05

0.25 ± 0.05

0.50 BSC

PACKAGE OUTLINE

R = 0.10

TYP

LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 4/10 Revised Maximum Value for LTC2264-12 Sampling Frequency in Timing Characteristics

Updated Title of Curve G53 in Typical Performance Characteristics

Revised Descriptions and Comments in Related Parts Section

B 7/11 Revised Software Reset paragraph and Table 4 in Applications Information section 26

22654312fb

LTC2265-12/

LTC2264-12/LTC2263-12

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2010

LT 0711 REV B • PRINTED IN USA

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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14-Bit, 25Msps/40Msps/65Msps

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LTC2268-14

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LTC2266-12/LTC2267-12/

LTC2268-12

12-Bit, 80Msps/105Msps/125Msps

1.8V Dual ADCs, Ultralow Power

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LTC5517 40MHz to 900MHz Direct Conversion

Quadrature Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LTC5527 400MHz to 3.7GHz High Linearity

Downconverting Mixer

24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 1900MHz, NF = 12.5dB,

50Ω Single-Ended RF and LO Ports, 5V Supply

LTC5557 400MHz to 3.8GHz High Linearity

Downconverting Mixer

24.7dBm IIP3 at 1950MHz, 23.7dBm IIP3 at 2.6GHz, NF = 13.2dB, 3.3V Supply

Operation, Integrated Transformer

LTC5575 800MHz to 2.7GHz Direct Conversion

Quadrature Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF

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Amplifiers/Filters

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Variable Gain Amplifier

Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise

Figure, 4mm × 4mm QFN-24

LTC6420-20 Dual Low Noise, Low Distortion

Differential ADC Drivers for 300MHz IF

Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 46dBm OIP3 at 100MHz,

80mA Supply Current per Amplifier, 3mm × 4mm QFN-20

LTC6421-20 Dual Low Noise, Low Distortion

Differential ADC Drivers for 140MHz IF

Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 42dBm OIP3 at 100MHz,

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LTC6605-7/LTC6605-10/

LTC6605-14

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with ADC Drivers

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Pin-Programmable Gain, 6mm × 3mm DFN-22

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Subsystem

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