1
®
FN4900.9
ICL3225E, ICL3227E, ICL3245E
±15kV ESD Protected, +3V to +5.5V,
1Microamp, 1Mbps, RS-232 Transceivers
with Enhanced Automatic Powerdown
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at VCC = 3.0V. Additionally,
they provide ±15kV ESD protection (IEC61000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and enhanced automatic powerdown
functions, reduce the standby supply current to a 1µA trickle.
Small footprint packaging, and the use of small, low value
capacitors ensure board space savings as well. Data rates
greater than 1Mbps are guaranteed at worst case load
conditions. This family is fully compatible with 3.3V only
systems, mixed 3.3V and 5.0V systems, and 5.0V only
systems.
The ICL3245E is a 3 driver, 5 receiver device that provides a
complete serial port suitable for laptop or notebook
computers. It also includes a noninverting always-active
receiver for “wake-up” capability.
These devices, feature an enhanced automatic
powerdown function which powers down the on-chip power-
supply and driver circuits. This occurs when all receiver and
transmitter inputs detect no signal transitions for a period of
30s. These devices power back up, automatically, whenever
they sense a transition on any transmitter or receiver input.
Table 1 summarizes the features of the device represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
(see Ordering Info)
• ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000)
• Manual and Enhanced Automatic Powerdown Features
• Drop in Replacements for MAX3225E, MAX3227E,
MAX3245E
• RS-232 Compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four External
0.1µF Capacitors
• Guaranteed Mouse Driveability (ICL3245E)
• “Ready to Transmit” Indicator Output
(ICL3225E/ICL3227E)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate . . . . . . . . . . . . . . 1Mbps
• Low Skew at Transmitter/Receiver Input Trip Points . . . 10ns
• Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . 24V/µs
• Wide Power Supply Range . . . . . . . Single +3V to +5.5V
• Low Supply Current in Powerdown State. . . . . . . . . . .1µA
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and Other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
NO. OF
Tx.
NO. OF
Rx.
NO. OF
MONITOR Rx.
(ROUTB)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWER-
DOWN?
ENHANCED
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3225E 2 2 0 1000 No Yes Yes Yes
ICL3227E 1 1 0 1000 No Yes Yes Yes
ICL3245E 3 5 1 1000 No No Yes Yes
Data Sheet February 27, 2006
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2001, 2003-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN4900.9
February 27, 2006
Ordering Information
PART NO. *
PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
ICL3225ECA ICL3225ECA 0 to 70 20 Ld SSOP M20.209
ICL3225ECAZ
(Note 1)
ICL3225ECAZ 0 to 70 20 Ld SSOP
(Pb-free)
M20.209
ICL3225ECP ICL3225ECP 0 to 70 20 Ld PDIP E20.3
ICL3225ECPZ
(Note 1)
3225ECPZ 0 to 70 20 Ld PDIP**
(Pb-free)
E20.3
ICL3225EIA ICL3225EIA -40 to 85 20 Ld SSOP M20.209
ICL3225EIAZ
(Note 1)
ICL3225EIAZ -40 to 85 20 Ld SSOP
(Pb-free)
M20.209
ICL3227ECA ICL3227ECA 0 to 70 16 Ld SSOP M16.209
ICL3227ECAZA
(Note 1)
3227ECAZ 0 to 70 16 Ld SSOP
(Pb-free)
M16.209
ICL3227EIA ICL3227EIA -40 to 85 16 Ld SSOP M16.209
ICL3227EIAZA
(Note 1)
3227EIAZ -40 to 85 16 Ld SSOP
(Pb-free)
M16.209
ICL3245ECA ICL3245ECA 0 to 70 28 Ld SSOP M28.209
ICL3245ECAZ
(Note 1)
ICL3245ECAZ 0 to 70 28 Ld SSOP
(Pb-Free)
M28.209
ICL3245ECB ICL3245ECB 0 to 70 28 Ld SOIC M28.3
ICL3245ECBZ
(Note 1)
ICL3245ECBZ 0 to 70 28 Ld SOIC
(Pb-free)
M28.3
ICL3245ECV ICL3245ECV 0 to 70 28 Ld TSSOP M28.173
ICL3245ECVZ
(Note 1)
ICL3245ECVZ 0 to 70 28 Ld TSSOP
(Pb-free)
M28.173
ICL3245EIA ICL3245EIA -40 to 85 28 Ld SSOP M28.209
ICL3245EIAZ
(Note 1)
ICL3245EIAZ -40 to 85 28 Ld SSOP
(Pb-free)
M28.209
ICL3245EIB ICL3245EIB -40 to 85 28 Ld SOIC M28.3
* Most surface mount devices are available on tape and reel; add “-T” to
suffix.
**Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE:
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NO. *
PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
PKG.
DWG. #
Pinouts
ICL3225E (PDIP, SSOP)
TOP VIEW
ICL3227E (SSOP)
TOP VIEW
READY
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
FORCEOFF
GND
T1OUT
R1IN
R1OUT
T1IN
INVALID
VCC
FORCEON
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
READY
C1+
V+
C1-
C2+
C2-
V-
R1IN
FORCEOFF
GND
T1OUT
FORCEON
T1IN
R1OUT
VCC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ICL3225E, ICL3227E, ICL3245E
3FN4900.9
February 27, 2006
ICL3245E (SOIC, SSOP, TSSOP)
TOP VIEW
Pinouts (Continued)
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
FORCEON
INVALID
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
FORCEOFF
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
Pin Descriptions
PIN FUNCTION
VCC System power supply input (3.0V to 5.5V).
V+ Internally generated positive transmitter supply (+5.5V).
V- Internally generated negative transmitter supply (-5.5V).
GND Ground connection.
C1+ External capacitor (voltage doubler) is connected to this lead.
C1- External capacitor (voltage doubler) is connected to this lead.
C2+ External capacitor (voltage inverter) is connected to this lead.
C2- External capacitor (voltage inverter) is connected to this lead.
TIN TTL/CMOS compatible transmitter Inputs.
TOUT ±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
RIN ±15kV ESD Protected, RS-232 compatible receiver inputs.
ROUT TTL/CMOS level receiver outputs.
ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
READY Active high output that indicates when the ICL32XXE is ready to transmit (i.e., V- ≤ -4V).
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
ICL3225E, ICL3227E, ICL3245E
4FN4900.9
February 27, 2006
Typical Operating Circuits
ICL3225E
ICL3227E
19
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
13
12
17
8
2
43
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
16
5kΩ
R2OUT R2IN
910
5kΩ
15
C1
C2
+C3
C4
READY
1
GND
+3.3V +0.1µF
18
TTL/CMOS
LOGIC LEVELS RS-232
LEVELS
R1
R2
FORCEON
FORCEOFF
14
20 VCC
11
INVALID TO POWER
CONTROL LOGIC
15
VCC
T1OUT
T1IN
T1
0.1µF
+0.1µF
+
0.1µF
11 13
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
R1
89
5kΩ
C1
C2
+C3
C4
READY
1
GND
+3.3V +0.1µF
14
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
FORCEON
FORCEOFF
12
16 VCC
10
INVALID TO POWER
CONTROL LOGIC
ICL3225E, ICL3227E, ICL3245E
5FN4900.9
February 27, 2006
ICL3245E
Typical Operating Circuits (Continued)
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+
0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
FORCEON
FORCEOFF
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
RS-232
LEVELS
R1
R2
R3
R4
21 INVALID
TO POWER
CONTROL LOGIC
ICL3225E, ICL3227E, ICL3245E
6FN4900.9
February 27, 2006
Absolute Maximum Ratings Thermal Information
VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
TIN, FORCEOFF, FORCEON. . . . . . . . . . . . . . . . . . . -0.3V to 6V
RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Output Voltages
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
ROUT
, INVALID, READY . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Short Circuit Duration
TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Thermal Resistance (Typical, Note 2) θJA (°C/W)
20 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 80
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 145
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 135
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC, SSOP, TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ICL32XXEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ICL32XXEI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C
PARAMETER TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All RIN Open, FORCEON = GND, FORCEOFF = VCC 25 - 1.0 10 µA
Supply Current, Powerdown FORCEOFF = GND 25 - 1.0 10 µA
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded, FORCEON = FORCEOFF = VCC 25 - 0.3 1.0 mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low TIN, FORCEON, FORCEOFF Full - - 0.8 V
Input Logic Threshold High TIN, FORCEON,
FORCEOFF
VCC = 3.3V Full 2.0 - - V
VCC = 5.0V Full 2.4 - - V
Input Leakage Current TIN, FORCEON, FORCEOFF Full - ±0.01 ±1.0 µA
Output Leakage Current FORCEOFF = GND, ICL3245E Only Full - ±0.05 ±10 µA
Output Voltage Low IOUT = 1.6mA Full - - 0.4 V
Output Voltage High IOUT = -1.0mA Full VCC -0.6 VCC -0.1 - V
RECEIVER INPUTS
Input Voltage Range Full -25 - 25 V
Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V
VCC = 5.0V 25 0.8 1.5 - V
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
VCC = 5.0V 25 - 1.8 2.4 V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V
ICL3225E, ICL3227E, ICL3245E
7FN4900.9
February 27, 2006
Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω
Output Short-Circuit Current Full - ±35 ±60 mA
Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V,
Automatic Powerdown or FORCEOFF = GND
Full - - ±25 µA
MOUSE DRIVEABILITY
Transmitter Output Voltage
(See Figure 11)
T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with 3kΩ
to GND, T1OUT and T2OUT Loaded with 2.5mA Each
Full ±5- -V
ENHANCED AUTOMATIC POWERDOWN (FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
INVALID High
See Figure 6 Full -2.7 - 2.7 V
Receiver Input Thresholds to
INVALID Low
See Figure 6 Full -0.3 - 0.3 V
INVALID, READY Output Voltage
Low
IOUT = 1.6mA Full - - 0.4 V
INVALID, READY Output Voltage
High
IOUT = -1.0mA Full VCC-0.6 - - V
Receiver Positive or Negative
Threshold to INVALID High Delay
(tINVH)
25 - 1 - µs
Receiver Positive or Negative
Threshold to INVALID Low Delay
(tINVL)
25 - 30 - µs
Receiver or Transmitter Edge to
Transmitters Enabled Delay (tWU)
(Note 3) 25 - 100 - µs
Receiver or Transmitter Edge to
Transmitters Disabled Delay
(tAUTOPWDN)
(Note 3) Full 15 30 60 sec
TIMING CHARACTERISTICS
Maximum Data Rate RL = 3kΩ, One Transmitter
Switching
CL = 1000pF Full 250 - - kbps
VCC = 3V to 4.5V, CL = 250pF Full 1000 - - kbps
VCC = 4.5V to 5.5V,
CL= 1000pF
Full 1000 - - kbps
Receiver Propagation Delay Receiver Input to Receiver
Output, CL = 150pF
tPHL 25 - 0.15 - µs
tPLH 25 - 0.15 - µs
Receiver Output Enable Time Normal Operation (ICL3245E Only) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (ICL3245E Only) 25 - 200 - ns
Transmitter Skew tPHL - tPLH (Note 4) 25 - 25 - ns
Receiver Skew tPHL - tPLH (Note 4) 25 - 50 - ns
Transition Region Slew Rate VCC = 3.3V, RL = 3kΩ to 7kΩ, Measured From 3V to -3V or
-3V to 3V, CL = 150pF to 1000pF
25 24 - 150 V/µs
ESD PERFORMANCE
RS-232 Pins (TOUT
, RIN) Human Body Model 25 - ±15 - kV
IEC61000-4-2 Contact Discharge 25 - ±8-kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
All Other Pins Human Body Model 25 - ±3-kV
NOTES:
3. An “edge” is defined as a transition through the transmitter or receiver input thresholds.
4. Skews are measured at the receiver input switching points (1.4V).
Electrical Specifications Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1µF; Unless Otherwise Specified.
Typicals are at TA = 25°C (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C) MIN TYP MAX UNITS
ICL3225E, ICL3227E, ICL3245E
8FN4900.9
February 27, 2006
Detailed Description
These ICL32XXE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 1Mbps minimum data rate,
require only four small external 0.1µF capacitors, feature low
power consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections: The
charge pump, the transmitters, and the receivers.
Charge-Pump
Intersil’s new ICL32XXE family utilizes regulated on-chip
dual charge pumps as voltage doublers, and voltage
inverters to generate ±5.5V transmitter supplies from a VCC
supply as low as 3.0V. This allows these devices to maintain
RS-232 compliant output levels over the ±10% tolerance
range of 3.3V powered systems. The efficient on-chip power
supplies require only four small, external 0.1µF capacitors
for the voltage doubler and inverter functions at VCC = 3.3V.
See the “Capacitor Selection” section, and Table 3 for
capacitor recommendations for other operating conditions.
The charge pumps operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Transmitter outputs disable and assume a high impedance
state when the device enters the powerdown mode (see
Table 2). These outputs may be driven to ±12V when
disabled.
All devices guarantee a 1Mbps data rate for full load
conditions (3kΩ and 250pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical
conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 1.4Mbps. Transmitter skew is
extremely low on these devices, and is specified at the
receiver input trip points (1.4V), rather than the arbitrary 0V
crossing point typical of other RS-232 families.
Transmitter inputs float if left unconnected, and may cause
ICC increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32XXE devices contain standard inverting
receivers, but only the ICL3245E receivers can tristate, via
the FORCEOFF control line. Additionally, the ICL3245E
includes a noninverting (monitor) receiver (denoted by the
ROUTB label) that is always active, regardless of the state of
any control lines. Both receiver types convert RS-232
signals to CMOS output levels and accept inputs up to ±25V
while presenting the required 3kΩ to 7kΩ input impedance
(see Figure 1) even if the power is off (VCC = 0V). The
receivers’ Schmitt trigger input stage uses hysteresis to
increase noise immunity and decrease errors due to slow
input signal transitions.
The ICL3245E inverting receivers disable during forced
(manual) powerdown, but not during automatic powerdown
(see Table 2). Conversely, the monitor receiver remains
active even during manual powerdown making it extremely
useful for Ring Indicator monitoring. Standard receivers
driving powered down peripherals must be disabled to
prevent current flow through the peripheral’s protection
diodes (see Figures 2 and 3). This renders them useless for
wake up functions, but the corresponding monitor receiver
can be dedicated to this task as shown in Figure 3.
RXOUT
GND ≤ VROUT ≤ VCC
5kΩ
RXIN
-25V ≤ VRIN ≤ +25V
GND
VCC
FIGURE 1. INVERTING RECEIVER CONNECTIONS
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
OLD
VCC
POWERED
GND SHDN = GND
VCC
Rx
Tx
VCC
CURRENT
VOUT = VCC
FLOW
RS-232 CHIP
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
ICL3245E
TRANSITION
RX
TX
R2OUTB
R2OUT
T1IN
FORCEOFF = GND
VCC
VCC
TO
R2IN
T1OUT
VOUT = HI-Z
POWERED
DETECTOR
DOWN
UART
WAKE-UP
LOGIC
ICL3225E, ICL3227E, ICL3245E
9FN4900.9
February 27, 2006
Powerdown Functionality
This 3V family of RS-232 interface devices requires a
nominal supply current of 0.3mA during normal operation
(not in powerdown mode). This is considerably less than the
5mA to 11mA current required of 5V RS-232 devices. The
already low current requirement drops significantly when the
device enters powerdown mode. In powerdown, supply
current drops to 1µA, because the on-chip charge pump
turns off (V+ collapses to VCC, V- collapses to GND), and
the transmitter outputs tristate. Inverting receiver outputs
may or may not disable in powerdown; refer to Table 2 for
details. This micro-power mode makes these devices ideal
for battery powered and portable applications.
Software Controlled (Manual) Powerdown
These three devices allow the user to force the IC into the
low power, standby state, and utilize a two pin approach
where the FORCEON and FORCEOFF inputs determine the
IC’s mode. For always enabled operation, FORCEON and
FORCEOFF are both strapped high. To switch between
active and powerdown modes, under logic or software
control, only the FORCEOFF input need be driven. The
FORCEON state isn’t critical, as FORCEOFF dominates
over FORCEON. Nevertheless, if strictly manual control over
powerdown is desired, the user must strap FORCEON high
to disable the enhanced automatic powerdown circuitry.
ICL3245E inverting (standard) receiver outputs also disable
when the device is in powerdown, thereby eliminating the
possible current path through a shutdown peripheral’s input
protection diode (see Figures 2 and 3).
Connecting FORCEOFF and FORCEON together disables
the enhanced automatic powerdown feature, enabling them
to function as a manual SHUTDOWN input (see Figure 4).
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100µs.
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RCVR OR
XMTR
EDGE
WITHIN 30
SEC?
FORCEOFF
INPUT
FORCEON
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 5)
ROUTB
OUTPUTS
RS-232
LEVEL
PRESENT
AT
RECEIVER
INPUT?
INVALID
OUTPUT MODE OF OPERATION
ICL3225E, ICL3227E
NO H H Active Active N.A. No L Normal Operation (Enhanced
Auto Powerdown Disabled)
NO H H Active Active N.A. Yes H
YES H L Active Active N.A. No L Normal Operation (Enhanced
Auto Powerdown Enabled)
YES H L Active Active N.A. Yes H
NO H L High-Z Active N.A. No L Powerdown Due to Enhanced
Auto Powerdown Logic
NO H L High-Z Active N.A. Yes H
X L X High-Z Active N.A. No L Manual Powerdown
X L X High-Z Active N.A. Yes H
ICL322XE - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X NOTE 6 NOTE 6 Active Active N.A. Yes H Normal Operation
X NOTE 6 NOTE 6 High-Z Active N.A. No L Forced Auto Powerdown
ICL3245E
NO H H Active Active Active No L Normal Operation (Enhanced
Auto Powerdown Disabled)
NO H H Active Active Active Yes H
YES H L Active Active Active No L Normal Operation (Enhanced
Auto Powerdown Enabled)
YES H L Active Active Active Yes H
NO H L High-Z Active Active No L Powerdown Due to Enhanced
Auto Powerdown Logic
NO H L High-Z Active Active Yes H
X L X High-Z High-Z Active No L Manual Powerdown
X L X High-Z High-Z Active Yes H
ICL3245E - INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X NOTE 6 NOTE 6 Active Active Active Yes H Normal Operation
X NOTE 6 NOTE 6 High-Z High-Z Active No L Forced Auto Powerdown
NOTES:
5. Applies only to the ICL3245E.
6. Input is connected to INVALID Output.
ICL3225E, ICL3227E, ICL3245E
10 FN4900.9
February 27, 2006
When using both manual and enhanced automatic
powerdown (FORCEON = 0), the ICL32XXE won’t power up
from manual powerdown until both FORCEOFF and
FORCEON are driven high, or until a transition occurs on a
receiver or transmitter input. Figure 5 illustrates a circuit for
ensuring that the ICL32XXE powers up as soon as
FORCEOFF switches high. The rising edge of the Master
Powerdown signal forces the device to power up, and the
ICL32XXE returns to enhanced automatic powerdown mode
an RC time constant after this rising edge. The time constant
isn’t critical, because the ICL32XXE remains powered up for
30 seconds after the FORCEON falling edge, even if there
are no signal transitions. This gives slow-to-wake systems
(e.g., a mouse) plenty of time to start transmitting, and as
long as it starts transmitting within 30 seconds both systems
remain enabled.
INVALID Output
The INVALID output always indicates (see Table 2) whether
or not 30µs have elapsed with invalid RS-232 signals (see
Figures 6 and 8) persisting on all of the receiver inputs,
giving the user an easy way to determine when the interface
block should power down. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off
(powered down) or when the RS-232 interface cable is
disconnected. In the case of a disconnected interface cable
where all the receiver inputs are floating (but pulled to GND
by the internal receiver pull down resistors), the INVALID
logic detects the invalid levels and drives the output low. The
power management logic then uses this indicator to power
down the interface block. Reconnecting the cable restores
valid levels at the receiver inputs, INVALID switches high,
and the power management logic wakes up the interface
block. INVALID can also be used to indicate the DTR or
RING INDICATOR signal, as long as the other receiver
inputs are floating, or driven to GND (as in the case of a
powered down driver).
Enhanced Automatic Powerdown
Even greater power savings is available by using these devices
which feature an enhanced automatic powerdown function.
When the enhanced powerdown logic determines that no
transitions have occurred on any of the transmitter nor receiver
inputs for 30 seconds, the charge pump and transmitters
powerdown, thereby reducing supply current to 1µA. The
ICL32XXE automatically powers back up whenever it detects a
transition on one of these inputs. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
Enhanced automatic powerdown operates when the
FORCEON input is low, and the FORCEOFF input is high.
Tying FORCEON high disables automatic powerdown, but
manual powerdown is always available via the overriding
FORCEOFF input. Table 2 summarizes the enhanced
automatic powerdown functionality.
Figure 7 illustrates the enhanced powerdown control logic.
Note that once the ICL32XXE enters powerdown (manually
or automatically), the 30 second timer remains timed out
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
PWR
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL32XXE
MGT
LOGIC
UART
FIGURE 5. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
FORCEOFF FORCEON
POWER MASTER POWERDOWN LINE
1MΩ
0.1µF
MANAGEMENT
UNIT
ICL32XXE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
0.3V
-0.3V
-2.7V
2.7V
INVALID LEVEL - INVALID = 0
VALID RS-232 LEVEL - INVALID = 1
VALID RS-232 LEVEL - INVALID = 1
INDETERMINATE
INDETERMINATE
FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC
30s
TIMER
S
R
FORCEOFF
AUTOSHDN
FORCEON
R_IN
T_IN EDGE
DETECT
EDGE
DETECT
ICL3225E, ICL3227E, ICL3245E
11 FN4900.9
February 27, 2006
(set), keeping the ICL32XXE powered down until FORCEON
transitions high, or until a transition occurs on a receiver or
transmitter input.
The INVALID output signal switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30µs (see Figure 8), but this has no direct effect
on the state of the ICL32XXE (see the next sections for
methods of utilizing INVALID to power down the device).
INVALID switches high 1µs after detecting a valid RS-232
level on a receiver input. INVALID operates in all modes
(forced or automatic powerdown, or forced on), so it is also
useful for systems employing manual powerdown circuitry.
The time to recover from automatic powerdown mode is
typically 100µs.
Emulating Standard Automatic Powerdown
If enhanced automatic powerdown isn’t desired, the user can
implement the standard automatic powerdown feature (mimics
the function on the ICL3221E/ICL3223E/ICL3243E) by
connecting the INVALID output to the FORCEON and
FORCEOFF inputs, as shown in Figure 9. After 30µs of invalid
receiver levels, INVALID switches low and drives the
ICL32XXE into a forced powerdown condition. INVALID
switches high as soon as a receiver input senses a valid RS-
232 level, forcing the ICL32XXE to power on. See the “INVALID
DRIVING FORCEON AND FORCEOFF” section of Table 2 for
an operational summary. This operational mode is perfect for
handheld devices that communicate with another computer via
a detachable cable. Detaching the cable allows the internal
receiver pull-down resistors to pull the inputs to GND (an invalid
RS-232 level), causing the 30µs timer to time-out and drive the
IC into powerdown. Reconnecting the cable restores valid
levels, causing the IC to power back up.
Hybrid Automatic Powerdown Options
For devices which communicate only through a detachable
cable, connecting INVALID to FORCEOFF (with FORCEON
= 0) may be a desirable configuration. While the cable is
attached INVALID and FORCEOFF remain high, so the
enhanced automatic powerdown logic powers down the RS-
232 device whenever there is 30 seconds of inactivity on the
receiver and transmitter inputs. Detaching the cable allows
the receiver inputs to drop to an invalid level (GND), so
INVALID switches low and forces the RS-232 device to
power down. The ICL32XXE remains powered down until
the cable is reconnected (INVALID = FORCEOFF = 1) and a
transition occurs on a receiver or transmitter input (see
Figure 7). For immediate power up when the cable is
reattached, connect FORCEON to FORCEOFF through a
network similar to that shown in Figure 5.
FIGURE 8. CONNECTIONS FOR AUTOMATIC POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL32XXE
UART
RECEIVER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
V+
VCC
0
V-
tINVL
tINVH
FIGURE 9. ENHANCED AUTOMATIC POWERDOWN, INVALID AND READY TIMING DIAGRAMS
READY
OUTPUT
TRANSMITTER
INPUTS
tWU
tAUTOPWDN
tAUTOPWDN tWU
INVALID
REGION
}
ICL3225E, ICL3227E, ICL3245E
12 FN4900.9
February 27, 2006
Ready Output (ICL3225E and ICL3227E Only)
The Ready output indicates that the ICL322XE is ready to
transmit. Ready switches low whenever the device enters
powerdown, and switches back high during power-up when
V- reaches -4V or lower.
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C2, C3, and C4 can be
increased without increasing C1’s value, however, do not
increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor’s equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a
capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
Operation Down to 2.7V
ICL32XXE transmitter outputs meet RS-562 levels (±3.7V),
at full data rate, with VCC as low as 2.7V. RS-562 levels
typically ensure inter operability with RS-232 devices.
Transmitter Outputs when Exiting
Powerdown
Figure 10 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3kΩ in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
Mouse Driveability
The ICL3245E is specifically designed to power a serial mouse
while operating from low voltage supplies. Figure 11 shows the
transmitter output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will supply
at least ±5V during worst case conditions (15mA for paralleled
V+ transmitters, 7.3mA for single V- transmitter).
High Data Rates
The ICL32XXE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates. Figure
12 details a transmitter loopback test circuit, and Figure 13
illustrates the loopback test result at 250kbps. For this test,
all transmitters were simultaneously driving RS-232 loads in
parallel with 1000pF, at 250kbps. Figure 14 shows the
loopback results for a single transmitter driving 250pF and
TABLE 3. REQUIRED CAPACITOR VALUES
VCC (V) C1 (µF) C2, C3, C4 (µF)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
TIME (20µs/DIV.)
T1
T2
2V/DIV
5V/DIV
VCC = +3.3V
FORCEOFF
FIGURE 10. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
C1 - C4 = 0.1µF
5V/DIV READY
FIGURE 11. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL VOUT+ CURRENT)
TRANSMITTER OUTPUT VOLTAGE (V)
LOAD CURRENT PER TRANSMITTER (mA)
0246810
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
13579
VOUT+
VOUT -
VCC
VOUT+
VOUT -
T1
T2
T3
VCC = 3.0V
ICL3245E
ICL3225E, ICL3227E, ICL3245E
13 FN4900.9
February 27, 2006
an RS-232 load at 1Mbps. The static transmitters were also
loaded with an RS-232 receiver.
Interconnection with 3V and 5V Logic
The ICL32XXE directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the ICL32XX at 3.3V, and
the logic supply at 5V, AC, HC, and CD4000 outputs can
drive ICL32XX inputs, but ICL32XX outputs do not reach the
minimum VIH for these logic families. See Table 4 for more
information.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to ±15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don’t interfere with RS-232 signals as large as ±25V.
FIGURE 12. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 13. LOOPBACK TEST AT 250kbps (CL = 1000pF)
ICL32XXE
VCC
C1
C2C4
C3
+
+
+
+
CL
V+
V-
5k
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC 0.1µF
VCC
FORCEOFF
FORCEON
T1IN
T1OUT
R1OUT
2µs/DIV.
VCC = +3.3V
5V/DIV.
C1 - C4 = 0.1µF
FIGURE 14. LOOPBACK TEST AT 1Mbps (CL = 250pF)
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
VCC
SUPPLY
VOLTAGE
(V) COMPATIBILITY
3.3 3.3 Compatible with all CMOS
families.
5 5 Compatible with all TTL and
CMOS logic families.
5 3.3 Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
T1IN
T1OUT
R1OUT
0.5µs/DIV.
5V/DIV.
VCC = +3.3V
C1 - C4 = 0.1µF
ICL3225E, ICL3227E, ICL3245E
14 FN4900.9
February 27, 2006
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5kΩ current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to ±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device’s RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
Typical Performance Curves VCC = 3.3V, TA = 25°C
FIGURE 15. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 16. SLEW RATE vs LOAD CAPACITANCE
-6
-4
-2
0
2
4
6
1000 2000 3000 4000 50000
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
1 TRANSMITTER AT 1Mbps
VOUT+
VOUT-
OTHER TRANSMITTERS AT 30kbps
LOAD CAPACITANCE (pF)
SLEW RATE (V/µs)
0 1000 2000 3000 4000 5000
0
10
30
50
110
-SLEW
+SLEW
70
90
ICL3225E, ICL3227E, ICL3245E
15 FN4900.9
February 27, 2006
Die Characteristics
MSUBSTRATE POTENTIAL (POWERED UP)
GND
TRANSISTOR COUNT
ICL3225E: 937
ICL3227E: 825
ICL3245E: 1109
PROCESS
Si Gate CMOS
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 18. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 19. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 20. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves VCC = 3.3V, TA = 25°C (Continued)
01000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
10
20
30
40
50
80
60
70
90
250kbps
120kbps
ICL3225E
1Mbps
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
10
20
30
40
50
80
60
70
90
ICL3227E
250kbps
120kbps
1Mbps
10
20
30
40
50
80
60
70
0 1000 2000 3000 4000 5000
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
120kbps
1Mbps
250kbps
90
ICL3245E
SUPPLY CURRENT (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5 NO LOAD
ALL OUTPUTS STATIC
ICL3225E, ICL3227E, ICL3245E
16 FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 -0.39 -4
A2 0.115 0.195 2.93 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C0.008 0.014 0.204 0.355 -
D0.980 1.060 24.89 26.9 5
D1 0.005 -0.13 -5
E0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L0.115 0.150 2.93 3.81 4
N20 209
Rev. 0 12/93
17 FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M16.209 (JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α0° 8° 0° 8° -
Rev. 3 6/05
18 FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
α
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) B
MM
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B0.010’ 0.015 0.25 0.38 9
C0.004 0.008 0.09 0.20’
D0.278 0.289 7.07 7.33 3
E0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H0.301 0.311 7.65 7.90’
L0.025 0.037 0.63 0.95 6
N20 207
α0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02
19 FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Small Outline Plastic Packages (SOIC)
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
20
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4900.9
February 27, 2006
ICL3225E, ICL3227E, ICL3245E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M28.209 (JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α0° 8° 0° 8° -
Rev. 2 6/05
