Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics DS182 (v1.6) July 25, 2012 Preliminary Product Specification Introduction KintexTM-7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. When operated at VCCINT = 1.0V, the speed specification of a -2L device is the same as the -2 speed grade. When operated at VCCINT = 0.9V, the -2L performance and static and dynamic power is reduced. Kintex-7 FPGA DC and AC characteristics are specified in commercial, extended, and industrial temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Kintex-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7. All specifications are subject to change without notice. DC Characteristics Table 1: Absolute Maximum Ratings (1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage -0.5 1.1 V VCCAUX Auxiliary supply voltage -0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories -0.5 1.1 V Output drivers supply voltage for 3.3V HR I/O banks -0.5 3.6 V Output drivers supply voltage for 1.8V HP I/O banks -0.5 2.0 V VCCAUX_IO Auxiliary supply voltage -0.5 2.06 V VREF Input reference voltage -0.5 2.0 V I/O input voltage -0.5 VCCO + 0.5 V I/O input voltage for VREF and differential I/O standards. -0.5 2.625 V Key memory battery backup supply -0.5 2.0 V VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits -0.5 1.1 V VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits -0.5 1.32 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers -0.5 1.935 V VMGTREFCLK GTX transceiver reference clock absolute input voltage -0.5 1.32 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX transceiver column -0.5 1.32 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage -0.5 1.26 V VCCO VIN(2)(3)(4) VCCBATT GTX Transceiver (c) 2011-2012 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 1 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings (1) (Cont'd) Symbol Description Min Max Units IDCIN DC input current for receiver input pins DC coupled MGTAVTT = 1.2V - 14 mA IDCOUT DC output current for transmitter pins DC coupled MGTAVTT = 1.2V - 14 mA XADC VCCADC XADC supply relative to GNDADC -0.5 2.0 V VREFP XADC reference input relative to GNDADC -0.5 2.0 V -65 150 C - +220 C - +260 C - +125 C Temperature TSTG TSOL Storage temperature (ambient) Maximum soldering temperature for Pb/Sn component bodies (6) Maximum soldering temperature for Pb-free component bodies (6) Maximum junction temperature(6) Tj Notes: 1. 2. 3. 4. 5. 6. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. The lower absolute voltage specification always applies. For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide. The maximum limit applied to DC and AC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. For soldering guidelines and thermal considerations, see UG475: 7 Series FPGA Packaging and Pinout Specification. Table 2: Recommended Operating Conditions (1) Symbol Description Min Typ Max Units Internal supply voltage 0.97 1.00 1.03 V For -2L (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V VCCBRAM Block RAM supply voltage 0.97 1.00 1.03 V Supply voltage for 3.3V HR I/O banks 1.14 - 3.465 V Supply voltage for 1.8V HP I/O banks 1.14 - 1.89 V Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V I/O input voltage -0.20 - VCCO + 0.2 V I/O input voltage for VREF and differential I/O standards -0.20 - 2.625 V - - 10 mA FPGA Logic VCCINT VCCO(2)(3) VCCAUX_IO VIN(4) IIN(5) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. VCCBATT(6) Battery voltage 1.0 - 1.89 V Analog supply voltage for the GTX transceiver QPLL frequency range 10.3125 GHz(8)(9) 0.97 1.0 1.08 V Analog supply voltage for the GTX transceiver QPLL frequency range > 10.3125 GHz 1.02 1.05 1.08 V VMGTAVTT(7) Analog supply voltage for the GTX transmitter and receiver termination circuits 1.17 1.2 1.23 V VMGTVCCAUX(7) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V GTX Transceiver VMGTAVCC(7) DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 2 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 2: Recommended Operating Conditions (1) (Cont'd) Symbol Description Min Typ Max Units Analog supply voltage for the resistor calibration circuit of the GTX transceiver column 1.17 1.2 1.23 V VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V VREFP Externally supplied reference voltage 1.20 1.25 1.30 V Junction temperature operating range for commercial (C) temperature devices 0 - 85 C Junction temperature operating range for extended (E) temperature devices 0 - 100 C -40 - 100 C VMGTAVTTRCAL(7) XADC Temperature Tj Junction temperature operating range for industrial (I) temperature devices Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. All voltages are relative to ground. Configuration data is retained even if VCCO drops to 0V. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The lower absolute voltage specification always applies. A total of 200 mA per bank should not be exceeded. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. Each voltage listed requires the filter circuit described in UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide. For data rates 10.3125 Gb/s, VMGTAVCC should be 1.0V 3% for lower power consumption. For lower power consumption, VMGTAVCC should be 1.0V 3% over the entire CPLL frequency range. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 - - V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 - - V IREF VREF leakage current per pin - - 15 A IL Input or output leakage current per pin (sample-tested) - - 15 A CIN(2) Die input capacitance at the pad - - 8 pF Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 90 - 330 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 68 - 250 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 34 - 220 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 23 - 150 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 12 - 120 A Pad pull-down (when selected) @ VIN = 3.3V 68 - 330 A Pad pull-down (when selected) @ VIN = 1.8V 45 - 180 A Analog supply current, analog circuits in powered up state - - 25 mA Battery supply current - - 150 nA IRPU IRPD ICCADC IBATT (3) DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 3 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 3: DC Characteristics Over Recommended Operating Conditions (Cont'd) Description Min Typ(1) Max Units Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) for commercial (C), industrial (I), and extended (E) temperature devices 28 40 55 Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) for commercial (C), industrial (I), and extended (E) temperature devices 35 50 65 Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) for commercial (C), industrial (I), and extended (E) temperature devices 44 60 83 n Temperature diode ideality factor - 1.010 - - r Temperature diode series resistance - 2 - Symbol RIN_TERM(4) Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25C. This measurement represents the die capacitance at the pad, not including the package. Maximum value specified for worst case process at 25C. Termination resistance to a VCCO/2 level. Table 4: Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks(1) AC Voltage Overshoot % of UI @-40C to 100C AC Voltage Undershoot % of UI @-40C to 100C VCCO + 0.40 100 -0.40 100 VCCO + 0.45 100 -0.45 61.7 VCCO + 0.50 100 -0.50 25.8 VCCO + 0.55 100 -0.55 11.0 VCCO + 0.60 46.6 -0.60 4.77 VCCO + 0.65 21.2 -0.65 2.10 VCCO + 0.70 9.75 -0.70 0.94 VCCO + 0.75 4.55 -0.75 0.43 VCCO + 0.80 2.15 -0.80 0.20 VCCO + 0.85 1.02 -0.85 0.09 VCCO + 0.90 0.49 -0.90 0.04 VCCO + 0.95 0.24 -0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. Table 5: Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks(1)(2) AC Voltage Overshoot % of UI @-40C to 100C AC Voltage Undershoot % of UI @-40C to 100C VCCO + 0.40 100 -0.40 100 VCCO + 0.45 100 -0.45 100 VCCO + 0.50 100 -0.50 100 VCCO + 0.55 100 -0.55 100 VCCO + 0.60 50.0 -0.60 50.0 VCCO + 0.65 50.0 -0.65 50.0 VCCO + 0.70 47.0 -0.70 50.0 VCCO + 0.75 21.2 -0.75 50.0 DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 4 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 5: Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks(1)(2) (Cont'd) AC Voltage Overshoot % of UI @-40C to 100C AC Voltage Undershoot % of UI @-40C to 100C VCCO + 0.80 9.71 -0.80 50.0 VCCO + 0.85 4.51 -0.85 28.4 VCCO + 0.90 2.12 -0.90 12.7 VCCO + 0.95 1.01 -0.95 5.79 Notes: 1. 2. A total of 200 mA per bank should not be exceeded. For UI smaller than 20 s. Table 6: Typical Quiescent Supply Current Speed Grade Symbol ICCINTQ ICCOQ ICCAUXQ Description Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current Device 0.9V Units -3 -2/-2L -1 -2L XC7K70T 241 241 241 187 mA XC7K160T 474 474 474 368 mA XC7K325T 810 810 810 629 mA XC7K355T 993 993 993 771 mA XC7K410T 1080 1080 1080 838 mA XC7K420T 1313 1313 1313 1019 mA XC7K480T 1313 1313 1313 1019 mA XC7K70T 1 1 1 1 mA XC7K160T 1 1 1 1 mA XC7K325T 1 1 1 1 mA XC7K355T 1 1 1 1 mA XC7K410T 1 1 1 1 mA XC7K420T 1 1 1 1 mA XC7K480T 1 1 1 1 mA XC7K70T 21 21 21 21 mA XC7K160T 40 40 40 40 mA XC7K325T 68 68 68 68 mA XC7K355T 75 75 75 75 mA XC7K410T 85 85 85 85 mA XC7K420T 99 99 99 99 mA XC7K480T 99 99 99 99 mA N/A N/A N/A N/A mA XC7K160T 2 2 2 2 mA XC7K325T 2 2 2 2 mA XC7K355T N/A N/A N/A N/A mA XC7K410T 2 2 2 2 mA XC7K420T N/A N/A N/A N/A mA XC7K480T N/A N/A N/A N/A mA ICCAUX_IOQ Quiescent VCCAUX_IO supply current XC7K70T DS182 (v1.6) July 25, 2012 Preliminary Product Specification 1.0V www.xilinx.com 5 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 6: Typical Quiescent Supply Current (Cont'd) Speed Grade Symbol ICCBRAMQ Description Quiescent VCCBRAM supply current Device 1.0V 0.9V Units -3 -2/-2L -1 -2L XC7K70T 6 6 6 6 mA XC7K160T 14 14 14 14 mA XC7K325T 19 19 19 19 mA XC7K355T 31 31 31 31 mA XC7K410T 34 34 34 34 mA XC7K420T 41 41 41 41 mA XC7K480T 41 41 41 41 mA Notes: 1. 2. 3. Typical values are specified at nominal voltage, 85C junction temperatures (Tj) with single-ended SelectIO resources. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. Use the XPowerTM Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for conditions other than those specified. Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the poweron sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: * The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. * The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. * When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT - VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. * When VMGTAVTT is powered before VCCINT and VMGTAVTT - VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 6 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 7 shows the minimum current, in addition to ICCQ, that are required by Kintex-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the XPower tools to estimate current drain on these supplies. Table 7: Power-On Current for Kintex-7 Devices ICCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IOMIN ICCBRAMMIN Typ(1) Typ(1) Typ(1) Typ(1) Typ(1) XC7K70T ICCINTQ + 450 ICCAUXQ + 40 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K160T ICCINTQ + 550 ICCAUXQ + 50 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K325T ICCINTQ + 600 ICCAUXQ + 80 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 40 mA XC7K355T ICCINTQ + 985 ICCAUXQ + 109 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 81 mA XC7K410T ICCINTQ + 1500 ICCAUXQ + 125 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 90 mA XC7K420T ICCINTQ + 2200 ICCAUXQ + 180 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA XC7K480T ICCINTQ + 2200 ICCAUXQ + 180 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA Device Units Notes: 1. 2. Typical values are specified at nominal voltage, 25C. Use the XPower Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents. Table 8: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM ms TJ = 0.2 50 100C(1) - 500 85C(1) - 800 TVCCO2VCCAUX Allowed time per power cycle for VCCO - VCCAUX > 2.625V TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms TJ = ms Notes: 1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 7 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 9: SelectIO DC Input and Output Levels (1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA HSTL_I -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO - 0.400 8 -8 HSTL_I_12 -0.300 VREF - 0.080 VREF + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 6.3 -6.3 HSTL_I_18 -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO - 0.400 8 -8 HSTL_II -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO - 0.400 16 -16 HSTL_II_18 -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO - 0.400 16 -16 HSUL_12 -0.300 VREF - 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 -0.1 LVCMOS12 -0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO - 0.400 Note 3 Note 3 LVCMOS15, LVDCI_15 -0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 4 Note 4 LVCMOS18, LVDCI_18 -0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO - 0.450 Note 5 Note 5 LVCMOS25 -0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO - 0.400 Note 6 Note 6 LVCMOS33 -0.300 0.800 2.000 3.450 0.400 VCCO - 0.400 Note 6 Note 6 LVTTL -0.300 0.800 2.000 3.450 0.400 2.400 Note 7 Note 7 MOBILE_DDR -0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.1 -0.1 PCI33_3 -0.500 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.5 -0.5 SSTL12 -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 - 0.150 VCCO/2 + 0.150 14.25 -14.25 SSTL135 -0.300 VREF - 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 - 0.150 VCCO/2 + 0.150 13.0 -13.0 SSTL135_R -0.300 VREF - 0.090 VREF + 0.090 VCCO + 0.300 VCCO/2 - 0.150 VCCO/2 + 0.150 8.9 -8.9 SSTL15 -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 - 0.175 VCCO/2 + 0.175 13.0 -13.0 SSTL15_R -0.300 VREF - 0.100 VREF + 0.100 VCCO + 0.300 VCCO/2 - 0.175 VCCO/2 + 0.175 8.9 -8.9 SSTL18_I -0.300 VREF - 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 - 0.470 VCCO/2 + 0.470 8 -8 SSTL18_II -0.300 VREF - 0.125 VREF + 0.125 VCCO + 0.300 VCCO/2 - 0.600 VCCO/2 + 0.600 13.4 -13.4 Notes: 1. 2. 3. 4. 5. 6. 7. 8. Tested according to relevant specifications. 3.3V and 2.5V standards are only supported in 3.3V I/O banks. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks. Supported drive strengths of 4, 8, 12, or 16 mA Supported drive strengths of 4, 8, 12, 16, or 24 mA For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 8 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 10: Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) V, Min V, Typ BLVDS_25 VID(2) V, Max VOCM(3) V, Min V, Typ V, Max VOD(4) V, Min V, Typ V, Max V, Min V, Typ V, Max Note 5 0.300 1.200 1.425 0.100 - - - 1.250 - MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600 PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400 RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600 TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO-0.405 VCCO-0.300 VCCO-0.190 0.400 0.600 0.800 Notes: 1. 2. 3. 4. 5. 6. 7. VICM is the input common mode voltage. VID is the input differential voltage (Q - Q). VOCM is the output common mode voltage. VOD is the output differential voltage (Q - Q). VOD for BLVDS will vary significantly depending on topology and loading. LVDS_25 is specified in Table 12. LVDS is specified in Table 13. Table 11: Complementary Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH V, Min V, Typ V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min DIFF_HSTL_I 0.300 0.750 1.125 0.100 - 0.400 VCCO-0.400 8.00 -8.00 DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 - 0.400 VCCO-0.400 8.00 -8.00 DIFF_HSTL_II 0.300 0.750 1.125 0.100 - 0.400 VCCO-0.400 16.00 -16.00 DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 - 0.400 VCCO-0.400 16.00 -16.00 DIFF_HSUL_12 0.300 0.600 0.850 0.100 - 20% VCCO 80% VCCO 0.100 -0.100 DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 - 10% VCCO 90% VCCO 0.100 -0.100 DIFF_SSTL12 0.300 0.600 0.850 0.100 - (VCCO/2) - 0.150 (VCCO/2) + 0.150 14.25 -14.25 DIFF_SSTL135 0.300 0.675 1.000 0.100 - (VCCO/2) - 0.150 (VCCO/2) + 0.150 13.0 -13.0 DIFF_SSTL135_R 0.300 0.675 1.000 0.100 - (VCCO/2) - 0.150 (VCCO/2) + 0.150 8.9 -8.9 DIFF_SSTL15 0.300 0.750 1.125 0.100 - (VCCO/2) - 0.175 (VCCO/2) + 0.175 13.0 -13.0 DIFF_SSTL15_R 0.300 0.750 1.125 0.100 - (VCCO/2) - 0.175 (VCCO/2) + 0.175 8.9 -8.9 DIFF_SSTL18_I 0.300 0.900 1.425 0.100 - (VCCO/2) - 0.470 (VCCO/2) + 0.470 8.00 -8.00 DIFF_SSTL18_II 0.300 0.900 1.425 0.100 - (VCCO/2) - 0.600 (VCCO/2) + 0.600 13.4 -13.4 Notes: 1. 2. 3. 4. VICM is the input common mode voltage. VID is the input differential voltage (Q - Q). VOL is the single-ended low-output voltage. VOH is the single-ended high-output voltage. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 9 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics LVDS DC Specifications (LVDS_25) The LVDS_25 standard is available in the HR I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for more information. Table 12: LVDS_25 DC Specifications Symbol DC Parameter Conditions Min Typ Max Units 2.375 2.500 2.625 V VCCO Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals - - 1.675 V VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.700 - - V VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High 100 350 600 mV VICM Input Common-Mode Voltage 0.300 1.200 1.425 V LVDS DC Specifications (LVDS) The LVDS standard is available in the HP I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for more information. Table 13: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units 1.710 1.800 1.890 V VCCO Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals - - 1.675 V VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.825 - - V VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High Common-mode input voltage = 1.25V 100 350 600 mV VICM Input Common-Mode Voltage Differential input voltage = 350 mV 0.300 1.200 1.425 V DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 10 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in ISE(R) software 14.2 v1.06 for the -3, -2, -2L(1.0V), -1, and v1.05 for -2L(0.9V) speed grades. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs. Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 14 correlates the current status of each Kintex-7 device on a per speed grade basis. Table 14: Kintex-7 Device Speed Grade Designations Device Speed Grade Designations Advance Preliminary XC7K70T -3 (1.0V) and -2L (0.9V) -2, -2L(1.0V), -1 XC7K160T -3 (1.0V) and -2L (0.9V) -2, -2L(1.0V), -1 XC7K325T -3 (1.0V) and -2L (0.9V) XC7K355T -3 (1.0V) and -2L (0.9V) XC7K410T -3 (1.0V) and -2L (0.9V) XC7K420T -3 (1.0V) and -2L (0.9V) -2, -2L(1.0V), -1 XC7K480T -3 (1.0V) and -2L (0.9V) -2, -2L(1.0V), -1 DS182 (v1.6) July 25, 2012 Preliminary Product Specification Production -2, -2L(1.0V), -1 -2, -2L(1.0V), -1 -2, -2L(1.0V), -1 www.xilinx.com 11 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 15 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 15: Kintex-7 Device Production Software and Speed Specification Release Speed Grade Designations Device 1.0V -3 0.9V -2/-2L -1 -2L XC7K70T XC7K160T XC7K325T ISE 14.2 v1.06 XC7K355T XC7K410T ISE 14.2 v1.06 XC7K420T XC7K480T Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Kintex-7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 11. In each table, the I/O bank type is either High Performance (HP) or High Range (HR). Table 16: Networking Applications Interface Performances I/O Bank Type Description SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) SDR LVDS receiver (SFI-4.1)(1) DDR LVDS receiver (SPI-4.2)(1) Speed Grade 1.0V 0.9V Units -3 -2/-2L -1 -2L HR 710 710 625 Mb/s HP 710 710 625 Mb/s HR 1250 1250 950 Mb/s HP 1600 1400 1250 Mb/s HR 710 710 625 Mb/s HP 710 710 625 Mb/s HR 1250 1250 950 Mb/s HP 1600 1400 1250 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 12 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 17: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FFG Packages)(1)(2) Speed Grade Memory Standard I/O Bank Type 1.0V VCCAUX_IO 0.9V -3 -2/-2L -1 -2L Units 4:1 Memory Controllers DDR3 DDR3L DDR2 RLDRAM III(3) HP 2.0V 1866 1866 1600 1333 Mb/s HP 1.8V 1600 1333 1066 1066 Mb/s HR N/A 1066 1066 800 800 Mb/s HP 2.0V 1600 1600 1333 1066 Mb/s HP 1.8V 1333 1066 800 800 Mb/s HR N/A 800 800 667 667 Mb/s HP 2.0V 800 800 800 800 Mb/s HP 1.8V 800 800 800 800 Mb/s HR N/A 800 800 800 800 Mb/s HP 2.0V 800 667 667 533 MHz HP 1.8V 550 500 450 450 MHz HR N/A N/A 2:1 Memory Controllers DDR3 DDR3L DDR2 QDR II+(4) RLDRAM II LPDDR2(3) HP 2.0V 1066 1066 800 800 Mb/s HP 1.8V 1066 1066 800 800 Mb/s HR N/A 1066 1066 800 800 Mb/s HP 2.0V 1066 1066 800 800 Mb/s HP 1.8V 1066 1066 800 800 Mb/s HR N/A 800 800 667 667 Mb/s HP 2.0V HP 1.8V 800 800 800 800 Mb/s HR N/A HP 2.0V HP 1.8V 550 500 450 450 MHz HR N/A 500 450 400 400 MHz HP 2.0V HP 1.8V 533 500 450 450 MHz HR N/A HP 2.0V 800 800 800 800 Mb/s HP 1.8V 800 800 800 800 Mb/s HR N/A 800 667 667 667 Mb/s Notes: 1. 2. 3. 4. VREF tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz). RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 13 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces (FBG Packages)(1)(2) Speed Grade Memory Standard I/O Bank Type VCCAUX_IO(3) 1.0V 0.9V -3 -2/-2L -1 -2L Units 4:1 Memory Controllers DDR3 DDR3L DDR2 RLDRAM III(4) HP N/A 1333 1066 800 800 Mb/s HR N/A 1066 800 800 800 Mb/s HP N/A 1066 800 667 667 Mb/s HR N/A 800 800 667 667 Mb/s HP N/A 800 800 800 800 Mb/s HR N/A 800 667 667 667 Mb/s HP N/A 550 500 450 450 MHz HR N/A N/A 2:1 Memory Controllers DDR3 DDR3L DDR2 QDR II+(5) RLDRAM II LPDDR2(4) HP N/A 1066 1066 800 800 Mb/s HR N/A 1066 800 800 800 Mb/s HP N/A 1066 800 667 667 Mb/s HR N/A 800 800 667 667 Mb/s HP N/A 800 800 800 800 Mb/s HR N/A 800 667 667 667 Mb/s HP N/A 550 500 450 450 MHz HR N/A 450 400 350 350 MHz HP N/A HR N/A 533 500 450 450 MHz HP N/A 667 667 667 667 Mb/s HR N/A 667 667 533 533 Mb/s Notes: 1. 2. 3. 4. 5. VREF tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz). FBG packages do not have separate VCCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks. RLDRAM III (BL = 4, BL = 8) and LPDDR2 specifications have not been validated with memory IP. The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 14 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics IOB Pad Input/Output/3-State Table 19 (3.3V high-range IOB (HR)) and Table 20 (1.8V high-performance IOB (HP)) summarizes the values of standardspecific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. * TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. * TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. * TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. Table 19: 3.3V IOB High Range (HR) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L LVTTL_S4 1.31 1.42 1.64 1.49 5.27 5.63 6.05 6.52 6.03 6.49 7.04 7.75 ns LVTTL_S8 1.31 1.42 1.64 1.49 4.45 4.83 5.30 5.78 5.21 5.69 6.29 7.01 ns LVTTL_S12 1.31 1.42 1.64 1.49 4.45 4.83 5.29 5.78 5.21 5.69 6.28 7.01 ns LVTTL_S16 1.31 1.42 1.64 1.49 3.47 3.88 4.40 4.85 4.23 4.74 5.39 6.08 ns LVTTL_S24 1.31 1.42 1.64 1.49 3.58 3.99 4.51 4.94 4.34 4.85 5.50 6.18 ns LVTTL_F4 1.31 1.42 1.64 1.49 4.70 4.98 5.29 5.88 5.46 5.84 6.28 7.12 ns LVTTL_F8 1.31 1.42 1.64 1.49 3.66 4.06 4.56 4.99 4.42 4.92 5.55 6.22 ns LVTTL_F12 1.31 1.42 1.64 1.49 3.66 4.06 4.56 4.97 4.42 4.92 5.55 6.21 ns LVTTL_F16 1.31 1.42 1.64 1.49 2.57 2.85 3.15 3.76 3.33 3.71 4.14 5.00 ns LVTTL_F24 1.31 1.42 1.64 1.49 2.41 2.64 2.89 3.55 3.17 3.50 3.88 4.79 ns LVDS_25(1) 0.64 0.68 0.80 0.70 1.36 1.47 1.55 2.16 2.12 2.33 2.54 3.40 ns MINI_LVDS_25 0.68 0.70 0.79 0.69 1.36 1.47 1.55 2.16 2.12 2.33 2.54 3.40 ns 0.65 0.69 0.80 0.71 1.83 2.02 2.20 2.74 2.59 2.88 3.19 3.97 ns BLVDS_25(1) RSDS_25 (point to point)(1) 0.63 0.68 0.79 0.70 1.36 1.48 1.55 2.16 2.12 2.34 2.54 3.40 ns PPDS_25(1) 0.65 0.69 0.80 0.72 1.36 1.49 1.58 2.22 2.12 2.35 2.57 3.46 ns TMDS_33(1) 0.72 0.76 0.86 0.78 1.43 1.54 1.60 2.22 2.19 2.40 2.59 3.46 ns PCI33_3(1) 1.28 1.41 1.65 1.48 2.71 3.08 3.52 3.64 3.47 3.94 4.51 4.88 ns HSUL_12 0.63 0.64 0.71 0.63 2.06 2.31 2.59 3.07 2.82 3.17 3.58 4.31 ns DIFF_HSUL_12 0.58 0.61 0.70 0.63 1.83 2.04 2.26 2.77 2.59 2.90 3.25 4.01 ns HSTL_I_S 0.61 0.64 0.73 0.64 1.55 1.69 1.80 2.40 2.31 2.55 2.79 3.64 ns HSTL_II_S 0.61 0.64 0.73 0.64 1.21 1.34 1.43 2.06 1.97 2.20 2.42 3.29 ns HSTL_I_18_S 0.64 0.67 0.76 0.66 1.28 1.39 1.45 2.14 2.04 2.25 2.44 3.37 ns HSTL_II_18_S 0.64 0.67 0.76 0.66 1.18 1.31 1.40 2.06 1.94 2.17 2.39 3.29 ns DIFF_HSTL_I_S 0.63 0.67 0.77 0.69 1.42 1.54 1.61 2.24 2.18 2.40 2.60 3.48 ns DIFF_HSTL_II_S 0.63 0.67 0.77 0.69 1.15 1.24 1.27 2.13 1.91 2.10 2.26 3.37 ns DIFF_HSTL_I_18_S 0.65 0.69 0.78 0.70 1.27 1.38 1.43 2.07 2.03 2.24 2.42 3.31 ns DIFF_HSTL_II_18_S 0.65 0.69 0.78 0.70 1.14 1.23 1.26 2.08 1.90 2.09 2.25 3.31 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 15 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 19: 3.3V IOB High Range (HR) Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L HSTL_I_F 0.61 0.64 0.73 0.64 1.10 1.19 1.23 1.94 1.86 2.05 2.22 3.18 ns HSTL_II_F 0.61 0.64 0.73 0.64 1.05 1.18 1.28 1.85 1.81 2.04 2.27 3.08 ns HSTL_I_18_F 0.64 0.67 0.76 0.66 1.05 1.18 1.28 1.92 1.81 2.04 2.27 3.16 ns HSTL_II_18_F 0.64 0.67 0.76 0.66 1.03 1.14 1.23 1.83 1.79 2.00 2.22 3.07 ns DIFF_HSTL_I_F 0.63 0.67 0.77 0.69 1.09 1.18 1.22 1.88 1.85 2.04 2.21 3.11 ns DIFF_HSTL_II_F 0.63 0.67 0.77 0.69 1.02 1.11 1.14 1.85 1.78 1.97 2.13 3.09 ns DIFF_HSTL_I_18_F 0.65 0.69 0.78 0.70 1.08 1.17 1.21 1.86 1.84 2.03 2.20 3.10 ns DIFF_HSTL_II_18_F 0.65 0.69 0.78 0.70 1.01 1.10 1.13 1.86 1.77 1.96 2.12 3.10 ns LVCMOS33_S4 1.31 1.40 1.60 1.49 5.23 5.61 6.09 6.51 5.99 6.47 7.08 7.75 ns LVCMOS33_S8 1.31 1.40 1.60 1.49 4.46 4.85 5.33 5.78 5.22 5.71 6.32 7.02 ns LVCMOS33_S12 1.31 1.40 1.60 1.49 3.46 3.89 4.42 4.84 4.22 4.75 5.41 6.07 ns LVCMOS33_S16 1.31 1.40 1.60 1.49 3.06 3.43 3.88 4.37 3.82 4.29 4.87 5.61 ns LVCMOS33_F4 1.31 1.40 1.60 1.49 4.70 5.01 5.36 5.87 5.46 5.87 6.35 7.10 ns LVCMOS33_F8 1.31 1.40 1.60 1.49 3.62 4.04 4.56 4.97 4.38 4.90 5.55 6.20 ns LVCMOS33_F12 1.31 1.40 1.60 1.49 2.57 2.85 3.15 3.76 3.33 3.71 4.14 4.99 ns LVCMOS33_F16 1.31 1.40 1.60 1.49 2.44 2.69 2.96 3.60 3.20 3.55 3.95 4.83 ns LVCMOS25_S4 1.08 1.16 1.32 1.25 4.49 4.80 5.16 5.54 5.25 5.66 6.15 6.77 ns LVCMOS25_S8 1.08 1.16 1.32 1.25 3.66 4.04 4.49 4.79 4.42 4.90 5.48 6.02 ns LVCMOS25_S12 1.08 1.16 1.32 1.25 2.77 3.10 3.49 3.86 3.53 3.96 4.48 5.10 ns LVCMOS25_S16 1.08 1.16 1.32 1.25 3.24 3.62 4.09 4.36 4.00 4.48 5.08 5.60 ns LVCMOS25_F4 1.08 1.16 1.32 1.25 3.96 4.31 4.72 5.05 4.72 5.17 5.71 6.29 ns LVCMOS25_F8 1.08 1.16 1.32 1.25 2.43 2.87 3.42 3.67 3.19 3.73 4.41 4.90 ns LVCMOS25_F12 1.08 1.16 1.32 1.25 2.23 2.63 3.13 3.41 2.99 3.49 4.12 4.65 ns LVCMOS25_F16 1.08 1.16 1.32 1.25 1.92 2.17 2.45 2.92 2.68 3.03 3.44 4.16 ns LVCMOS18_S4 0.64 0.66 0.74 0.75 3.24 3.45 3.66 4.18 4.00 4.31 4.65 5.41 ns LVCMOS18_S8 0.64 0.66 0.74 0.75 2.58 2.91 3.31 3.66 3.34 3.77 4.30 4.89 ns LVCMOS18_S12 0.64 0.66 0.74 0.75 2.58 2.91 3.31 3.66 3.34 3.77 4.30 4.89 ns LVCMOS18_S16 0.64 0.66 0.74 0.75 1.82 2.03 2.24 2.77 2.58 2.89 3.23 4.01 ns LVCMOS18_S24(1) 0.64 0.66 0.74 0.75 1.74 1.92 2.08 2.66 2.50 2.78 3.07 3.90 ns LVCMOS18_F4 0.64 0.66 0.74 0.75 3.12 3.31 3.49 4.05 3.88 4.17 4.48 5.28 ns LVCMOS18_F8 0.64 0.66 0.74 0.75 1.91 2.13 2.36 2.87 2.67 2.99 3.35 4.11 ns LVCMOS18_F12 0.64 0.66 0.74 0.75 1.91 2.13 2.36 2.87 2.67 2.99 3.35 4.11 ns LVCMOS18_F16 0.64 0.66 0.74 0.75 1.52 1.68 1.81 2.41 2.28 2.54 2.80 3.65 ns LVCMOS18_F24(1) 0.64 0.66 0.74 0.75 1.34 1.46 1.55 2.19 2.10 2.32 2.54 3.43 ns LVCMOS15_S4 0.66 0.69 0.81 0.78 3.48 3.74 4.03 4.54 4.24 4.60 5.02 5.78 ns LVCMOS15_S8 0.66 0.69 0.81 0.78 2.37 2.67 3.01 3.40 3.13 3.53 4.00 4.63 ns LVCMOS15_S12 0.66 0.69 0.81 0.78 1.83 2.03 2.23 2.78 2.59 2.89 3.22 4.02 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 16 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 19: 3.3V IOB High Range (HR) Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L LVCMOS15_S16 0.66 0.69 0.81 0.78 1.76 1.95 2.13 2.69 2.52 2.81 3.12 3.93 ns LVCMOS15_F4 0.66 0.69 0.81 0.78 3.39 3.60 3.80 4.37 4.15 4.46 4.79 5.61 ns LVCMOS15_F8 0.66 0.69 0.81 0.78 1.79 1.99 2.18 2.69 2.55 2.85 3.17 3.93 ns LVCMOS15_F12 0.66 0.69 0.81 0.78 1.40 1.54 1.65 2.27 2.16 2.40 2.64 3.51 ns LVCMOS15_F16 0.66 0.69 0.81 0.78 1.37 1.51 1.61 2.24 2.13 2.37 2.60 3.48 ns LVCMOS12_S4 0.88 0.91 1.00 0.89 3.85 4.22 4.69 4.99 4.61 5.08 5.68 6.23 ns LVCMOS12_S8 0.88 0.91 1.00 0.89 2.52 2.96 3.52 3.73 3.28 3.82 4.51 4.97 ns LVCMOS12_S12(1) 0.88 0.91 1.00 0.89 2.06 2.31 2.59 3.07 2.82 3.17 3.58 4.31 ns LVCMOS12_F4 0.88 0.91 1.00 0.89 3.44 3.73 4.06 4.49 4.20 4.59 5.05 5.72 ns LVCMOS12_F8 0.88 0.91 1.00 0.89 1.72 2.04 2.40 2.82 2.48 2.90 3.39 4.06 ns LVCMOS12_F12(1) 0.88 0.91 1.00 0.89 1.54 1.71 1.87 2.45 2.30 2.57 2.86 3.69 ns SSTL135_S 0.61 0.64 0.73 0.61 1.27 1.40 1.50 2.00 2.03 2.26 2.49 3.24 ns SSTL15_S 0.61 0.64 0.73 0.64 1.24 1.37 1.47 1.96 2.00 2.23 2.46 3.20 ns SSTL18_I_S 0.64 0.67 0.76 0.66 1.59 1.74 1.85 2.43 2.35 2.60 2.84 3.67 ns SSTL18_II_S 0.64 0.67 0.76 0.66 1.27 1.40 1.50 1.96 2.03 2.26 2.49 3.20 ns DIFF_SSTL135_S 0.59 0.61 0.73 0.63 1.27 1.40 1.50 2.00 2.03 2.26 2.49 3.24 ns DIFF_SSTL15_S 0.63 0.67 0.77 0.69 1.24 1.37 1.47 1.96 2.00 2.23 2.46 3.20 ns DIFF_SSTL18_I_S 0.65 0.69 0.78 0.70 1.50 1.63 1.72 2.33 2.26 2.49 2.71 3.57 ns DIFF_SSTL18_II_S 0.65 0.69 0.78 0.70 1.13 1.22 1.25 2.02 1.89 2.08 2.24 3.25 ns SSTL135_F 0.61 0.64 0.73 0.61 1.04 1.17 1.26 1.84 1.80 2.03 2.25 3.08 ns SSTL15_F 0.61 0.64 0.73 0.64 1.04 1.17 1.26 1.85 1.80 2.03 2.25 3.09 ns SSTL18_I_F 0.64 0.67 0.76 0.66 1.12 1.22 1.26 1.94 1.88 2.08 2.25 3.18 ns SSTL18_II_F 0.64 0.67 0.76 0.66 1.05 1.18 1.28 1.83 1.81 2.04 2.27 3.07 ns DIFF_SSTL135_F 0.59 0.61 0.73 0.63 1.04 1.17 1.26 1.84 1.80 2.03 2.25 3.08 ns DIFF_SSTL15_F 0.63 0.67 0.77 0.69 1.04 1.17 1.26 1.85 1.80 2.03 2.25 3.09 ns DIFF_SSTL18_I_F 0.65 0.69 0.78 0.70 1.10 1.19 1.23 1.89 1.86 2.05 2.22 3.12 ns DIFF_SSTL18_II_F 0.65 0.69 0.78 0.70 1.02 1.10 1.14 1.87 1.78 1.96 2.13 3.11 ns Notes: 1. This I/O standard is only available in the 3.3V high-range (HR) banks. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 17 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 20: 1.8V IOB High Performance (HP) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L LVDS 0.75 0.79 0.92 0.89 1.05 1.17 1.24 1.70 1.68 1.92 2.06 2.56 ns HSUL_12 0.69 0.72 0.82 0.92 1.65 1.84 2.05 2.43 2.29 2.59 2.87 3.29 ns DIFF_HSUL_12 0.69 0.72 0.82 0.92 1.65 1.84 2.05 2.43 2.29 2.59 2.87 3.29 ns HSTL_I_S 0.68 0.72 0.82 0.90 1.15 1.28 1.38 1.80 1.79 2.03 2.20 2.67 ns HSTL_II_S 0.68 0.72 0.82 0.90 1.05 1.17 1.26 1.71 1.69 1.93 2.08 2.57 ns HSTL_I_18_S 0.70 0.72 0.82 0.89 1.12 1.24 1.34 1.74 1.75 2.00 2.16 2.60 ns HSTL_II_18_S 0.70 0.72 0.82 0.89 1.06 1.18 1.26 1.71 1.70 1.94 2.08 2.57 ns HSTL_I_12_S 0.68 0.72 0.82 0.90 1.14 1.27 1.37 1.80 1.78 2.02 2.20 2.66 ns HSTL_I_DCI_S 0.68 0.72 0.82 0.90 1.11 1.23 1.33 1.74 1.74 1.99 2.15 2.60 ns HSTL_II_DCI_S 0.68 0.72 0.82 0.90 1.05 1.17 1.26 1.71 1.69 1.93 2.08 2.57 ns HSTL_II_T_DCI_S 0.70 0.72 0.82 0.89 1.15 1.28 1.38 1.80 1.78 2.03 2.20 2.66 ns HSTL_I_DCI_18_S 0.70 0.72 0.82 0.89 1.11 1.23 1.33 1.74 1.74 1.99 2.15 2.60 ns HSTL_II_DCI_18_S 0.70 0.72 0.82 0.89 1.05 1.16 1.24 1.71 1.69 1.92 2.06 2.57 ns HSTL_II _T_DCI_18_S 0.70 0.72 0.82 0.89 1.11 1.23 1.33 1.74 1.74 1.99 2.15 2.60 ns DIFF_HSTL_I_S 0.75 0.79 0.92 0.89 1.15 1.28 1.38 1.80 1.79 2.03 2.20 2.67 ns DIFF_HSTL_II_S 0.75 0.79 0.92 0.89 1.05 1.17 1.26 1.71 1.69 1.93 2.08 2.57 ns DIFF_HSTL_I_DCI_S 0.75 0.79 0.92 0.89 1.15 1.28 1.38 1.80 1.78 2.03 2.20 2.66 ns DIFF_HSTL_II_DCI_S 0.75 0.79 0.92 0.89 1.05 1.17 1.26 1.71 1.69 1.93 2.08 2.57 ns DIFF_HSTL_I_18_S 0.75 0.79 0.92 0.89 1.12 1.24 1.34 1.74 1.75 2.00 2.16 2.60 ns DIFF_HSTL_II_18_S 0.75 0.79 0.92 0.89 1.06 1.18 1.26 1.71 1.70 1.94 2.08 2.57 ns DIFF_HSTL_I_DCI_18_S 0.75 0.79 0.92 0.89 1.11 1.23 1.33 1.74 1.74 1.99 2.15 2.60 ns DIFF_HSTL_II_DCI_18_S 0.75 0.79 0.92 0.89 1.05 1.16 1.24 1.71 1.69 1.92 2.06 2.57 ns DIFF_HSTL_II _T_DCI_18_S 0.75 0.79 0.92 0.89 1.11 1.23 1.33 1.74 1.74 1.99 2.15 2.60 ns HSTL_I_F 0.68 0.72 0.82 0.90 1.02 1.14 1.22 1.64 1.66 1.90 2.04 2.50 ns HSTL_II_F 0.68 0.72 0.82 0.90 0.97 1.08 1.15 1.62 1.61 1.84 1.97 2.48 ns HSTL_I_18_F 0.70 0.72 0.82 0.89 1.04 1.16 1.24 1.65 1.68 1.91 2.06 2.51 ns HSTL_II_18_F 0.70 0.72 0.82 0.89 0.98 1.09 1.16 1.64 1.62 1.85 1.98 2.50 ns HSTL_I_12_F 0.68 0.72 0.82 0.90 1.02 1.13 1.21 1.63 1.65 1.88 2.03 2.49 ns HSTL_I_DCI_F 0.68 0.72 0.82 0.90 1.04 1.16 1.24 1.65 1.67 1.91 2.06 2.51 ns HSTL_II_DCI_F 0.68 0.72 0.82 0.90 0.97 1.08 1.15 1.62 1.61 1.84 1.97 2.48 ns HSTL_II_T_DCI_F 0.70 0.72 0.82 0.89 1.02 1.14 1.22 1.64 1.66 1.90 2.04 2.50 ns HSTL_I_DCI_18_F 0.70 0.72 0.82 0.89 1.04 1.16 1.24 1.65 1.67 1.91 2.06 2.51 ns HSTL_II_DCI_18_F 0.70 0.72 0.82 0.89 0.98 1.09 1.16 1.63 1.61 1.85 1.98 2.50 ns HSTL_II _T_DCI_18_F 0.70 0.72 0.82 0.89 1.04 1.16 1.24 1.65 1.67 1.91 2.06 2.51 ns DIFF_HSTL_I_F 0.75 0.79 0.92 0.89 1.02 1.14 1.22 1.64 1.66 1.90 2.04 2.50 ns DIFF_HSTL_II_F 0.75 0.79 0.92 0.89 0.97 1.08 1.15 1.62 1.61 1.84 1.97 2.48 ns DIFF_HSTL_I_DCI_F 0.75 0.79 0.92 0.89 1.02 1.14 1.22 1.64 1.66 1.90 2.04 2.50 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 18 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L DIFF_HSTL_II_DCI_F 0.75 0.79 0.92 0.89 0.97 1.08 1.15 1.62 1.61 1.84 1.97 2.48 ns DIFF_HSTL_I_18_F 0.75 0.79 0.92 0.89 1.04 1.16 1.24 1.65 1.68 1.91 2.06 2.51 ns DIFF_HSTL_II_18_F 0.75 0.79 0.92 0.89 0.98 1.09 1.16 1.64 1.62 1.85 1.98 2.50 ns DIFF_HSTL_I_DCI_18_F 0.75 0.79 0.92 0.89 1.04 1.16 1.24 1.65 1.67 1.91 2.06 2.51 ns DIFF_HSTL_II_DCI_18_F 0.75 0.79 0.92 0.89 0.98 1.09 1.16 1.63 1.61 1.85 1.98 2.50 ns DIFF_HSTL_II _T_DCI_18_F 0.75 0.79 0.92 0.89 1.04 1.16 1.24 1.65 1.67 1.91 2.06 2.51 ns LVCMOS18_S2 0.47 0.50 0.60 0.88 3.95 4.28 4.85 4.84 4.59 5.04 5.67 5.70 ns LVCMOS18_S4 0.47 0.50 0.60 0.88 2.67 2.98 3.43 3.51 3.31 3.73 4.26 4.37 ns LVCMOS18_S6 0.47 0.50 0.60 0.88 2.14 2.38 2.72 2.90 2.77 3.14 3.54 3.76 ns LVCMOS18_S8 0.47 0.50 0.60 0.88 1.98 2.21 2.52 2.74 2.61 2.97 3.35 3.60 ns LVCMOS18_S12 0.47 0.50 0.60 0.88 1.70 1.91 2.17 2.50 2.34 2.67 2.99 3.36 ns LVCMOS18_S16 0.47 0.50 0.60 0.88 1.57 1.75 1.97 2.33 2.20 2.51 2.79 3.19 ns LVCMOS18_F2 0.47 0.50 0.60 0.88 3.50 3.87 4.48 4.49 4.14 4.63 5.30 5.35 ns LVCMOS18_F4 0.47 0.50 0.60 0.88 2.23 2.50 2.87 2.97 2.87 3.25 3.69 3.83 ns LVCMOS18_F6 0.47 0.50 0.60 0.88 1.80 2.00 2.26 2.48 2.43 2.76 3.08 3.34 ns LVCMOS18_F8 0.47 0.50 0.60 0.88 1.46 1.72 2.04 2.24 2.10 2.47 2.86 3.10 ns LVCMOS18_F12 0.47 0.50 0.60 0.88 1.26 1.40 1.53 1.97 1.89 2.16 2.35 2.83 ns LVCMOS18_F16 0.47 0.50 0.60 0.88 1.19 1.33 1.44 1.90 1.83 2.08 2.26 2.76 ns LVCMOS15_S2 0.59 0.62 0.73 0.88 3.55 3.89 4.45 4.42 4.19 4.65 5.27 5.28 ns LVCMOS15_S4 0.59 0.62 0.73 0.88 2.45 2.70 3.06 3.29 3.08 3.45 3.89 4.15 ns LVCMOS15_S6 0.59 0.62 0.73 0.88 2.24 2.51 2.88 3.11 2.88 3.26 3.71 3.97 ns LVCMOS15_S8 0.59 0.62 0.73 0.88 1.91 2.16 2.49 2.75 2.55 2.91 3.31 3.61 ns LVCMOS15_S12 0.59 0.62 0.73 0.88 1.77 1.98 2.23 2.57 2.41 2.73 3.05 3.43 ns LVCMOS15_S16 0.59 0.62 0.73 0.88 1.62 1.81 2.02 2.39 2.26 2.56 2.84 3.25 ns LVCMOS15_F2 0.59 0.62 0.73 0.88 3.38 3.69 4.18 4.19 4.02 4.44 5.00 5.05 ns LVCMOS15_F4 0.59 0.62 0.73 0.88 2.04 2.21 2.44 2.78 2.68 2.97 3.26 3.64 ns LVCMOS15_F6 0.59 0.62 0.73 0.88 1.47 1.74 2.09 2.34 2.10 2.50 2.91 3.20 ns LVCMOS15_F8 0.59 0.62 0.73 0.88 1.31 1.46 1.61 2.04 1.95 2.22 2.43 2.90 ns LVCMOS15_F12 0.59 0.62 0.73 0.88 1.21 1.34 1.45 1.92 1.84 2.10 2.27 2.78 ns LVCMOS15_F16 0.59 0.62 0.73 0.88 1.18 1.31 1.41 1.89 1.82 2.07 2.23 2.75 ns LVCMOS12_S2 0.64 0.67 0.78 0.96 3.38 3.80 4.48 4.43 4.02 4.55 5.30 5.29 ns LVCMOS12_S4 0.64 0.67 0.78 0.96 2.62 2.94 3.43 3.55 3.26 3.70 4.25 4.41 ns LVCMOS12_S6 0.64 0.67 0.78 0.96 2.05 2.33 2.72 2.93 2.69 3.08 3.54 3.79 ns LVCMOS12_S8 0.64 0.67 0.78 0.96 1.94 2.18 2.51 2.78 2.58 2.94 3.33 3.64 ns LVCMOS12_F2 0.64 0.67 0.78 0.96 2.84 3.15 3.62 3.75 3.48 3.90 4.44 4.62 ns LVCMOS12_F4 0.64 0.67 0.78 0.96 1.97 2.18 2.44 2.76 2.61 2.93 3.26 3.62 ns LVCMOS12_F6 0.64 0.67 0.78 0.96 1.33 1.51 1.70 2.09 1.96 2.26 2.52 2.95 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 19 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L LVCMOS12_F8 0.64 0.67 0.78 0.96 1.27 1.42 1.55 2.00 1.91 2.18 2.37 2.86 ns LVDCI_18 0.47 0.50 0.60 0.88 1.99 2.15 2.35 2.86 2.62 2.91 3.17 3.72 ns LVDCI_15 0.59 0.62 0.73 0.88 1.98 2.23 2.58 2.95 2.62 2.99 3.40 3.81 ns LVDCI_DV2_18 0.47 0.50 0.60 0.88 1.99 2.15 2.34 2.86 2.62 2.90 3.17 3.72 ns LVDCI_DV2_15 0.59 0.62 0.73 0.88 1.98 2.23 2.58 2.96 2.62 2.99 3.40 3.82 ns HSLVDCI_18 0.68 0.72 0.82 0.90 1.99 2.15 2.35 2.86 2.62 2.91 3.17 3.72 ns HSLVDCI_15 0.68 0.72 0.82 0.90 1.98 2.23 2.58 2.95 2.62 2.99 3.40 3.81 ns SSTL18_I_S 0.68 0.72 0.82 0.90 1.02 1.15 1.24 1.79 1.66 1.90 2.07 2.65 ns SSTL18_II_S 0.68 0.72 0.82 0.90 1.17 1.29 1.37 1.84 1.81 2.05 2.19 2.70 ns SSTL18_I_DCI_S 0.68 0.72 0.82 0.90 0.92 1.06 1.17 1.73 1.56 1.82 1.99 2.59 ns SSTL18_II_DCI_S 0.68 0.72 0.82 0.90 0.88 0.98 1.08 1.71 1.51 1.74 1.90 2.57 ns SSTL18_II_T_DCI_S 0.68 0.72 0.82 0.90 0.92 1.06 1.17 1.73 1.56 1.82 1.99 2.59 ns SSTL15_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.58 1.82 1.97 2.55 ns SSTL15_DCI_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.57 1.82 1.97 2.55 ns SSTL15_T_DCI_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.57 1.82 1.97 2.55 ns SSTL135_S 0.69 0.72 0.82 0.91 0.97 1.10 1.19 1.74 1.60 1.85 2.01 2.60 ns SSTL135_DCI_S 0.69 0.72 0.82 0.91 0.97 1.09 1.19 1.74 1.60 1.85 2.01 2.60 ns SSTL135_T_DCI_S 0.69 0.72 0.82 0.91 0.97 1.09 1.19 1.74 1.60 1.85 2.01 2.60 ns SSTL12_S 0.69 0.72 0.82 0.91 0.96 1.09 1.18 1.73 1.60 1.84 2.00 2.59 ns SSTL12_DCI_S 0.69 0.72 0.82 0.91 1.03 1.17 1.27 1.73 1.66 1.92 2.09 2.59 ns SSTL12_T_DCI_S 0.69 0.72 0.82 0.91 1.03 1.17 1.27 1.73 1.66 1.92 2.09 2.59 ns DIFF_SSTL18_I_S 0.75 0.79 0.92 0.89 1.02 1.15 1.24 1.79 1.66 1.90 2.07 2.65 ns DIFF_SSTL18_II_S 0.75 0.79 0.92 0.89 1.17 1.29 1.37 1.84 1.81 2.05 2.19 2.70 ns DIFF_SSTL18_I_DCI_S 0.75 0.79 0.92 0.89 0.92 1.06 1.17 1.73 1.56 1.82 1.99 2.59 ns DIFF_SSTL18_II_DCI_S 0.75 0.79 0.92 0.89 0.88 0.98 1.08 1.71 1.51 1.74 1.90 2.57 ns DIFF_SSTL18_II_T_DCI_S 0.75 0.79 0.92 0.89 0.92 1.06 1.17 1.73 1.56 1.82 1.99 2.59 ns DIFF_SSTL15_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.58 1.82 1.97 2.55 ns DIFF_SSTL15_DCI_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.57 1.82 1.97 2.55 ns DIFF_SSTL15_T_DCI_S 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.57 1.82 1.97 2.55 ns DIFF_SSTL135_S 0.69 0.72 0.82 0.91 0.97 1.10 1.19 1.74 1.60 1.85 2.01 2.60 ns DIFF_SSTL135_DCI_S 0.69 0.72 0.82 0.91 0.97 1.09 1.19 1.74 1.60 1.85 2.01 2.60 ns DIFF_SSTL135_T_DCI_S 0.69 0.72 0.82 0.91 0.97 1.09 1.19 1.74 1.60 1.85 2.01 2.60 ns DIFF_SSTL12_S 0.69 0.72 0.82 0.91 0.96 1.09 1.18 1.73 1.60 1.84 2.00 2.59 ns DIFF_SSTL12_DCI_S 0.69 0.72 0.82 0.91 1.03 1.17 1.27 1.73 1.66 1.92 2.09 2.59 ns DIFF_SSTL12_T_DCI_S 0.69 0.72 0.82 0.91 1.03 1.17 1.27 1.73 1.66 1.92 2.09 2.59 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 20 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 20: 1.8V IOB High Performance (HP) Switching Characteristics (Cont'd) I/O Standard TIOPI TIOOP TIOTP Speed Grade Speed Grade Speed Grade 1.0V 0.9V 1.0V 0.9V 1.0V 0.9V Units -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L -3 -2/-2L -1 -2L SSTL18_I_F 0.68 0.72 0.82 0.90 0.94 1.06 1.15 1.69 1.58 1.82 1.97 2.55 ns SSTL18_II_F 0.68 0.72 0.82 0.90 0.97 1.09 1.16 1.65 1.61 1.84 1.99 2.51 ns SSTL18_I_DCI_F 0.68 0.72 0.82 0.90 0.89 1.02 1.10 1.74 1.53 1.77 1.92 2.60 ns SSTL18_II_DCI_F 0.68 0.72 0.82 0.90 0.89 1.02 1.10 1.67 1.53 1.77 1.92 2.53 ns SSTL18_II_T_DCI_F 0.68 0.72 0.82 0.90 0.89 1.02 1.10 1.74 1.53 1.77 1.92 2.60 ns SSTL15_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns SSTL15_DCI_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns SSTL15_T_DCI_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns SSTL135_F 0.69 0.72 0.82 0.91 0.88 1.00 1.08 1.65 1.52 1.76 1.90 2.51 ns SSTL135_DCI_F 0.69 0.72 0.82 0.91 0.89 1.00 1.08 1.64 1.52 1.76 1.90 2.50 ns SSTL135_T_DCI_F 0.69 0.72 0.82 0.91 0.89 1.00 1.08 1.64 1.52 1.76 1.90 2.50 ns SSTL12_F 0.69 0.72 0.82 0.91 0.88 1.00 1.08 1.63 1.52 1.76 1.90 2.50 ns SSTL12_DCI_F 0.69 0.72 0.82 0.91 0.91 1.03 1.11 1.69 1.54 1.79 1.93 2.55 ns SSTL12_T_DCI_F 0.69 0.72 0.82 0.91 0.91 1.03 1.11 1.69 1.54 1.79 1.93 2.55 ns DIFF_SSTL18_I_F 0.75 0.79 0.92 0.89 0.94 1.06 1.15 1.69 1.58 1.82 1.97 2.55 ns DIFF_SSTL18_II_F 0.75 0.79 0.92 0.89 0.97 1.09 1.16 1.65 1.61 1.84 1.99 2.51 ns DIFF_SSTL18_I_DCI_F 0.75 0.79 0.92 0.89 0.89 1.02 1.10 1.74 1.53 1.77 1.92 2.60 ns DIFF_SSTL18_II_DCI_F 0.75 0.79 0.92 0.89 0.89 1.02 1.10 1.67 1.53 1.77 1.92 2.53 ns DIFF_SSTL18_II_T_DCI_F 0.75 0.79 0.92 0.89 0.89 1.02 1.10 1.74 1.53 1.77 1.92 2.60 ns DIFF_SSTL15_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns DIFF_SSTL15_DCI_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns DIFF_SSTL15_T_DCI_F 0.68 0.72 0.82 0.90 0.89 1.01 1.09 1.64 1.53 1.77 1.91 2.50 ns DIFF_SSTL135_F 0.69 0.72 0.82 0.91 0.88 1.00 1.08 1.65 1.52 1.76 1.90 2.51 ns DIFF_SSTL135_DCI_F 0.69 0.72 0.82 0.91 0.89 1.00 1.08 1.64 1.52 1.76 1.90 2.50 ns DIFF_SSTL135_T_DCI_F 0.69 0.72 0.82 0.91 0.89 1.00 1.08 1.64 1.52 1.76 1.90 2.50 ns DIFF_SSTL12_F 0.69 0.72 0.82 0.91 0.88 1.00 1.08 1.63 1.52 1.76 1.90 2.50 ns DIFF_SSTL12_DCI_F 0.69 0.72 0.82 0.91 0.91 1.03 1.11 1.69 1.54 1.79 1.93 2.55 ns DIFF_SSTL12_T_DCI_F 0.69 0.72 0.82 0.91 0.91 1.03 1.11 1.69 1.54 1.79 1.93 2.55 ns Notes: 1. This I/O standard is only available in the 1.8V high-performance (HP) banks. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 21 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 21 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. Table 21: IOB 3-state Output Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units TIOTPHZ T input to pad high-impedance 0.76 0.86 0.99 1.24 ns TIOIBUFDISABLE_HR IBUF turn-on time from IBUFDISABLE to O output for HR I/O banks 1.72 1.89 2.14 2.17 ns TIOIBUFDISABLE_HP IBUF turn-on time from IBUFDISABLE to O output for HP I/O banks 1.31 1.46 1.76 1.86 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 22 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 22: ILOGIC Switching Characteristics Speed Grade Symbol Description 1.0V -3 -2/-2L 0.9V -1 Units -2L Setup/Hold TICE1CK/TICKCE1 CE1 pin Setup/Hold with respect to CLK 0.42/0.00 0.48/0.00 0.67/0.00 0.48/0.00 ns TISRCK/TICKSR SR pin Setup/Hold with respect to CLK 0.53/0.01 0.61/0.01 0.99/0.01 0.88/0.01 ns TIDOCKE2/TIOCKDE2 D pin Setup/Hold with respect to CLK without Delay (HP I/O banks only) 0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.41 ns TIDOCKDE2/TIOCKDDE2 DDLY pin Setup/Hold with respect to CLK (using IDELAY) 0.01/0.27 0.02/0.29 0.02/0.34 0.01/0.41 (HP I/O banks only) ns TIDOCKE3/TIOCKDE3 0.01/0.27 0.01/0.29 0.01/0.34 0.01/0.41 ns 0.01/0.27 0.02/0.29 0.02/0.34 0.01/0.41 ns D pin Setup/Hold with respect to CLK without Delay (HR I/O banks only) TIDOCKDE3/TIOCKDDE3 DDLY pin Setup/Hold with respect to CLK (using IDELAY) (HR I/O banks only) Combinatorial TIDIE2 D pin to O pin propagation delay, no Delay (HP I/O banks only) 0.09 0.10 0.12 0.14 ns TIDIDE2 DDLY pin to O pin propagation delay (using IDELAY) (HP I/O banks only) 0.10 0.11 0.13 0.15 ns TIDIE3 D pin to O pin propagation delay, no Delay (HR I/O banks only) 0.09 0.10 0.12 0.14 ns TIDIDE3 DDLY pin to O pin propagation delay (using IDELAY) (HR I/O banks only) 0.10 0.11 0.13 0.15 ns TIDLOE2 D pin to Q1 pin using flip-flop as a latch without Delay (HP I/O banks only) 0.36 0.39 0.45 0.54 ns TIDLODE2 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HP I/O banks only) 0.36 0.39 0.45 0.55 ns TIDLOE3 D pin to Q1 pin using flip-flop as a latch without Delay (HR I/O banks only) 0.36 0.39 0.45 0.54 ns TIDLODE3 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HR I/O banks only) 0.36 0.39 0.45 0.55 ns TICKQ CLK to Q outputs 0.47 0.50 0.58 0.71 ns TRQ_ILOGICE2 SR pin to OQ/TQ out (HP I/O banks only) 0.84 0.94 1.16 1.32 ns TGSRQ_ILOGICE2 Global Set/Reset to Q outputs (HP I/O banks only) 7.60 7.60 10.51 11.39 ns TRQ_ILOGICE3 SR pin to OQ/TQ out (HR I/O banks only) 0.84 0.94 1.16 1.32 ns TGSRQ_ILOGICE3 Global Set/Reset to Q outputs (HR I/O banks only) 7.60 7.60 10.51 11.39 ns TRPW_ILOGICE2 Minimum Pulse Width, SR inputs (HP I/O banks only) 0.54 0.63 0.63 0.68 ns, Min TRPW_ILOGICE3 Minimum Pulse Width, SR inputs (HR I/O banks only) 0.54 0.63 0.63 0.68 ns, Min Sequential Delays Set/Reset DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 23 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 23: OLOGIC Switching Characteristics Speed Grade Symbol Description 1.0V -3 -2/-2L 0.9V -1 Units -2L Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.59/-0.13 0.62/-0.13 0.74/-0.13 0.62/-0.13 ns TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.28/0.03 0.29/0.03 0.45/0.03 0.29/0.03 ns TOSRCK/TOCKSR SR pin Setup/Hold with respect to CLK 0.32/0.18 0.38/0.18 0.70/0.18 0.62/0.18 ns TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.60/-0.16 0.64/-0.16 0.78/-0.16 0.64/-0.16 ns TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.28/0.01 0.30/0.01 0.45/0.01 0.30/0.01 ns D1 to OQ out or T1 to TQ out 0.73 0.81 0.97 1.23 ns TOCKQ CLK to OQ/TQ out 0.41 0.43 0.49 0.63 ns TRQ_OLOGICE2 SR pin to OQ/TQ out (HP I/O banks only) 0.63 0.70 0.83 1.12 ns TGSRQ_OLOGICE2 Global Set/Reset to Q outputs (HP I/O banks only) 7.60 7.60 10.51 11.39 ns TRQ_OLOGICE3 SR pin to OQ/TQ out (HR I/O banks only) 0.63 0.70 0.83 1.12 ns TGSRQ_OLOGICE3 Global Set/Reset to Q outputs (HR I/O banks only) 7.60 7.60 10.51 11.39 ns TRPW_OLOGICE2 Minimum Pulse Width, SR inputs (HP I/O banks only) 0.54 0.54 0.63 0.68 ns, Min TRPW_OLOGICE3 Minimum Pulse Width, SR inputs (HR I/O banks only) 0.54 0.54 0.63 0.68 ns, Min Combinatorial TODQ Sequential Delays Set/Reset DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 24 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 24: ISERDES Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L 0.02/0.13 0.02/0.15 Units Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV 0.01/0.12 0.02/0.21 ns TISCCK_CE/ TISCKC_CE(2) CE pin Setup/Hold with respect to CLK (for CE1) 0.39/-0.02 0.44/-0.02 0.63/-0.02 0.44/-0.02 ns TISCCK_CE2/ TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV (for CE2) -0.12/0.29 -0.12/0.31 -0.12/0.35 -0.12/0.40 ns Setup/Hold for Data Lines TISDCK_D/TISCKD_D D pin Setup/Hold with respect to CLK -0.02/0.11 -0.02/0.12 -0.02/0.15 -0.02/0.19 ns TISDCK_DDLY/ TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using IDELAY)(1) -0.02/0.11 -0.02/0.12 -0.02/0.15 -0.02/0.19 ns TISDCK_D_DDR/ TISCKD_D_DDR D pin Setup/Hold with respect to CLK at DDR mode -0.02/0.11 -0.02/0.12 -0.02/0.15 -0.02/0.19 ns TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK at DDR mode (using IDELAY)(1) 0.11/0.11 0.12/0.12 0.15/0.15 0.19/0.19 ns CLKDIV to out at Q pin 0.46 0.47 0.58 0.67 ns D input to DO output pin 0.09 0.10 0.12 0.14 ns Sequential Delays TISCKO_Q Propagation Delays TISDO_DO Notes: 1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 25 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Output Serializer/Deserializer Switching Characteristics Table 25: OSERDES Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V Units -3 -2/-2L -1 -2L D input Setup/Hold with respect to CLKDIV 0.37/0.02 0.40/0.02 0.55/0.02 0.44/0.02 ns T input Setup/Hold with respect to CLK 0.60/-0.15 0.64/-0.15 0.77/-0.15 0.64/-0.15 ns T input Setup/Hold with respect to CLKDIV 0.27/-0.15 0.30/-0.15 0.34/-0.15 0.46/-0.15 ns TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.28/0.03 0.29/0.03 0.45/0.03 0.29/0.03 ns TOSCCK_S SR (Reset) input Setup with respect to CLKDIV 0.41 0.46 0.75 0.70 ns TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.28/0.01 0.30/0.01 0.45/0.01 0.30/0.01 ns Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSDCK_T2/TOSCKD_T2 (1) Sequential Delays TOSCKO_OQ Clock to out from CLK to OQ 0.35 0.37 0.42 0.54 ns TOSCKO_TQ Clock to out from CLK to TQ 0.41 0.43 0.49 0.63 ns T input to TQ Out 0.73 0.81 0.97 1.18 ns Combinatorial TOSDO_TTQ Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 26 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Input/Output Delay Switching Characteristics Table 26: Input/Output Delay Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units IDELAYCTRL TDLYCCO_RDY FIDELAYCTRL_REF Reset to Ready for IDELAYCTRL 3.22 3.22 3.22 3.22 s Attribute REFCLK frequency = 200.0(1) 200 200 200 200 MHz Attribute REFCLK frequency = 300.0(1) 300 300 N/A N/A MHz 10 10 10 10 MHz 52.00 52.00 52.00 52.00 ns IDELAYCTRL_REF_PRECISION REFCLK precision TIDELAYCTRL_RPW Minimum Reset pulse width IDELAY/ODELAY TIDELAYRESOLUTION IDELAY/ODELAY chain delay resolution 1/(32 x 2 x FREF) ps Pattern dependent period jitter in delay chain for clock pattern.(2) 0 0 0 0 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(3) 5 5 5 5 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(4) 9 9 9 9 ps per tap TIDELAY_CLK_MAX/ TODELAY_CLK_MAX Maximum frequency of CLK input to IDELAY/ODELAY 800 800 710 710 MHz TIDCCK_CE / TIDCKC_CE CE pin Setup/Hold with respect to C for IDELAY 0.11/0.10 0.14/0.12 0.18/0.14 0.14/0.16 ns TODCCK_CE / TODCKC_CE CE pin Setup/Hold with respect to C for ODELAY 0.14/0.03 0.16/0.04 0.19/0.05 0.28/0.06 ns TIDCCK_INC/ TIDCKC_INC INC pin Setup/Hold with respect to C for IDELAY 0.10/0.14 0.12/0.16 0.14/0.20 0.12/0.23 ns TODCCK_INC/ TODCKC_INC INC pin Setup/Hold with respect to C for ODELAY 0.10/0.07 0.12/0.08 0.13/0.09 0.19/0.16 ns TIDCCK_RST/ TIDCKC_RST RST pin Setup/Hold with respect to C for IDELAY 0.13/0.08 0.14/0.10 0.16/0.12 0.22/0.19 ns TODCCK_RST/ TODCKC_RST RST pin Setup/Hold with respect to C for ODELAY 0.16/0.04 0.19/0.06 0.24/0.08 0.32/0.11 ns TIDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 ps TODDO_ODATAIN Propagation delay through ODELAY Note 5 Note 5 Note 5 Note 5 ps TIDELAYPAT_JIT and TODELAYPAT_JIT Notes: 1. 2. 3. 4. 5. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. When HIGH_PERFORMANCE mode is set to TRUE. When HIGH_PERFORMANCE mode is set to FALSE. Delay depends on IDELAY/ODELAY tap setting. See TRACE report for actual values. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 27 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 27: IO_FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units IO_FIFO Clock to Out Delays TOFFCKO_DO RDCLK to Q outputs 0.51 0.56 0.63 0.81 ns TCKO_FLAGS Clock to IO_FIFO Flags 0.59 0.62 0.81 0.81 ns Setup/Hold TCCK_D/TCKC_D D inputs to WRCLK 0.43/-0.01 0.47/-0.01 0.53/-0.01 0.76/-0.01 ns TIFFCCK_WREN /TIFFCKC_WREN WREN to WRCLK 0.39/-0.01 0.43/-0.01 0.50/-0.01 0.70/-0.01 ns TOFFCCK_RDEN/TOFFCKC_RDEN RDEN to RDCLK 0.49/0.01 0.53/0.02 0.61/0.02 0.79/0.02 ns Minimum Pulse Width TPWH_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.29 ns TPWL_IO_FIFO RESET, RDCLK, WRCLK 0.81 0.92 1.08 1.29 ns RDCLK and WRCLK 533 470 400 333 MHz Maximum Frequency FMAX DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 28 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics CLB Switching Characteristics Table 28: CLB Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Combinatorial Delays TILO An - Dn LUT address to A 0.05 0.05 0.06 0.07 ns, Max TILO_2 An - Dn LUT address to AMUX/CMUX 0.15 0.16 0.19 0.22 ns, Max TILO_3 An - Dn LUT address to BMUX_A 0.24 0.25 0.30 0.37 ns, Max TITO An - Dn inputs to A - D Q outputs 0.58 0.61 0.74 0.91 ns, Max TAXA AX inputs to AMUX output 0.38 0.40 0.49 0.62 ns, Max TAXB AX inputs to BMUX output 0.40 0.42 0.52 0.66 ns, Max TAXC AX inputs to CMUX output 0.39 0.41 0.50 0.62 ns, Max TAXD AX inputs to DMUX output 0.43 0.44 0.52 0.67 ns, Max TBXB BX inputs to BMUX output 0.31 0.33 0.40 0.51 ns, Max TBXD BX inputs to DMUX output 0.38 0.39 0.47 0.62 ns, Max TCXC CX inputs to CMUX output 0.27 0.28 0.34 0.43 ns, Max TCXD CX inputs to DMUX output 0.33 0.34 0.41 0.54 ns, Max TDXD DX inputs to DMUX output 0.32 0.33 0.40 0.52 ns, Max TCKO Clock to AQ - DQ outputs 0.26 0.27 0.32 0.40 ns, Max TSHCKO Clock to AMUX - DMUX outputs 0.32 0.32 0.39 0.46 ns, Max Sequential Delays Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TAS/TAH AN - DN input to CLK on A - D Flip Flops 0.01/0.12 0.02/0.13 0.03/0.18 0.02/0.18 ns, Min TDICK/TCKDI AX - DX input to CLK on A - D Flip Flops 0.04/0.14 0.04/0.14 0.05/0.20 0.05/0.21 ns, Min AX - DX input through MUXs and/or carry logic to CLK on A - D Flip Flops 0.36/0.10 0.37/0.11 0.46/0.16 0.56/0.15 ns, Min TCECK_CLB/ TCKCE_CLB CE input to CLK on A - D Flip Flops 0.19/0.05 0.20/0.05 0.25/0.05 0.24/0.05 ns, Min TSRCK/TCKSR SR input to CLK on A - D Flip Flops 0.30/0.05 0.31/0.07 0.37/0.09 0.48/0.07 ns, Min Set/Reset TSRMIN SR input minimum pulse width 0.52 0.78 1.04 0.95 ns, Min TRQ Delay from SR input to AQ - DQ flip-flops 0.38 0.38 0.46 0.59 ns, Max TCEO Delay from CE input to AQ - DQ flip-flops 0.34 0.35 0.43 0.54 ns, Max FTOG Toggle frequency (for export control) 1818 1818 1818 1286 MHz DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 29 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 29: CLB Distributed RAM Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Sequential Delays TSHCKO Clock to A - B outputs 0.68 0.70 0.85 1.08 ns, Max TSHCKO_1 Clock to AMUX - BMUX outputs 0.91 0.95 1.15 1.44 ns, Max Setup and Hold Times Before/After Clock CLK TDS_LRAM/TDH_LRAM A - D inputs to CLK 0.45/0.23 0.45/0.24 0.54/0.27 0.69/0.33 ns, Min TAS_LRAM/TAH_LRAM Address An inputs to clock 0.13/0.50 0.14/0.50 0.17/0.58 0.21/0.63 ns, Min Address An inputs through MUXs and/or carry logic to clock 0.40/0.16 0.42/0.17 0.52/0.23 0.63/0.23 ns, Min TWS_LRAM/TWH_LRAM WE input to clock 0.29/0.09 0.30/0.09 0.36/0.09 0.46/0.10 ns, Min TCECK_LRAM/ TCKCE_LRAM CE input to CLK 0.29/0.09 0.30/0.09 0.37/0.09 0.47/0.10 ns, Min Clock CLK TMPW Minimum pulse width 0.68 0.77 0.91 0.82 ns, Min TMCP Minimum clock period 1.35 1.54 1.82 1.64 ns, Min Notes: 1. 2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path. CLB Shift Register Switching Characteristics (SLICEM Only) Table 30: CLB Shift Register Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Sequential Delays TREG Clock to A - D outputs 0.96 0.98 1.20 1.35 ns, Max TREG_MUX Clock to AMUX - DMUX output 1.19 1.23 1.50 1.72 ns, Max TREG_M31 Clock to DMUX output via M31 output 0.89 0.91 1.10 1.20 ns, Max Setup and Hold Times Before/After Clock CLK TWS_SHFREG/ TWH_SHFREG WE input 0.26/0.09 0.27/0.09 0.33/0.09 0.41/0.10 ns, Min TCECK_SHFREG/ TCKCE_SHFREG CE input to CLK 0.27/0.09 0.28/0.09 0.33/0.09 0.42/0.10 ns, Min TDS_SHFREG/ TDH_SHFREG A - D inputs to CLK 0.28/0.26 0.28/0.26 0.33/0.30 0.41/0.36 ns, Min Minimum pulse width 0.55 Clock CLK TMPW_SHFREG 0.65 0.78 0.70 ns, Min Notes: 1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 30 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Block RAM and FIFO Switching Characteristics Table 31: Block RAM and FIFO Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V Units -3 -2/-2L -1 -2L Clock CLK to DOUT output (without output register)(2)(3) 1.78 1.80 2.08 2.75 ns, Max Clock CLK to DOUT output (with output register)(4)(5) 0.54 0.63 0.75 0.86 ns, Max Clock CLK to DOUT output with ECC (without output register)(2)(3) 2.35 2.58 3.26 4.49 ns, Max Clock CLK to DOUT output with ECC (with output register)(4)(5) 0.62 0.69 0.80 0.94 ns, Max Clock CLK to DOUT output with Cascade (without output register)(2) 2.21 2.45 2.80 3.19 ns, Max Clock CLK to DOUT output with Cascade (with output register)(4) 0.98 1.08 1.24 1.32 ns, Max Clock CLK to FIFO flags outputs(6) 0.65 0.74 0.89 0.87 ns, Max 0.79 0.87 0.98 1.10 ns, Max Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) TRCKO_DO_ECC and TRCKO_DO_ECC_REG TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG TRCKO_FLAGS outputs(7) TRCKO_POINTERS Clock CLK to FIFO pointers TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only mode 0.66 0.72 0.80 0.93 ns, Max TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to BITERR (without output register) 2.17 2.38 3.01 4.15 ns, Max Clock CLK to BITERR (with output register) 0.57 0.65 0.76 0.89 ns, Max Clock CLK to RDADDR output with ECC (without output register) 0.64 0.74 0.90 0.98 ns, Max Clock CLK to RDADDR output with ECC (with output register) 0.71 0.79 0.92 1.10 ns, Max TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Setup and Hold Times Before/After Clock CLK TRCCK_ADDRA/TRCKC_ADDRA ADDR inputs(8) 0.38/0.27 0.42/0.28 0.48/0.31 0.65/0.31 ns, Min TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode(9) 0.49/0.51 0.55/0.53 0.63/0.57 0.78/0.56 ns, Min TRDCK_DI_RF/TRCKD_DI_RF Data input setup/hold time when block RAM is configured in READ_FIRST mode(9) 0.17/0.25 0.19/0.29 0.21/0.35 0.25/0.32 ns, Min TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode(9) 0.42/0.37 0.47/0.39 0.53/0.43 0.66/0.46 ns, Min TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only(9) 0.79/0.37 0.87/0.39 0.99/0.43 1.17/0.41 ns, Min TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode(9) 0.89/0.47 0.98/0.50 1.12/0.54 1.32/0.65 ns, Min TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC mode 0.49/0.30 0.55/0.31 0.63/0.34 0.78/0.41 ns, Min TRCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.30/0.17 0.33/0.18 0.38/0.20 0.48/0.22 ns, Min TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.21/0.13 0.25/0.13 0.31/0.14 0.28/0.13 ns, Min 0.25/0.06 0.27/0.06 0.29/0.06 0.35/0.06 ns, Min TRCCK_RSTREG/TRCKC_RSTREG Synchronous RSTREG input DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 31 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 31: Block RAM and FIFO Switching Characteristics (Cont'd) Speed Grade Symbol Description 1.0V 0.9V Units -3 -2/-2L -1 -2L TRCCK_RSTRAM/TRCKC_RSTRAM Synchronous RSTRAM input 0.27/0.35 0.29/0.37 0.31/0.39 0.38/0.34 ns, Min TRCCK_WEA/TRCKC_WEA Write Enable (WE) input (Block RAM only) 0.38/0.15 0.41/0.16 0.46/0.17 0.54/0.19 ns, Min TRCCK_WREN/TRCKC_WREN WREN FIFO inputs 0.39/0.25 0.39/0.30 0.40/0.37 0.65/0.32 ns, Min TRCCK_RDEN/TRCKC_RDEN RDEN FIFO inputs 0.36/0.26 0.36/0.30 0.37/0.37 0.60/0.32 ns, Min 0.76 0.83 0.93 1.06 ns, Max Reset Delays TRCO_FLAGS Reset RST to FIFO flags/pointers(10) TRREC_RST/TRREM_RST FIFO reset recovery and removal timing(11) 1.59/-0.68 1.76/-0.68 2.01/-0.68 1.97/-0.46 ns, Max Maximum Frequency FMAX_BRAM_WF_NC Block RAM (Write first and No change modes) When not in SDP RF mode 601 543 458 372 MHz FMAX_BRAM_RF_PERFORMANCE Block RAM (Read first, Performance mode) When in SDP RF mode but no address overlap between port A and port B 601 543 458 372 MHz FMAX_BRAM_RF_DELAYED_WRITE Block RAM (Read first, Delayed_write mode) When in SDP RF mode and there is possibility of overlap between port A and port B addresses 528 477 400 317 MHz FMAX_CAS_WF_NC Block RAM Cascade (Write first, No change mode) When cascade but not in RF mode 551 493 408 322 MHz FMAX_CAS_RF_PERFORMANCE Block RAM Cascade (Read first, Performance mode) When in cascade with RF mode and no possibility of address overlap/one port is disabled 551 493 408 322 MHz FMAX_CAS_RF_DELAYED_WRITE When in cascade RF mode and there is a possibility of address overlap between port A and port B 478 427 350 267 MHz FMAX_FIFO FIFO in all modes without ECC 601 543 458 372 MHz FMAX_ECC Block RAM and FIFO in ECC configuration 484 430 351 254 MHz Notes: 1. 2. 3. 4. 5. 6. 7. 8. TRACE will report all of these parameters as TRCKO_DO. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. These parameters also apply to synchronous FIFO with DO_REG = 0. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. These parameters include both A and B inputs as well as the parity inputs of A and B. 10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 32 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics DSP48E1 Switching Characteristics Table 32: DSP48E1 Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.24/ 0.12 0.27/ 0.14 0.31/ 0.16 0.38/ 0.14 ns TDSPDCK_B_BREG/TDSPCKD_B_BREG B input to B register CLK 0.28/ 0.13 0.32/ 0.14 0.39/ 0.15 0.51/ 0.16 ns TDSPDCK_C_CREG/TDSPCKD_C_CREG C input to C register CLK 0.15/ 0.15 0.17/ 0.17 0.20/ 0.20 0.31/ 0.21 ns TDSPDCK_D_DREG/TDSPCKD_D_DREG D input to D register CLK 0.21/ 0.19 0.27/ 0.22 0.35/ 0.26 0.46/ 0.20 ns TDSPDCK_ACIN_AREG/TDSPCKD_ACIN_AREG ACIN input to A register CLK 0.21/ 0.12 0.24/ 0.14 0.27/ 0.16 0.31/ 0.12 ns TDSPDCK_BCIN_BREG/TDSPCKD_BCIN_BREG BCIN input to B register CLK 0.22/ 0.13 0.25/ 0.14 0.30/ 0.15 0.34/ 0.16 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, B}_MREG_MULT/ TDSPCKD_B_MREG_MULT {A, B,} input to M register CLK using multiplier 2.04/ -0.01 2.34/ -0.01 2.79/ -0.01 3.66/ -0.01 ns TDSPDCK_{A, B}_ADREG/ TDSPCKD_ D_ADREG {A, D} input to AD register CLK 1.09/ -0.02 1.25/ -0.02 1.49/ -0.02 1.94/ -0.02 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT {A, B,} input to P register CLK using multiplier 3.41/ -0.24 3.90/ -0.24 4.64/ -0.24 5.89/ -0.24 ns TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK using multiplier 3.33/ -0.62 3.81/ -0.62 4.53/ -0.62 5.70/ -0.62 ns TDSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG A or B input to P register CLK not using multiplier 1.47/ -0.24 1.68/ -0.24 2.00/ -0.24 2.37/ -0.24 ns TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not using multiplier 1.30/ -0.22 1.49/ -0.22 1.78/ -0.22 2.11/ -0.22 ns TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK 1.12/ -0.13 1.28/ -0.13 1.52/ -0.13 1.81/ -0.13 ns TDSPDCK_{CEA;CEB}_{AREG;BREG}/ TDSPCKD_{CEA;CEB}_{AREG;BREG} {CEA; CEB} input to {A; B} register CLK 0.30/ 0.05 0.36/ 0.06 0.44/ 0.09 0.37/ 0.01 ns TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK 0.24/ 0.08 0.29/ 0.09 0.36/ 0.11 0.43/ 0.11 ns TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK 0.31/ -0.02 0.36/ -0.02 0.44/ -0.02 0.58/ 0.12 ns TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK 0.26/ 0.15 0.29/ 0.17 0.33/ 0.20 0.39/ 0.25 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK 0.31/ 0.01 0.36/ 0.01 0.45/ 0.01 0.54/ 0.00 ns Setup and Hold Times of the CE Pins DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 33 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 32: DSP48E1 Switching Characteristics (Cont'd) Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} {RSTA, RSTB} input to {A, B} register CLK 0.34/ 0.10 0.39/ 0.11 0.47/ 0.13 0.53/ 0.34 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.06/ 0.22 0.07/ 0.24 0.08/ 0.26 0.08/ 0.31 ns TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.37/ 0.06 0.42/ 0.06 0.50/ 0.07 0.57/ 0.07 ns TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.18/ 0.18 0.20/ 0.21 0.23/ 0.24 0.24/ 0.29 ns TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG 0.24/ 0.01 0.26/ 0.01 0.30/ 0.01 0.37/ 0.01 ns RSTP input to P register CLK Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier 3.21 3.69 4.39 5.60 ns TDSPDO_D_P_MULT D input to P output using multiplier 3.15 3.61 4.30 5.44 ns TDSPDO_A_P A input to P output not using multiplier 1.30 1.48 1.76 2.10 ns TDSPDO_C_P C input to P output 1.13 1.30 1.55 1.84 ns Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} output 0.47 0.53 0.63 0.75 ns TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to CARRYCASCOUT output using multiplier 3.44 3.94 4.69 5.96 ns TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT output using multiplier 3.36 3.85 4.58 5.77 ns TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to CARRYCASCOUT output not using multiplier 1.50 1.72 2.04 2.44 ns TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT output 1.34 1.53 1.83 2.18 ns Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier 3.09 3.55 4.24 5.42 ns TDSPDO_ACIN_P ACIN input to P output not using multiplier 1.16 1.33 1.59 2.07 ns TDSPDO_ACIN_ACOUT ACIN input to ACOUT output 0.32 0.37 0.45 0.53 ns TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT output using multiplier 3.30 3.79 4.52 5.76 ns TDSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT output not using multiplier 1.37 1.57 1.87 2.40 ns TDSPDO_PCIN_P PCIN input to P output 0.94 1.08 1.29 1.54 ns TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output 1.15 1.32 1.57 1.88 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_P_PREG CLK PREG to P output 0.33 0.35 0.39 0.45 ns TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output 0.44 0.50 0.59 0.71 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 34 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 32: DSP48E1 Switching Characteristics (Cont'd) Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_P_MREG CLK MREG to P output 1.42 1.64 1.96 2.31 ns TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT output 1.63 1.87 2.24 2.65 ns TDSPCKO_P_ADREG_MULT CLK ADREG to P output using multiplier 2.30 2.63 3.13 3.90 ns TDSPCKO_CARRYCASCOUT_ADREG_MULT CLK ADREG to CARRYCASCOUT output using multiplier 2.51 2.87 3.41 4.23 ns Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier 3.34 3.83 4.55 5.80 ns TDSPCKO_P_BREG CLK BREG to P output not using multiplier 1.39 1.59 1.88 2.24 ns TDSPCKO_P_CREG CLK CREG to P output not using multiplier 1.43 1.64 1.95 2.32 ns TDSPCKO_P_DREG_MULT CLK DREG to P output using multiplier 3.32 3.80 4.51 5.74 ns 0.55 0.62 0.74 0.87 ns TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT CLK (AREG, BREG) to CARRYCASCOUT output using multiplier 3.55 4.06 4.84 6.13 ns TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to CARRYCASCOUT output not using multiplier 1.60 1.82 2.16 2.58 ns TDSPCKO_CARRYCASCOUT_ DREG_MULT CLK DREG to CARRYCASCOUT output using multiplier 3.52 4.03 4.79 6.07 ns TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to CARRYCASCOUT output 1.64 1.88 2.23 2.65 ns FMAX With all registers used 741 650 547 429 MHz FMAX_PATDET With pattern detector 627 549 463 365 MHz FMAX_MULT_NOMREG Two register multiply without MREG 412 360 303 248 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 374 327 276 225 MHz FMAX_PREADD_MULT_NOADREG Without ADREG 468 408 342 263 MHz FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern detect 468 408 342 263 MHz FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) 306 267 225 177 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect 285 249 209 165 MHz Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} CLK (ACOUT, BCOUT) to {A,B} register output Maximum Frequency DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 35 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Clock Buffers and Networks Table 33: Global Clock Switching Characteristics (Including BUFGCTRL) Speed Grade Symbol Description 1.0V -3 TBCCCK_CE/TBCCKC_CE (1) -2/-2L 0.9V -1 Units -2L CE pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.27/0.38 ns TBCCCK_S/TBCCKC_S(1) S pins Setup/Hold 0.12/0.30 0.14/0.38 0.26/0.38 0.27/0.38 ns TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.10 0.12 0.13 ns Global clock tree (BUFG) 741 710 625 560 MHz Maximum Frequency FMAX_BUFG Notes: 1. 2. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 34: Input/Output Clock Switching Characteristics (BUFIO) Speed Grade Symbol TBIOCKO_O Description 1.0V 0.9V Units -3 -2/-2L -1 -2L Clock to out delay from I to O 1.04 1.14 1.32 1.73 ns I/O clock tree (BUFIO) 800 800 710 710 MHz 0.9V Units Maximum Frequency FMAX_BUFIO Table 35: Regional Clock Buffer Switching Characteristics (BUFR) Speed Grade Symbol Description 1.0V -3 -2/-2L -1 -2L TBRCKO_O Clock to out delay from I to O 0.60 0.65 0.77 1.23 ns TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set 0.30 0.32 0.38 0.68 ns TBRDO_O Propagation delay from CLR to O 0.71 0.75 0.96 0.96 ns Regional clock tree (BUFR) 600 540 450 450 MHz Maximum Frequency FMAX_BUFR(1) Notes: 1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 36 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 36: Horizontal Clock Buffer Switching Characteristics (BUFH) Speed Grade Symbol Description TBHCKO_O BUFH delay from I to O TBHCCK_CE/TBHCKC_CE CE pin Setup and Hold 1.0V 0.9V -3 -2/-2L -1 -2L 0.10 0.11 0.13 0.14 0.20/0.16 0.23/0.20 0.38/0.21 0.32/0.20 Units ns ns Maximum Frequency FMAX_BUFH Horizontal clock buffer (BUFH) 741 710 625 560 MHz 0.9V Units Table 37: Duty Cycle Distortion and Clock-Tree Skew Speed Grade Symbol Description TDCD_CLK Global Clock Tree Duty Cycle Distortion(1) TCKSKEW Global Clock Tree Skew(2) Device 1.0V -3 -2/-2L -1 -2L All 0.20 0.20 0.20 0.25 ns XC7K70T 0.29 0.40 0.40 0.48 ns XC7K160T 0.42 0.53 0.57 0.70 ns XC7K325T 0.59 0.74 0.79 0.95 ns XC7K355T 0.45 0.57 0.59 0.72 ns XC7K410T 0.60 0.74 0.79 0.95 ns XC7K420T 0.60 0.74 0.79 0.95 ns XC7K480T 0.60 0.74 0.79 0.95 ns TDCD_BUFIO I/O clock tree duty cycle distortion All 0.12 0.12 0.12 0.12 ns TBUFIOSKEW I/O clock tree skew across one clock region All 0.02 0.02 0.02 0.03 ns TDCD_BUFR Regional clock tree duty cycle distortion All 0.15 0.15 0.15 0.15 ns Notes: 1. 2. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 37 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics MMCM Switching Characteristics Table 38: MMCM Specification Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units MMCM_FINMAX Maximum Input Clock Frequency 1066 933 800 800 MHz MMCM_FINMIN Minimum Input Clock Frequency 10 10 10 10 MHz MMCM_FINJITTER Maximum Input Clock Period Jitter MMCM_FINDUTY Allowable Input Duty Cycle: 10--49 MHz 25 25 25 25 % Allowable Input Duty Cycle: 50--199 MHz 30 30 30 30 % Allowable Input Duty Cycle: 200--399 MHz 35 35 35 35 % Allowable Input Duty Cycle: 400--499 MHz 40 40 40 40 % Allowable Input Duty Cycle: >500 MHz 45 45 45 45 % < 20% of clock input period or 1 ns Max MMCM_FMIN_PSCLK Minimum Dynamic Phase Shift Clock Frequency 0.01 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum Dynamic Phase Shift Clock Frequency 550 500 450 450 MHz MMCM_FVCOMIN Minimum MMCM VCO Frequency 600 600 600 600 MHz MMCM_FVCOMAX Maximum MMCM VCO Frequency MMCM_FBANDWIDTH 1600 1440 1200 1200 MHz Low MMCM Bandwidth at Typical(1) 1.00 1.00 1.00 1.00 MHz High MMCM Bandwidth at Typical(1) 4.00 4.00 4.00 4.00 MHz 0.12 0.12 0.12 0.12 ns MMCM_TSTATPHAOFFSET Static Phase Offset of the MMCM MMCM_TOUTJITTER MMCM Output Outputs(2) Jitter(3) Note 1 MMCM_TOUTDUTY MMCM Output Clock Duty Cycle MMCM_TLOCKMAX MMCM_FOUTMAX Precision(4) 0.20 0.20 0.20 0.25 ns MMCM Maximum Lock Time 100 100 100 100 s MMCM Maximum Output Frequency 1066 933 800 800 MHz 4.69 4.69 4.69 4.69 MHz Frequency(5)(6) MMCM_FOUTMIN MMCM Minimum Output MMCM_TEXTFDVAR External Clock Feedback Variation MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to High or Optimized 550 500 450 450 MHz Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to Low 300 300 300 300 MHz MMCM_FPFDMIN Minimum Frequency at the Phase Frequency Detector 10 10 10 10 MHz MMCM_TFBDELAY Maximum Delay in the Feedback Path < 20% of clock input period or 1 ns Max 3 ns Max or one CLKIN cycle MMCM Switching Characteristics Setup and Hold TMMCMDCK_PSEN/ TMMCMCKD_PSEN Setup and Hold of Phase Shift Enable 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and Hold of Phase Shift Increment/Decrement 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns TMMCMCKO_PSDONE Phase Shift Clock-to-Out of PSDONE 0.59 0.68 0.81 0.78 ns Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK TMMCMDCK_DADDR/ TMMCMCKD_DADDR DADDR Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min TMMCMDCK_DI/ TMMCMCKD_DI DI Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 38 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 38: MMCM Specification (Cont'd) Speed Grade Symbol Description 1.0V -3 -2/-2L 0.9V -1 Units -2L TMMCMDCK_DEN/ TMMCMCKD_DEN DEN Setup/Hold 1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min TMMCMDCK_DWE/ TMMCMCKD_DWE DWE Setup/Hold 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min TMMCMCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.70 ns, Max FDCK DCLK frequency 200 200 200 100 MHz, Max Notes: 1. 2. 3. 4. 5. 6. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any MMCM outputs with identical phase. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. PLL Switching Characteristics Table 39: PLL Specification Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units PLL_FINMAX Maximum Input Clock Frequency 1066 933 800 800 MHz PLL_FINMIN Minimum Input Clock Frequency 19 19 19 19 MHz PLL_FINJITTER Maximum Input Clock Period Jitter PLL_FINDUTY Allowable Input Duty Cycle: 19--49 MHz 25 25 25 25 % Allowable Input Duty Cycle: 50--199 MHz 30 30 30 30 % Allowable Input Duty Cycle: 200--399 MHz 35 35 35 35 % Allowable Input Duty Cycle: 400--499 MHz 40 40 40 40 % Allowable Input Duty Cycle: >500 MHz 45 45 45 45 % PLL_FVCOMIN Minimum PLL VCO Frequency 800 800 800 800 MHz PLL_FVCOMAX Maximum PLL VCO Frequency PLL_FBANDWIDTH PLL_TSTATPHAOFFSET PLL_TOUTJITTER < 20% of clock input period or 1 ns Max 2133 1866 1600 1600 MHz Low PLL Bandwidth at Typical(1) 1.00 1.00 1.00 1.00 MHz High PLL Bandwidth at Typical(1) 4.00 4.00 4.00 4.00 MHz 0.12 0.12 0.12 0.12 ns Static Phase Offset of the PLL PLL Output Outputs(2) Jitter(3) Note 1 PLL_TOUTDUTY PLL Output Clock Duty Cycle PLL_TLOCKMAX PLL_FOUTMAX Precision(4) 0.20 0.20 0.20 0.25 ns PLL Maximum Lock Time 100 100 100 100 s PLL Maximum Output Frequency 1066 933 800 800 MHz 6.25 6.25 6.25 6.25 MHz Frequency(5) PLL_FOUTMIN PLL Minimum Output PLL_TEXTFDVAR External Clock Feedback Variation PLL_RSTMINPULSE Minimum Reset Pulse Width DS182 (v1.6) July 25, 2012 Preliminary Product Specification < 20% of clock input period or 1 ns Max 5.00 5.00 5.00 5.00 ns www.xilinx.com 39 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 39: PLL Specification (Cont'd) Speed Grade Symbol Description 1.0V 0.9V Units -3 -2/-2L -1 -2L Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to High or Optimized 550 500 450 450 MHz Maximum Frequency at the Phase Frequency Detector with Bandwidth Set to Low 300 300 300 300 MHz PLL_FPFDMIN Minimum Frequency at the Phase Frequency Detector 19 19 19 19 MHz PLL_TFBDELAY Maximum Delay in the Feedback Path PLL_FPFDMAX 3 ns Max or one CLKIN cycle Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK TPLLCCK_DADDR/ TPLLCKC_DADDR Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min TPLLCCK_DI/ TPLLCKC_DI Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min TPLLCCK_DEN/ TPLLCKC_DEN Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min TPLLCCK_DWE/ TPLLCKC_DWE Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min TPLLCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.70 ns, Max FDCK DCLK frequency 200 200 200 100 MHz, Max Notes: 1. 2. 3. 4. 5. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. The static offset is measured between any PLL outputs with identical phase. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. Includes global clock buffer. Calculated as FVCO/128 assuming output duty cycle is 50%. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 40 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Device Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region) Speed Grade Symbol Description Device 1.0V -3 -2/-2L 0.9V -1 Units -2L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF without MMCM/PLL (near clock region) XC7K70T 4.98 5.49 6.17 7.94 ns XC7K160T 5.23 5.77 6.48 8.31 ns XC7K325T 5.72 6.31 7.09 9.05 ns XC7K355T 5.34 5.87 6.57 8.27 ns XC7K410T 5.84 6.44 7.22 9.21 ns XC7K420T 5.48 6.04 6.77 8.51 ns XC7K480T 5.50 6.04 6.77 8.51 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Table 41: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region) Speed Grade Symbol Description Device 1.0V -3 -2/-2L 0.9V -1 Units -2L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF without MMCM/PLL (far clock region) XC7K70T 5.29 5.83 6.55 8.41 ns XC7K160T 5.84 6.45 7.24 9.25 ns XC7K325T 6.33 6.99 7.84 9.99 ns XC7K355T 5.95 6.55 7.32 9.20 ns XC7K410T 6.45 7.12 7.97 10.14 ns XC7K420T 6.40 7.06 7.90 9.90 ns XC7K480T 6.41 7.06 7.90 9.91 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 41 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 42: Clock-Capable Clock Input to Output Delay With MMCM Speed Grade Symbol Description Device 1.0V -3 0.9V -2/-2L -1 -2L Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XC7K70T 0.95 0.95 0.95 2.09 ns XC7K160T 0.96 0.96 0.96 2.13 ns XC7K325T 1.00 1.00 1.00 2.13 ns XC7K355T 1.00 1.00 1.00 1.88 ns XC7K410T 1.00 1.00 1.00 2.15 ns XC7K420T 1.00 1.00 1.00 1.95 ns XC7K480T 1.07 1.07 1.07 1.95 ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation. Table 43: Clock-Capable Clock Input to Output Delay With PLL Speed Grade Symbol Description Device 1.0V -3 0.9V -2/-2L -1 -2L Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL XC7K70T 0.84 0.84 0.84 1.69 ns XC7K160T 0.89 0.89 0.89 1.76 ns XC7K325T 0.89 0.89 0.89 1.74 ns XC7K355T 0.89 0.89 0.89 1.49 ns XC7K410T 0.89 0.89 0.89 1.76 ns XC7K420T 0.89 0.89 0.89 1.55 ns XC7K480T 0.96 0.96 0.96 1.55 ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. PLL output jitter is already included in the timing calculation. Table 44: Pin-to-Pin, Clock-to-Out using BUFIO Speed Grade Symbol Description 1.0V -3 -2/-2L 0.9V -1 -2L Units SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. TICKOFCS Clock-to-Out of I/O clock for HR I/O banks 4.93 5.52 6.20 7.70 ns Clock-to-Out of I/O clock for HP I/O banks 4.85 5.44 6.11 7.75 ns DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 42 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 45: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Speed Grade Symbol Description Device 1.0V -3 Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock Input and IFF(2) without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks -2/-2L 0.9V -1 Units -2L Standard.(1) XC7K70T 2.83/-0.29 2.95/-0.29 3.15/-0.29 4.70/-0.79 ns XC7K160T 3.17/-0.35 3.29/-0.35 3.55/-0.35 5.43/-0.97 ns XC7K325T 2.83/-0.06 2.94/-0.06 3.15/-0.06 4.98/-0.68 ns XC7K355T 3.26/-0.32 3.41/-0.32 3.67/-0.32 5.65/-1.02 ns XC7K410T 3.43/-0.34 3.59/-0.34 3.88/-0.34 6.06/-1.09 ns XC7K420T 3.45/-0.35 3.61/-0.35 3.90/-0.35 6.08/-1.11 ns XC7K480T 3.37/-0.27 3.48/-0.27 3.76/-0.27 5.86/-1.10 ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Table 46: Clock-Capable Clock Input Setup and Hold With MMCM Speed Grade Symbol Description Device 1.0V -3 Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 TPSMMCMCC/ TPHMMCMCC No Delay clock-capable clock input and IFF(2) with MMCM -2/-2L 0.9V -1 Units -2L Standard.(1) XC7K70T 2.39/-0.22 2.65/-0.22 2.94/-0.22 2.65/-0.62 ns XC7K160T 2.49/-0.20 2.77/-0.20 3.07/-0.20 2.79/-0.58 ns XC7K325T 2.55/-0.16 2.85/-0.16 3.14/-0.16 2.72/-0.58 ns XC7K355T 2.43/-0.16 2.73/-0.16 3.00/-0.16 2.54/-0.69 ns XC7K410T 2.55/-0.16 2.84/-0.16 3.14/-0.16 2.76/-0.56 ns XC7K420T 2.55/-0.16 2.86/-0.16 3.15/-0.16 2.70/-0.75 ns XC7K480T 2.47/-0.09 2.73/-0.09 3.02/-0.09 2.48/-0.75 ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 43 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 47: Clock-Capable Clock Input Setup and Hold With PLL Speed Grade Symbol Description Device 1.0V -3 Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 TPSPLLCC/ TPHPLLCC No Delay clock-capable clock input and IFF(2) with PLL 0.9V -2/-2L -1 Units -2L Standard.(1) XC7K70T 2.75/-0.32 3.04/-0.32 3.33/-0.32 3.06/-0.71 ns XC7K160T 2.85/-0.31 3.16/-0.31 3.46/-0.31 3.20/-0.78 ns XC7K325T 2.91/-0.27 3.24/-0.27 3.54/-0.27 3.13/-0.78 ns XC7K355T 2.79/-0.27 3.12/-0.27 3.40/-0.27 2.95/-0.78 ns XC7K410T 2.91/-0.27 3.24/-0.27 3.53/-0.27 3.16/-0.77 ns XC7K420T 2.91/-0.27 3.25/-0.27 3.55/-0.27 3.11/-0.84 ns XC7K480T 2.83/-0.20 3.12/-0.20 3.41/-0.20 2.89/-0.84 ns Notes: 1. 2. 3. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. IFF = Input Flip-Flop or Latch Use IBIS to determine any duty-cycle distortion incurred using various standards. Table 48: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO Speed Grade Symbol Description 1.0V -3 0.9V -2/-2L -1 -2L Units Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. TPSCS/TPHCS Setup/Hold of I/O clock for HR I/O banks -0.36/1.36 -0.36/1.50 -0.36/1.70 -0.46/2.01 ns Setup/Hold of I/O clock for HP I/O banks -0.34/1.39 -0.34/1.53 -0.34/1.73 -0.47/1.99 ns Table 49: Sample Window Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units TSAMP Sampling Error at Receiver Pins(1) 0.51 0.56 0.61 0.56 ns TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) 0.30 0.35 0.40 0.35 ns Notes: 1. 2. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 44 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock transmitter and receiver data-valid windows. Table 50: Package Skew Symbol TPKGSKEW Description Package Skew(1) Device XC7K70T XC7K160T XC7K325T Package ps FBG676 ps FBG484 118 ps FBG676 136 ps FFG676 161 ps FBG676 146 ps FFG676 154 ps FBG900 163 ps FFG900 161 FFG901 XC7K410T FBG676 XC7K480T Units FBG484 XC7K355T XC7K420T Value ps ps 165 ps FFG676 168 ps FBG900 151 ps FFG900 146 ps FFG901 149 ps FFG1156 145 ps FFG901 149 ps FFG1156 145 ps Notes: 1. 2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time from Pad to Ball (7.0 ps per mm). Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 45 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics GTX Transceiver Specifications GTX Transceiver DC Input and Output Levels Table 51 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide for further details. Table 51: GTX Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units - - 1000 mV DVPPOUT Differential peak-to-peak output Transmitter output swing is set to voltage (1) maximum setting VCMOUTDC DC common mode output voltage. ROUT Differential output resistance - 100 - TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew - 2 12 ps >10.3125 Gb/s 150 - 1250 mV 6.6 Gb/s to 10.3125 Gb/s 150 - 1250 mV 6.6 Gb/s 150 - 2000 mV Differential peak-to-peak input voltage (external AC coupled) DVPPIN Equation based MGTAVTT - DVPPOUT/4 mV VIN Absolute input voltage DC coupled MGTAVTT = 1.2V -200 - MGTAVTT mV VCMIN Common mode input voltage DC coupled MGTAVTT = 1.2V - 2/3 MGTAVTT - mV RIN Differential input resistance - 100 - - 100 - nF CEXT Recommended external AC coupling capacitor(2) Notes: 1. 2. The output swing and preemphasis levels are programmable using the attributes discussed in UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide and can result in values lower than reported in this table. Other values can be used as appropriate to conform to specific protocols and standards. X-Ref Target - Figure 1 +V P Single-Ended Voltage N 0 ds182_01_041712 Figure 1: Single-Ended Peak-to-Peak Voltage X-Ref Target - Figure 2 +V Differential Voltage 0 -V P-N ds182_02_042712 Figure 2: Differential Peak-to-Peak Voltage DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 46 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 52 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide for further details. Table 52: GTX Transceiver Clock DC Input Level Specification Symbol DC Parameter Min Typ Max Units 250 - 2000 mV VIDIFF Differential peak-to-peak input voltage RIN Differential input resistance - 100 - CEXT Required external AC coupling capacitor - 100 - nF GTX Transceiver Switching Characteristics Consult UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide for further information. Table 53: GTX Transceiver Performance Speed Grade 1.0V Symbol Output Divider Description -3 0.9V -1(1) -2/-2L -2L(2) Units Package Type FGTXMAX(3) FGTXMIN (3) FGTXCRANGE FF FB FF FB FF FB FF FB Maximum GTX transceiver data rate 12.5 6.6 10.3125 6.6 6.6 6.6 6.6 6.6 Gb/s Minimum GTX transceiver data rate 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 Gb/s CPLL line rate range 1 3.2-6.6 Gb/s 2 1.6-3.3 Gb/s 4 0.8-1.65 Gb/s 8 0.5-0.825 Gb/s 16 N/A Gb/s 1 FGTXQRANGE1 QPLL line rate range 1 5.93- 8.0 5.93- 6.6 5.93- 8.0 5.93- 6.6 5.93-6.6 5.93-6.6 Gb/s 2 2.965-4.0 2.965-4.0 2.965-3.3 2.965-3.3 Gb/s 4 1.4825-2.0 1.4825-2.0 1.4825-1.65 1.4825-1.65 Gb/s 8 0.74125-1.0 0.74125-1.0 0.74125-0.825 0.74125-0.825 Gb/s 16 N/A N/A N/A N/A Gb/s N/A N/A N/A Gb/s 1 9.8- 12.5 N/A 9.8- 10.3125 2 4.9-6.25 4.9-5.15625 N/A N/A Gb/s 4 2.45-3.125 2.45-2.578125 N/A N/A Gb/s 8 1.225-1.5625 1.225-1.2890625 N/A N/A Gb/s 0.6125-0.78125 0.6125- 0.64453125 N/A N/A Gb/s GTX transceiver CPLL frequency range 1.6-3.3 1.6-3.3 1.6-3.3 1.6-3.3 GHz FGQPLLRANGE1 GTX transceiver QPLL frequency range 1 5.93-8.0 5.93-8.0 5.93-6.6 5.93-6.6 GHz FGTXQRANGE2 QPLL line rate range 2(4) 16 FGCPLLRANGE DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 47 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 53: GTX Transceiver Performance (Cont'd) Speed Grade 1.0V Symbol Output Divider Description -3 0.9V -1(1) -2/-2L -2L(2) Units Package Type FF FGQPLLRANGE2 GTX transceiver QPLL frequency range 2 FB 9.8-12.5 FF FB FF 9.8-10.3125 FB FF FB N/A N/A GHz Notes: 1. 2. 3. 4. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s. The -2L (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8 Gb/s. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s. Table 54: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Speed Grade Symbol FGTXDRPCLK Description 1.0V GTXDRPCLK maximum frequency 0.9V -3 -2/-2L -1 -2L 175 175 156.25 125 Units MHz Table 55: GTX Transceiver Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Units Min Typ Max -3 speed grade 60 - 700 MHz All other speed grades 60 - 670 MHz FGCLK Reference clock frequency range TRCLK Reference clock rise time 20% - 80% - 200 - ps TFCLK Reference clock fall time 80% - 20% - 200 - ps TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 % X-Ref Target - Figure 3 TRCLK 80% 20% TFCLK ds182_03_042712 Figure 3: Reference Clock Timing Parameters DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 48 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 56: GTX Transceiver PLL /Lock Time Adaptation Symbol TLOCK Description All Speed Grades Conditions Typ Max - - 1 ms x106 UI Initial PLL lock Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE). TDLOCK After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled. Units Min - 50,000 37 - 50,000 2.3 x106 UI 0.9V Units Table 57: GTX Transceiver User Clock Switching Characteristics(1)(2) Speed Grade Symbol Description Conditions 1.0V -3(3) -2/-2L(3) -1(4) -2L(5) FTXOUT TXOUTCLK maximum frequency 412.5 412.5 312.5 237.5 MHz FRXOUT RXOUTCLK maximum frequency 412.5 412.5 312.5 237.5 MHz FTXIN TXUSRCLK maximum frequency 16-bit data path 412.5 412.5 312.5 237.5 MHz 32-bit data path 391 322.5 206.5 206.5 MHz FRXIN RXUSRCLK maximum frequency 16-bit data path 412.5 412.5 312.5 237.5 MHz 32-bit data path 391 322.5 206.5 206.5 MHz 16-bit data path 412.5 412.5 312.5 237.5 MHz 32-bit data path 391 322.5 206.5 206.5 MHz 64-bit data path 195.5 161.5 103.5 103.5 MHz 16-bit data path 412.5 412.5 312.5 237.5 MHz 32-bit data path 391 322.5 206.5 206.5 MHz 64-bit data path 195.5 161.5 103.5 103.5 MHz FTXIN2 TXUSRCLK2 maximum frequency FRXIN2 RXUSRCLK2 maximum frequency Notes: 1. 2. 3. 4. 5. Clocking must be implemented as described in UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide. These frequencies are not supported for all possible transceiver configurations. For speed grades -3, -2, -2L (1.0V), a 16-bit data path can only be used for speeds less than 6.6 Gb/s. For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s. For speed grade -2L (0.9V), a 16-bit data path can only be used for speeds less than 3.8 Gb/s. Table 58: GTX Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units 0.500 - FGTXMAX Gb/s - ps FGTXTX Serial data rate range TRTX TX Rise time 20%-80% - 40 TFTX TX Fall time 80%-20% - 40 - ps TLLSKEW TX lane-to-lane skew(1) - - 500 ps VTXOOBVDPP Electrical idle amplitude - - 15 mV TTXOOBTRANSITION Electrical idle transition time - - 140 ns - - 0.28 UI - - 0.17 UI - - 0.28 UI - - 0.17 UI Jitter(2)(4) TJ12.5 Total DJ12.5 Deterministic Jitter(2)(4) TJ11.18 Total Jitter(2)(4) DJ11.18 Deterministic DS182 (v1.6) July 25, 2012 Preliminary Product Specification Jitter(2)(4) 12.5 Gb/s 11.18 Gb/s www.xilinx.com 49 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 58: GTX Transceiver Transmitter Switching Characteristics (Cont'd) Symbol TJ10.3125 Description Total Jitter(2)(4) Jitter(2)(4) DJ10.3125 Deterministic TJ9.953 Total Jitter(2)(4) DJ9.953 TJ9.8 Deterministic Total Jitter(2)(4) Jitter(2)(4) Jitter(2)(4) DJ9.8 Deterministic TJ8.0 Total Jitter(2)(4) DJ8.0 Deterministic Jitter(2)(4) TJ6.6_QPLL Total Jitter(2)(4) Jitter(2)(4) DJ6.6_QPLL Deterministic TJ6.6_CPLL Total Jitter(3)(4) DJ6.6_CPLL Deterministic Jitter(3)(4) TJ5.0 Total Jitter(3)(4) Jitter(3)(4) DJ5.0 Deterministic TJ4.25 Total Jitter(3)(4) DJ4.25 Deterministic Jitter(3)(4) TJ3.75 Total Jitter(3)(4) Jitter(3)(4) DJ3.75 Deterministic TJ3.2 Total Jitter(3)(4) DJ3.2 Deterministic Jitter(3)(4) TJ3.2L Total Jitter(3)(4) Jitter(3)(4) DJ3.2L Deterministic TJ2.5 Total Jitter(3)(4) DJ2.5 Deterministic Jitter(3)(4) TJ1.25 Total Jitter(3)(4) Jitter(3)(4) DJ1.25 Deterministic TJ500 Total Jitter(3)(4) DJ500 Deterministic Jitter(3)(4) Condition 10.3125 Gb/s 9.953 Gb/s 9.8 Gb/s 8.0 Gb/s 6.6 Gb/s 6.6 Gb/s 5.0 Gb/s 4.25 Gb/s 3.75 Gb/s 3.20 Gb/s(5) 3.20 Gb/s(6) 2.5 Gb/s(7) 1.25 Gb/s(8) 500 Mb/s Min Typ Max Units - - 0.28 UI - - 0.17 UI - - 0.28 UI - - 0.17 UI - - 0.28 UI - - 0.17 UI - - 0.30 UI - - 0.15 UI - - 0.28 UI - - 0.17 UI - - 0.30 UI - - 0.15 UI - - 0.30 UI - - 0.15 UI - - 0.30 UI - - 0.15 UI - - 0.30 UI - - 0.15 UI - - 0.2 UI - - 0.1 UI - - 0.32 UI - - 0.16 UI - - 0.20 UI - - 0.08 UI - - 0.15 UI - - 0.06 UI - - 0.1 UI - - 0.03 UI Notes: 1. 2. 3. 4. 5. 6. 7. 8. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads). Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 1e-12. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 50 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 59: GTX Transceiver Receiver Switching Characteristics Symbol Description RX oversampler not enabled Min Typ Max Units 0.500 - FGTXMAX Gb/s FGTXRX Serial data rate TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data - 10 - ns RXOOBVDPP OOB detect threshold peak-to-peak 60 - 150 mV RXSST Receiver spread-spectrum tracking(1) -5000 - 0 ppm RXRL Run length (CID) - - 512 UI Bit rates 6.6 Gb/s -1250 - 1250 ppm Bit rates > 6.6 Gb/s and 8.0 Gb/s -700 - 700 ppm Bit rates > 8.0 Gb/s -200 - 200 ppm Data/REFCLK PPM offset tolerance RXPPMTOL SJ Jitter Modulated @ 33 KHz Tolerance(2) JT_SJ12.5 JT_SJ11.18 JT_SJ10.32 JT_SJ9.95 JT_SJ9.8 JT_SJ8.0 JT_SJ6.6_QPLL JT_SJ6.6_CPLL JT_SJ5.0 JT_SJ4.25 JT_SJ3.75 JT_SJ3.2 JT_SJ3.2L JT_SJ2.5 JT_SJ1.25 JT_SJ500 Sinusoidal Jitter (QPLL)(3) 12.5 Gb/s 0.3 - - UI Sinusoidal Jitter (QPLL)(3) 11.18 Gb/s 0.3 - - UI Sinusoidal Jitter (QPLL)(3) 10.32 Gb/s 0.3 - - UI Sinusoidal Jitter (QPLL)(3) 9.95 Gb/s 0.3 - - UI Sinusoidal Jitter (QPLL)(3) 9.8 Gb/s 0.3 - - UI Sinusoidal Jitter (QPLL)(3) 8.0 Gb/s 0.44 - - UI Sinusoidal Jitter (QPLL)(3) 6.6 Gb/s 0.48 - - UI Sinusoidal Jitter (CPLL)(3) 6.6 Gb/s 0.44 - - UI Sinusoidal Jitter (CPLL)(3) 5.0 Gb/s 0.44 - - UI Sinusoidal Jitter (CPLL)(3) 4.25 Gb/s 0.44 - - UI Sinusoidal Jitter (CPLL)(3) 3.75 Gb/s Sinusoidal Jitter (CPLL)(3) Sinusoidal Jitter (CPLL)(3) Sinusoidal Jitter (CPLL)(3) Sinusoidal Jitter (CPLL)(3) 1.25 Sinusoidal Jitter (CPLL)(3) SJ Jitter Tolerance with Stressed JT_TJSE3.2 JT_TJSE6.6 JT_SJSE3.2 JT_SJSE6.6 0.44 - - UI 3.2 Gb/s(4) 0.45 - - UI 3.2 Gb/s(5) 0.45 - - UI 2.5 Gb/s(6) 0.5 - - UI 0.5 - - UI 500 Mb/s 0.4 - - UI 3.2 Gb/s 0.70 - - UI 6.6 Gb/s 0.70 - - UI 3.2 Gb/s 0.1 - - UI 6.6 Gb/s 0.1 - - UI Gb/s(7) Eye(2) Total Jitter with Stressed Eye(8) Sinusoidal Jitter with Stressed Eye(8) Notes: 1. 2. 3. 4. 5. 6. 7. 8. Using RXOUT_DIV = 1, 2, and 4. All jitter values are based on a bit error ratio of 1e-12. The frequency of the injected sinusoidal jitter is 10 MHz. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. Composite jitter with RX and LPM or DFE mode. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 51 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics GTX Transceiver Protocol Jitter Characteristics For Table 60 through Table 65, the UG476: 7 Series FPGAs GTX/GTH Transceiver User Guide contains recommended settings for optimal usage of protocol specific characteristics. Table 60: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 1250 - 0.24 UI 1250 0.749 - UI Line Rate (Mb/s) Min Max Units 3125 - 0.35 UI 3125 0.65 - UI Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance Table 61: XAUI Protocol Characteristics Description XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance Table 62: PCI Express Protocol Characteristics(1) Standard Description Line Rate (Mb/s) Min Max Units PCI Express Transmitter Jitter Generation PCI Express Gen 1 Total transmitter jitter 2500 - 0.25 UI PCI Express Gen 2 Total transmitter jitter 5000 - 0.25 UI - 31.25 ps - 12 ps 0.65 - UI 0.40 - UI 0.30 - UI 1.00 - UI Note 4 - UI 0.10 - UI PCI Express Gen 3(2) Total transmitter jitter uncorrelated Deterministic transmitter jitter uncorrelated 8000 PCI Express Receiver High Frequency Jitter Tolerance PCI Express Gen 1 PCI Express Gen 2(3) Total receiver jitter tolerance 2500 Receiver inherent timing error Receiver inherent deterministic timing error 5000 0.03 MHz-1.0 MHz PCI Express Gen 3(2) Receiver sinusoidal jitter tolerance 1.0 MHz-10 MHz 8000 10 MHz-100 MHz Notes: 1. 2. 3. 4. Tested per card electromechanical (CEM) methodology. PCI-SIG 3.0 certification and compliance test boards are currently not available. Using common REFCLK. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 52 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 63: CEI-6G and CEI-11G Protocol Characteristics Description Line Rate (Mb/s) Interface Min Max Units CEI-6G-SR - 0.3 UI CEI-6G-LR - 0.3 UI CEI-6G-SR 0.6 - UI CEI-6G-LR 0.95 - UI CEI-11G-SR - 0.3 UI CEI-11G-LR/MR - 0.3 UI CEI-11G-SR 0.65 - UI CEI-11G-MR 0.65 - UI CEI-11G-LR 0.825 - UI CEI-6G Transmitter Jitter Generation Total transmitter jitter(1) 4976-6375 CEI-6G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(1) 4976-6375 CEI-11G Transmitter Jitter Generation Total transmitter jitter(2) 9950-11100 CEI-11G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(2) 9950-11100 Notes: 1. 2. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. Table 64: SFP+ Protocol Characteristics Description Line Rate (Mb/s) Min Max Units - 0.28 UI 0.7 - UI SFP+ Transmitter Jitter Generation 9830.40(1) 9953.00 Total transmitter jitter 10312.50 10518.75 11100.00 SFP+ Receiver Frequency Jitter Tolerance 9830.40(1) 9953.00 Total receiver jitter tolerance 10312.50 10518.75 11100.00 Notes: 1. Line rated used for CPRI over SFP+ applications. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 53 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 65: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units 614.4 - 0.35 UI 1228.8 - 0.35 UI 2457.6 - 0.35 UI 3072.0 - 0.35 UI 4915.2 - 0.3 UI 6144.0 - 0.3 UI 9830.4 - Note 1 UI 614.4 0.65 - UI 1228.8 0.65 - UI 2457.6 0.65 - UI 3072.0 0.65 - UI 4915.2 0.95 - UI 6144.0 0.95 - UI 9830.4 Note 1 - UI CPRI Transmitter Jitter Generation Total transmitter jitter CPRI Receiver Frequency Jitter Tolerance Total receiver jitter tolerance Notes: 1. Tested per SFP+ specification, see Table 64. Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: http://www.xilinx.com/technology/protocols/pciexpress.htm Table 66: Maximum Performance for PCI Express Designs Speed Grade Symbol Description 1.0V 0.9V -3 -2/-2L -1 -2L Units FPIPECLK Pipe clock maximum frequency 250 250 250 250 MHz FUSERCLK User clock maximum frequency 500 500 250 250 MHz FUSERCLK2 User clock 2 maximum frequency 250 250 250 250 MHz FDRPCLK DRP clock maximum frequency 250 250 250 250 MHz DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 54 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics XADC Specifications Table 67: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = -40C to 100C, Typical values at Tj=+40C ADC Accuracy(1) Resolution 12 - - Bits - - 3 LSBs No missing codes, guaranteed monotonic - - 1 LSBs Offset Error Offset calibration enabled - - 6 LSBs Gain Error Gain calibration disabled - - 0.5 % Offset Matching Offset calibration enabled - - 4 LSBs Gain Matching Gain calibration disabled - - 0.3 % 0.1 - 1 MS/s FSAMPLE = 500KS/s, FIN = 20KHz 60 - - dB External 1.25V reference - - 2 LSBs On-chip reference - 3 - LSBs FSAMPLE = 500KS/s, FIN = 20KHz - 70 - dB 10 - - Bits - - 1 No missing codes, guaranteed monotonic - - 1 LSB (at 10 bits) Unipolar operation 0 - 1 V -0.5 - +0.5 V Unipolar common mode range (FS input) 0 - +0.5 V Bipolar common mode range (FS input) +0.5 - +0.6 V Adjacent channels set within these ranges should not corrupt measurements on adjacent channels -0.1 - VCCADC V 250 - - KHz Tj = -40C to 100C. - - 4 C Tj = -55C to +125C - - 6 C Measurement range of VCCAUX 1.8V 5% Tj = -40C to +100C - - 1 % Measurement range of VCCAUX 1.8V 5% Tj = -55C to +125C - - 2 % Integral Nonlinearity(2) Differential Nonlinearity INL DNL Sample Rate Signal to Noise Ratio(2) SNR RMS Code Noise Total Harmonic Distortion(2) THD ADC Accuracy at Extended Temperatures (-55C to 125C) Resolution Integral Nonlinearity(2) Differential Nonlinearity Analog INL DNL Inputs(3) ADC Input Ranges Bipolar operation Maximum External Channel Input Ranges Auxiliary Channel Full Resolution Bandwidth FRBW On-Chip Sensors Temperature Sensor Error(4) Supply Sensor Error Conversion Rate(5) Conversion Time - Continuous tCONV Number of ADCCLK cycles 26 - 32 Conversion Time - Event tCONV Number of CLK cycles - - 21 DRP Clock Frequency DCLK DRP clock frequency 8 - 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK 1 - 26 MHz 40 - 60 % DCLK Duty Cycle DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 55 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 67: XADC Specifications (Cont'd) Parameter Symbol Comments/Conditions Min Typ Max Units 1.20 1.25 1.30 V 1.2375 1.25 1.2625 V XADC Reference(6) External Reference VREFP Externally supplied reference voltage Ground VREFP pin to AGND, Tj = -40C to 100C On-Chip Reference Notes: 1. 2. 3. 4. 5. 6. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. Only specified for new BitGen option XADCEnhancedLinearity = ON. See the ADC chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description. Accuracy of temperature sensor error data is based on characterization at Tj = 0C to 125C. See the Timing chapter in UG480: 7 Series FPGAs XADC User Guide for a detailed description. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by 4% is permitted. On-chip reference variation is 1%. Configuration Switching Characteristics Table 68: Configuration Switching Characteristics Speed Grade Symbol Description 1.0V 0.9V Units -3 -2/-2L -1 -2L 5 5 5 5 ms, Max Power-up Timing Characteristics TPL(1) Program latency TPOR(1) Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 ms, Min/Max 250 250 250 250 ns, Min 150 150 150 150 ns, Min TPROGRAM Program pulse width CCLK Output (Master Mode) TICCK Master CCLK output delay TMCCKL Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 %, Min/Max FMCCK Master CCLK frequency 100 100 100 70 MHz, Max Master CCLK frequency for AES encrypted x16 50 50 50 50 MHz, Max FMCCK_START Master CCLK frequency at start of configuration 3 3 3 3 MHz, Typ FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK 50 50 50 50 %, Max CCLK Input (Slave Modes) TSCCKL Slave CCLK clock minimum Low time 2.50 2.50 2.50 2.50 ns, Min TSCCKH Slave CCLK clock minimum High time 2.50 2.50 2.50 2.50 ns, Min FSCCK Slave CCLK frequency 100 100 100 70 MHz, Max EMCCLK Input (Master Mode) TEMCCKL External master CCLK Low time 2.50 2.50 2.50 2.50 ns, Min TEMCCKH External master CCLK High time 2.50 2.50 2.50 2.50 ns, Min FEMCCK External master CCLK frequency 100 100 100 70 MHz, Max Master/Slave Serial Mode Programming Switching TDCCK/TCCKD DIN Setup/Hold DS182 (v1.6) July 25, 2012 Preliminary Product Specification 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min www.xilinx.com 56 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Table 68: Configuration Switching Characteristics (Cont'd) Speed Grade Symbol Description TCCO 1.0V DOUT clock to out 0.9V -3 -2/-2L -1 -2L 8.00 8.00 8.00 9.00 Units ns, Max SelectMAP Mode Programming Switching TSMDCCK/TSMCCKD D[31:00] Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min TSMCSCCK/TSMCCKCS CSI_B Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min TSMWCCK/TSMCCKW RDWR_B Setup/Hold 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00 ns, Min TSMCKCSO CSO_B clock to out (330 pull-up resistor required) 7.00 7.00 7.00 8.00 ns, Max TSMCO D[31:00] clock to out in readback 8.00 8.00 8.00 10.00 ns, Max FRBCCK Readback frequency 100 100 100 70 MHz, Max Boundary-Scan Port Timing Specifications TTAPTCK/TTCKTAP TMS and TDI Setup/Hold TTCKTDO TCK falling edge to TDO output FTCK TCK frequency 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min 7.00 7.00 7.00 8.50 ns, Max 66 66 66 50 MHz, Max 8.50 8.50 8.50 10.00 ns, Max BPI Master Flash Mode Programming Switching TBPICCO(2) A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out TBPIDCC/TBPICCD D[15:00] Setup/Hold 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 ns, Min SPI Master Flash Mode Programming Switching TSPIDCC/TSPICCD D[03:00] Setup/Hold TSPICCM MOSI clock to out 8.00 8.00 8.00 9.00 ns, Max TSPICCFC FCS_B clock to out 8.00 8.00 8.00 9.00 ns, Max Notes: 1. 2. To support longer delays in configuration, use the design solutions described in UG470: 7 Series FPGA Configuration User Guide. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O. eFUSE Programming Conditions Table 69 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA Configuration User Guide. Table 69: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IFS VCCAUX supply current - - 115 mA tj Temperature range 15 - 125 C Notes: 1. The FPGA must not be configured during eFUSE programming. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 57 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Revision History The following table shows the revision history for this document: Date Version Description 03/01/11 1.0 Initial Xilinx release. 04/01/11 1.1 Added the XC7K355T, XC7K420T, and XC7K480T devices throughout data sheet. Added the extended temperature range discussion to page 1. Updated VCCAUX_IO in Table 2. Edits to clarify Power-On/Off Power Supply Sequencing power sequencing discussion. Added ICCAUX_IO and ICCBRAM to Table 6 and Table 7. Updated MMCM_FINDUTY and added FINJITTER, TOUTJITTER, TEXTFDVAR, and Note 3 to Table 38. Removed the SBG324 package from Table 50. Updated the Notice of Disclaimer. 10/04/11 1.2 Replaced -1L with -2L throughout this data sheet. Updated Min/Max values and removed Note 5 from Table 2. Clarified Power-On/Off Power Supply Sequencing power sequencing discussion including adding TVCCO2VCCAUX to Table 8. Updated VICM in Table 12 and Table 13. Added Note 1 to table 12. Updated Table 69 including adding Note 1. Added Absolute Maximum Ratings for GTX Transceivers. Revised the reference clock maximum frequency (FGCLK) in Table 55. Added Table 57. Added LVTTL and removed SSTL135_II and SSTL15_II specifications from Table 19. Removed HSTL_III from Table 20. Removed the I/O Standard Adjustment Measurement Methodology section. Use IBIS for more accurate information and measurements. Updated TIDELAYPAT_JIT in Table 26. Added TAS/TAH to Table 28. Added TRDCK_DI_WF_NC/TRCKD_DI_WF_NC and TRDCK_DI_RF/TRCKD_DI_RF to Table 31. Completely updated Table 68. Updated the AC Switching Characteristics in Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, Table 26 through Table 38, Table 40 though Table 37, and Table 67. 11/03/11 1.3 Revised the VOCM specification in Table 12. Updated the AC Switching Characteristics based upon the ISE 13.3 v1.02 speed specification throughout document including Table 19 and Table 20. Added MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in Table 38 and PLL to the symbol names in Table 39. In Table 40 through Table 47, updated the pin-to-pin descriptions with the SSTL15 standard. Updated units in Table 49. 02/13/12 1.4 Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and updated Tj. Added typical values to Table 3. Updated the notes in Table 6. Added MGTAVCC, MGTAVTT, and MGTVCCAUX power supply ramp times to Table 8. Rearranged Table 9, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 10 and Table 11. Revised the specifications in Table 12 and Table 13. Updated the eFUSE Programming Conditions section and removed the endurance table. Added the IO_FIFO Switching Characteristics table. Revised ICCADC and updated Note 1 in Table 67. Revised DDR LVDS transmitter data width in Table 16. Updated the AC Switching Characteristics based upon the ISE 13.4 v1.03 speed specification throughout document. Removed notes from Table 28 as they are no longer applicable. Updated specifications in Table 68. Updated Note 1 in Table 37. In the GTX Transceiver DC Input and Output Levels section: Revised VIN, and added IDCIN and IDCOUT to Table 51. Added Note 4 to Table 53. In Table 55, revised FGCLK, removed TPHASE, and added TDLOCK. Revised specifications and added Note 2 to Table 57. Added Table 58 and Table 59 along with GTX Transceiver Protocol Jitter Characteristics in Table 60 through Table 65. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 58 Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics Date Version Description 05/23/12 1.5 Reorganized entire data sheet including adding Table 44 and Table 48. Updated TSOL in Table 1. Updated IBATT and added RIN_TERM to Table 3. Added values to Table 6 and Table 7. Updated Power-On/Off Power Supply Sequencing, page 6 with regards to GTX transceivers. Updated many parameters in Table 9 including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 11. Updated VOL in Table 12. Updated Table 16 and removed notes 2 and 3. Updated Table 17. Updated the AC Switching Characteristics based upon the ISE 14.1 v1.04 for the -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed specifications throughout the document. In Table 31, updated Reset Delays section including Note 10 and Note 11. Added data for TLOCK and TDLOCK in Table 55. Updated many of the XADC specifications in Table 67 and added Note 2. Updated and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from Table 68 to Table 38 and Table 39. 07/25/12 1.6 Updated the descriptions, changed VIN and Note 2 and added Note 4 in Table 1. In Table 2, changed descriptions and notes, removed Note 7, changed GTX transceiver parameters and values and added Note 8. Updated parameters in Table 3. Added Table 4 and Table 5. Changed the typical values for many of the devices in Table 7. Updated LVCMOS12 and the SSTLs in Table 9. Updated many of the specifications in Table 10 and Table 11. Updated speed specification to v1.06 (-3, -2, -2L(1.0V), -1) and v1.05 (-2L(0.9V)) with appropriate changes to Table 14 and Table 15 including production release of the XC7K325T and the XC7K410T in the -2, -2L(1.0V), -1 speed designations. Added notes and specifications to Table 17 and Table 18. Updated the IOB Pad Input/Output/3-State discussion and changed Table 21 by adding TIOIBUFDISABLE. Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from Table 28. Rearranged Table 51 including moving some parameters to Table 1. Added Table 56. Updated Table 57. In Table 59, updated SJ Jitter Tolerance with Stressed Eye section, page 51 and Note 8. Added Note 1, Note 2, and Note 3 to Table 62. Added Note 1 and Note 2 to Table 63, and line rate ranges. Updated Table 64 including adding Note 1. Updated Table 65 including adding Note 1. In Table 67 updated Note 1 and added Note 4. In Table 68, updated TPOR and FEMCCK. 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AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAILSAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS182 (v1.6) July 25, 2012 Preliminary Product Specification www.xilinx.com 59