Features
•16 Mbit SRAM Multi Chip Module
•Allows 32-, 16- or 8-bit access configuration
•Operating Voltage: 3.3V + 0.3V
•Access Time
– 20 ns, 18 ns for AT68166F
•Power Consumption
– Active: 620 mW per byte (Max) @ 18ns - 415 mW per byte (Max) @ 50ns (1)
– Standby: 13 mW (Typ)
•Military Temperature Range: -55 to +125°C
•TTL-Compatible Inputs and Outputs
•Asynchronous
•Die manufactured on Atmel 0.25 µm Radiation Hardened Process
•No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2
•Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
•ESD Better than 4000V
•Quality Grades:
– QML-Q or V with SMD 5962-06229
–ESCC
•950 Mils Wide MQFP 68 Package
•Mass : 8.5 grams
Note: 1. Only for AT68166F-18. 450mW for AT68166F-20.
Description
The AT68166F is a 16Mbit SRAM packaged in a hermetic Multi Chip Module
(MCM) for space applications.
The AT68166F MCM incorporates four 4Mbit AT60142FT SRAM dice. It can be orga-
nized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It
combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit
Upset immunity and a total dose tolerance of 300Krads, with a fast access time.
The MCM packaging technology allows a reduction of the PCB area by 50% with a
weight savings of 75% compared to four 4Mbit packages.
Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo-
date the assembly of the four dice on one side of the package which facilitates the
power dissipation.
The compatibility with other products allows designers to easily migrate to the Atmel
AT68166F memory.
The AT68166F is powered at 3.3V.
The AT68166F is processed according to the test methods of the latest revision of the
MIL-PRF-38535 or the ESCC 9000.
7747B–AERO–04/09
Rad Hard
16 MegaBit 3.3V
SRAM Multi-
Chip Module
AT68166F
2
7747B–AERO–04/09
AT68166F
Block Diagram Figure 1. AT68166F Block Diagram
Figure 2. 512K x 8 Banks Block Diagram (AT60142F)
Packages AT68166F and AT68166G are packed in MQFP68.
The pin assignment depends on the access time. There are 2 versions:
– YM package where 3 pins are not connected.
– YS package where the 3 above pins are connected to GND or VCC.
A[18:0]
OE
CS1
WE1
I/O[15:8]
BANK1
512k x 8
CS2
WE2
I/O[23:16]
BANK2
512k x 8
CS3
WE3
I/O[31:24]
BANK3
512k x 8
CS0
WE0
I/O[7:0]
BANK0
512k x 8
or
I/O2[31:16]
or
I/O2[15:0]
or
I/O1[31:16]
or
I/O1[15:0]
or
I/O3[7:0]
or
I/O2[7:0]
or
I/O1[7:0]
or
I/O[7:0]
A0
-
-
-
A10
I/Ox0
I/Ox7
CSx
WEx
OE
Access Time
20 ns 18 ns <18 ns
AT68166F YM YS
AT68166G YS
3
7747B–AERO–04/09
AT68166F
Pin
Configuration
Table 1. AT68166F pin assignment in YS package
Notes: 1. In YM package leads 33, 34 and 68 are not connected.
Lead Signal Lead Signal Lead Signal Lead Signal
1 I/O0[0] 18 VCC 35 I/O3[7] 52 VCC
2 I/O0[1] 19 A11 36 I/O3[6] 53 A10
3 I/O0[2] 20 A12 37 I/O3[5] 54 A9
4 I/O0[3] 21 A13 38 I/O3[4] 55 A8
5 I/O0[4] 22 A14 39 I/O3[3] 56 A7
6 I/O0[5] 23 A15 40 I/O3[2] 57 A6
7 I/O0[6] 24 A16 41 I/O3[1] 58 WE0
8 I/O0[7] 25 CS0 42 I/O3[0] 59 CS3
9GND26OE43 GND 60 GND
10 I/O1[0] 27 CS1 44 I/O2[7] 61 CS2
11 I/O1[1] 28 A17 45 I/O2[6] 62 A5
12 I/O1[2] 29 WE1 46 I/O2[5] 63 A4
13 I/O1[3] 30 WE2 47 I/O2[4] 64 A3
14 I/O1[4] 31 WE3 48 I/O2[3] 65 A2
15 I/O1[5] 32 A18 49 I/O2[2] 66 A1
16 I/O1[6] 33 GND 50 I/O2[1] 67 A0
17 I/O1[7] 34 VCC 51 I/O2[0] 68 VCC
4
7747B–AERO–04/09
AT68166F
Figure 3. AT68166F pin assignment in YM package
Figure 4. AT68166F pin assignment in YS package
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
AT68166F
(top view)
NC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
NC
NC
A18
WE3
WE2
WE1
A17
CS1
0E
CS0
A16
A15
A14
A13
A12
A11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
AT68166F
(top view)
VCC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
VCC
GND
A18
WE3
WE2
WE1
A17
CS1
0E
CS0
A16
A15
A14
A13
A12
A11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
5
7747B–AERO–04/09
AT68166F
Pin Description Table 2. Pin Names
Note: 1. The package lid is connected to GND
Table 3. Truth Table(1)
Name Description
A0 - A18 Address Inputs
I/O0 - I/O31 Data Input/Output
CS0 - CS3 Chip Select
WE0 - WE3 Write Enable
OE Output Enable
VCC Power Supply
GND(1) Ground
CSxWEx OE Inputs/Outputs Mode
H X X Z Standby
L H L Data Out Read
L L X Data In Write
L H H Z Output Disable
Note: 1. L=low, H=high, X= H or L, L=high impedance.
6
7747B–AERO–04/09
AT68166F
Electrical Characteristics
Absolute Maximum Ratings*
Military Operating Range
Recommended DC Operating Conditions
Capacitance
Note: 1. Guaranteed but not tested.
Supply Voltage to GND Potential: ....................... -0.5V + 4.6V
Voltage range on any input: ...................... GND -0.5V to 4.6V
Voltage range on any ouput: ..................... GND -0.5V to 4.6V
Storage Temperature: ................................. -65°C to + 150°C
Output Current from Output Pins: ................................ 20 mA
Electrostatic Discharge Voltage: ............................... > 4000V
(MIL STD 883D Method 3015.3)
*NOTE: Stresses beyond those listed under "Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure between recommended DC
operating and absolute maximum rating
conditions for extended periods may
affect device reliability.
Operating Voltage Operating Temperature
3.3 + 0.3V -55°C to + 125°C
Parameter Description Min Typ Max Unit
Vcc Supply voltage 3 3.3 3.6 V
GND Ground 0.0 0.0 0.0 V
VIL Input low voltage GND - 0.3 0.0 0.8 V
VIH Input high voltage 2.2 – VCC + 0.3 V
Parameter Description Min Typ Max Unit
Cin(1) (OE and Ax) Input capacitance – – 48 pF
Cin(1) (CSx and
WEx) Input capacitance – – 12 pF
Cio(1) I/O capacitance – – 12 pF
7
7747B–AERO–04/09
AT68166F
DC Parameters
Notes: 1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2. VCC min. IOL = 8 mA
3. VCC min. IOH = -4 mA
Consumption
Notes: 1. All CSx >VIH
2. All CSx > VCC - 0.3V
3. F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
4. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
Parameter Description Minimum Typical Maximum Unit
IIX(1) Input leakage current -1 – 1 μA
IOZ(1) Output leakage
current -1 – 1 μA
VOL(2) Output low voltage – – 0.4 V
VOH(3) Output high voltage 2.4 – – V
Symbol Description
TAVAV/TAVAW Test
Condition
AT68166F-20 AT68166F-18
Unit Value
ICCSB(1) Standby
Supply Current –107mAmax
ICCSB1(2) Standby
Supply Current – 8 6 mA max
ICCOP(3) Read
per byte
Dynamic
Operating
Current
18 ns
20 ns
50 ns
1 µs
–
170
85
15
170
165
80
12
mA max
ICCOP(4) Write
per byte
Dynamic
Operating
Current
18 ns
20 ns
50 ns
1 µs
–
150
125
110
145
140
115
105
mA max
8
7747B–AERO–04/09
AT68166F
Data Retention
Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-
ply current are guaranteed over temperature. The following rules insure data retention:
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-
mizing power dissipation.
3. During power-up and power-down transitions CSx and OE must be kept between VCC +
0.3V and 70% of VCC.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 5. Data Retention Timing
Data Retention Characteristics
vcc
CSx
Parameter Description Min Typ TA = 25°CMax Unit
VCCDR VCC for data retention 2.0 – – V
tCDR
Chip deselect to data
retention time 0.0 – – ns
tR
Operation recovery
time tAVAV (1)
1. TAVAV = Read cycle time.
––ns
ICCDR (2)
2. All CSx = VCC, VIN = GND/VCC.
Data retention current – 3
6 (AT68166F-20)
mA
4.5 (AT68166F-18)
9
7747B–AERO–04/09
AT68166F
AC Characteristics
Temperature Range:................................................ -55 +125°C
Supply Voltage: ....................................................... 3.3 +0.3V
Input Pulse Levels: .................................................. GND to 3.0V
Input Rise and Fall Times:....................................... 3ns (10 - 90%)
Input and Output Timing Reference Levels: ............ 1.5V
Output Loading IOL/IOH:............................................ See Figure 3
Figure 6. AC Test Loads Waveforms
Write Cycle
Table 4. Write cycle timings(1)
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.)
Specific (TWLQZ, TWHQX, TELQX, TEHQZ
TGLQX, TGHQZ)
General
Symbol Parameter
AT68166F-20 AT68166F-18
Unitmin max min max
TAVAW Write cycle time 20 - 18 - ns
TAVWL Address set-up time 2 - 2 - ns
TAVWH Address valid to end of write 14 - 11 - ns
TDVWH Data set-up time 9 - 8 - ns
TELWH CS low to write end 12 - 12 - ns
TWLQZ Write low to high Z(2) -10- 8 ns
TWLWH Write pulse width 12 - 9 - ns
TWHAX Address hold from end of write 0 - 0 - ns
TWHDX Data hold time 2 - 1 - ns
TWHQX Write high to low Z(2) 5-3- ns
10
7747B–AERO–04/09
AT68166F
Figure 7. Write Cycle 1. WE Controlled, OE High During Write
Figure 8. Write Cycle 2. WE Controlled, OE Low
Figure 9. Write Cycle 3. CS Controlled
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in active mode. The data
input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
E
E
ADDRESS
CSx
WEx
I/Os
OE
E
E
ADDRESS
CSx
WEx
I/Os
E
ADDRESS
CSx
WEx
I/Os
11
7747B–AERO–04/09
AT68166F
Read Cycle
Table 5. Read cycle timings(1)
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.)
Figure 10. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH)
Symbol Parameter
AT68166F-20 AT68166F-18
Unitmin max min max
TAVAV Read cycle time 20 - 18 - ns
TAVQV Address access time - 20 - 18 ns
TAVQX Address valid to low Z 5 - 5 - ns
TELQV Chip-select access time - 20 - 18 ns
TELQX CS low to low Z(2) 5-5-ns
TEHQZ CS high to high Z(2) -9-8ns
TGLQV Output Enable access time - 11 - 8 ns
TGLQX OE low to low Z(2) 2-2-ns
TGHQZ OE high to high Z (2) -9-8ns
ADDRESS
DOUT
12
7747B–AERO–04/09
AT68166F
Figure 11. Read Cycle nb 2: Chip Select Controlled (WE = VIH)
CSx
OE
DOUT
13
7747B–AERO–04/09
AT68166F
Typical
Applications
This section presents some standard implementations of the AT68166F in application.
32-bit mode
application
When used on a 32-bit (word) application, the module shall be connected as follow :
• The 32 lines of data are connected to distinct data lines
• The four CSx are connected together and linked to a single host CS output
• Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half
word and word format write.
Figure 12. 32-bit typical application ( 1 SRAM bank)
16-bit mode
application
When used on a 16-bit (half word) application, the module can be connected as presented in the
following figure. This allows use of a single AT68166F part for two SRAM memory banks.
All input controls of the AT68166F not used in the application shall be pulled-up.
Figure 13. 16-bit typical application (two SRAM banks)
8-bit mode
application
When used on a 8-bit (byte) application, the module can be connected as presented in the fol-
lowing figure. This allows use of a single AT68166F part for up to four SRAM memory banks.
All input controls of the AT68166F not used in the application shall be pulled-up.
CS[3:0]
OE
WE[3:0]
A[17:0]
I/O[31:0]
AT68166F
RAMOE0*
AD
AT697E
A[27:0]
D[31:0]
D[31:0]
A[19:2]
RWE[3:0]*
RAMS0* A[19:2]
D[31:0]
A[17:0]
I/O[15:0]
AT68166F A
D
AT697E
A[27:0]
D[31:0]
D[31:16]
A[18:1]
A[18:1]
D[31:0]
I/O[31:16] D[31:16]
CS[1:0]
WE[1:0]
RWE0*
RAMS0*
CS[3:2]
WE[3:2]
RWE0*
RAMS1*
OE
RAMOE[1:0]*
14
7747B–AERO–04/09
AT68166F
Figure 14. 8-bit typical application (two SRAM banks)
A[17:0]
I/O[7:0]
AT68166F
A
D
AT697E
A[27:0]
D[31:0]
D[31:24]
A[17:0]
A[17:0]
D[31:0]
I/O[15:8] D[31:24]
CS[0]
WE[0]
RWE0*
RAMS0*
CS[1]
WE[1]
RWE0*
RAMS1*
OE
RAMOE[1:0]*
CS[3]
WE[3]
RWE0*
RAMS2*
CS[2]
WE[2]
RWE0*
RAMS2*
I/O[23:16] D[31:24]
I/O[31:24] D[31:24]
15
7747B–AERO–04/09
AT68166F
Ordering Information
Note: 1. Will be replaced by SMD part number when available.
Part Number Temperature Range Speed Package Flow
AT68166F
AT68166F-YM20-E 25°C 20 ns MQFP68 Engineering Samples
5962-0622902QXC -55° to +125°C 20 ns MQFP68 QML Q
5962-0622902VXC -55° to +125°C 20 ns MQFP68 QML V
5962R0622902VXC -55° to +125°C 20 ns MQFP68 QML V RHA
AT68166F-YM20-SCC -55° to +125°C 20 ns MQFP68 ESCC
AT68166F-YS18-E 25°C 18 ns MQFP68 Engineering Samples
5962-0622904QYC -55° to +125°C 18 ns MQFP68 QML Q
5962-0622904VYC -55° to +125°C 18 ns MQFP68 QML V
5962R0622904VYC -55° to +125°C 18 ns MQFP68 QML V RHA
AT68166F-YS18-SCC(1) -55° to +125°C 18 ns MQFP68 ESCC
16
7747B–AERO–04/09
AT68166F
Package Drawings
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note: 1. Lid is connected to Ground.
2. YM and YS package drawings are identical.
17
7747B–AERO–04/09
AT68166F
Document Revision History
Changes from
Rev. A to Rev. B
1. Suppression of version AT68166G
2. Update of Absolute Maximum Ratings section
Printed on recycled paper.
7747B–AERO–04/09
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