CS3511-CNZ - Cirrus Logic - Datasheet.Live

http://www.cirrus.com

Preliminary Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Stereo 10 W High-efficiency Class-D Audio Power Amplifier

Features

Closed-loop Advanced ΔΣ Architecture

True Spread Spectrum Modulation

Premium Quality Audio Amplification

– 99 dB Dynamic Range - System Level

– 0.025% THD+N @ 5 W - System Level

– -96 dB Channel Separation

Four Selectable Amplifier Gain Settings

Integrated Protection and Automatic Recovery

for Over-current, Under-voltage, and Thermal

Overload

Single-supply Operation (Typ. = 9-12 V)

No Bootstrap Capacitors Required

Low-power Standby Mode

Supports Differential or Single-ended Inputs

Thermally Enhanced 32-pin, 6 x 6 mm QFN

Package Requires No External Heat Sink

Common Applications

Active Speakers

Portable Media Player Docking Stations

Mini/Micro Shelf Systems

Digital Televisions

General Description

The CS3511 is a h igh-efficiency class-D PWM amplifier

that integrates on-chip over-current, under-voltage,

over-temperature protection, and error reporting. An on-

board regulator generates a 5 VDC supply used

to power the internal low-voltage analog and digital cir-

cuitry. The low RDS(ON) outputs can source peak cur-

rents up to 2.7 A, deliver high efficiency, allow a small

device package, and lower power supply voltage levels.

The CS3511 is available in a 32-pin QFN package in

Commercial grade (-10°C to +70°C). The CRD3511

customer reference design is also available. Please re-

fer to “Ordering Information” on page 24 for complete

ordering information.

GAIN0

GAIN1

MUTE

STATUS

Gain

Control

SLEEP

Posi tive Input

Negative Input

Posi tive Input

Negative Input

Channel 2

Channel 1

PGND

Charge Pump

5 V

Regulator

Digital PowerAnalog Power

Gate

Drive

Gate

Drive

Processing

and

Modulation

Channel 2

Positive Output

Negative Output

Channel 1

Positive Output

Negative Output

12 V

Processing

and

Modulation

CS3511

AUG ‘09

DS845PP2

CS3511

2DS845PP2

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................6

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

DC ELECTRICAL CHARACTERISTICS ....... .... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... .... ... ... ... ..... 8

DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 8

DIGITAL I/O PIN CHARACTERISTICS .. ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... .............. 9

3. TYPICAL CONNECTION DIAGRAMS .................................................................................................10

4. APPLICATIONS ................................................................................................................................... 12

4.1 CS3511 Input Stage ... .... ................ ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ................ ... ................ 12

4.2 Dynamic DC Offset Calibration ...................... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ............ 12

4.3 CS3511 Amplifier Gain ............... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ... ................ ................ 13

4.4 MUTE Pin .......................... ... ... .... ................ ... ... ... .... ................ ... ... ... ................. ... ... ...................... 13

4.5 SLEEP Pin .............. ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ................ ... ... .... ... ... ...................... 13

4.6 Power Up and Power Down Sequence ............. ................ ................ ................. ................ ............ 13

4.6.1 Recommended Power-Up Sequence .................................................................................... 13

4.6.2 Recommended Power-Down Sequence ............................................................................... 14

4.7 Protection Circuits ............. ... ................ ... .... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ...................... 14

4.7.1 Under-Voltage Protection ...................................................................................................... 14

4.7.2 Over-Temperature Protection ................................................................................................ 14

4.7.3 Over-Current Protection ........................................................................................................ 14

4.8 Integrated 5 V Regulator ................................................................................................................ 14

4.9 Power Dissipation De-Rating ......................................................................................................... 14

4.10 Performance Measurements of the CS3511 ................................................................................ 15

4.11 Full-Bridge Output Filter ............................................................................................................... 15

5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 16

5.1 Power Supply and Grounding ........................................................................................................ 16

5.1.1 Maximum Supply Voltage ...................................................................................................... 16

5.2 QFN Thermal Pad .......................... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ................ ... ................ 16

5.3 Layout Considerations ......................... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ............................ 16

6. TYPICAL AUDIO PERFORMANCE PLOTS ........................................................................................ 17

7. PARAMETER DEFINITIONS ................................................................................................................ 21

8. PACKAGE DIMENSIONS .................................................................................................................... 22

9. THERMAL CHARACTERISTICS ......................................................................................................... 23

9.1 Thermal Flag ........................... .... ... ... ... ... ................. ... ... ... .... ................ ... ... ... .... ... ......................... 23

10. ORDERING INFORMATIO N ....... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... .... ... ......... 24

11. REVISION HISTORY ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... .... ... ... ................ ... .... ... ... ... ................... 25

CS3511

DS845PP2 3

LIST OF FIGURES

Figure 1.Typical Connection Diagram - Stereo Amplifier with Differential Inputs ...................................... 10

Figure 2.Typical Connection Diagram - Stereo Amplifier with Single-Ended Inputs ................................. 11

Figure 3.CS3511 Input Stage .................................................................................................................... 12

Figure 4.Output Filter ................................................................................................................................ 15

Figure 5.THD+N vs. Output Power (RL= 8 W) .......................................................................................... 17

Figure 6.THD+N vs. Output Power (RL= 6 W) .......................................................................................... 17

Figure 7.THD+N vs. Output Power (RL= 8 W) .......................................................................................... 17

Figure 8.THD+N vs. Output Power (RL= 6 W) .......................................................................................... 17

Figure 9.THD+N vs. Output Power (RL= 8 W) .......................................................................................... 17

Figure 10.THD+N vs. Output Power (RL= 6 W) ........................................................................................ 17

Figure 11.Supply Current vs. POUT (RL= 8 W) ........................................................................................ 18

Figure 12.Supply Current vs. POUT (RL= 6 W) ........................................................................................ 18

Figure 13.THD+N vs. Frequency (RL= 8 W) ............................................................................................. 18

Figure 14.THD+N vs. Frequency (RL= 6 W) ............................................................................................. 18

Figure 15.Frequency Response (POUT = 1 W, RL= 8 W) ........................................................................ 18

Figure 16.Frequency Response (POUT = 1 W, RL= 6 W) ........................................................................ 18

Figure 17.Crosstalk vs. Frequency (RL= 8 W) .......................................................................................... 19

Figure 18.Crosstalk vs. Frequency (RL= 6 W) .......................................................................................... 19

Figure 19.Output FFT (POUT = 1 W, RL= 8 W) ........................................................................................ 19

Figure 20.Output FFT (POUT = 1 W, RL= 6 W) ........................................................................................ 19

Figure 21.Output FFT (POUT = 5 W, RL= 8 W) ........................................................................................ 19

Figure 22.Output FFT (POUT = 5 W, RL= 6 W) ........................................................................................ 19

Figure 23.Efficiency (RL= 8 W) .... ... ... .... ................ ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ...................... 20

Figure 24.Efficiency (RL= 6 W) .... ... ... .... ................ ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ...................... 20

LIST OF TABLES

Table 1. I/O Power Rails ............................................................................................................................. 9

Table 2. Low-Pass Filter Components ... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................ ... .... ............ 15

CS3511

4DS845PP2

1. PIN DESCRIPTIONS

Pin Name #Pin Description

IN1+

IN1-

IN2+

IN2-

Differential Analog Input (Input) - Differential Audio Signal Inputs for channel 1 and channel 2.

V5D 2 Digita l Power (Input) - Supply for digital logic. Connect to 5VGEN.

GAIN0

GAIN1 3

22 Gain (Input) - Gain select bits. GAIN0 is the least significant bit.

DGND 4 Digital Ground (Input) - Ground reference for the internal logic and digital I/O.

REF 5 Reference (Output) - Internal reference voltage.

SLEEP 6 Sleep (Input) - When set to logic high, device enters low power mode. If not used, this pin should be

grounded.

MUTE 7 Mute (Input) - When set to logic high, both amplifiers are muted and in Idle Mode. When low

(grounded), both amplifiers are fully operational. If not used, this pin should be grounded.

STATUS 8

Status (Output) - A lo gic high output indicates over-current or under-voltage condition, thermal over-

load, that an output is shorted to ground or to another output, that the device is in low power mode (the

SLEEP pin is high), or that the device is in reset. A logic low st ate indicates that the CS3511 is ready to

output audio.

Thermal Pad

109

11 12 13 14 15 16

262728

303132

IN1-

IN2+

OUT1+

IN1+

Top-Down (Through Package) View

32-Pin QFN Package

PGND

OUT1-

OUT2-

PGND

OUT2+

V5D

GAIN0

DGND

REF

SLEEP

MUTE

STATUS

AGND

BIASCAP

V5A

AGND

IN2-

AGND

GAIN1

5VGEN

DCAP

CPUMP

PGND

CS3511

DS845PP2 5

OUT1+

OUT1-

OUT2+

OUT2-

Differential PWM Output (Output) - Differential PWM Outputs for channel 1 and channel 2.

VP 10

20 High Voltage Power (Input) - Supply pins for high current H-bridges.

PGND 11

17 Power Ground (Input) - High current ground for analog outputs.

CPUMP 18 Charge Pump Input (Input) - Input pin for charge pump.

DCAP 19 Charge Pump Switching Pin (Output) - Free-running 350 kHz square wave between VP and ground.

5VGEN 21 5 Volt Generator (Output) - Regulated 5 VDC source used to supply power to the input section (pins 2

and 28).

AGND 23

30 Analog Ground (Input) - Connect all pins together directly at the thermal pad of the CS3511.

IN2+

IN2- 24

25 Negative Analog Input (Input) - Negative Audio Signal for channel 2 and channel 1, respectively.

C1 26

31 Pop Minimization Capacitor (Input) - External capacitor used to reduce turn on/off pops.

V5A 28 Analog Power (Input) - Supply for analog circuitry. Connect to 5VGEN.

BIASCAP 29 Analog Input Bias (Input) - Input stage bias voltage.

Thermal Pad - Thermal Pad (Input) - Thermal reli ef pad for optimized heat dissipation. Connect to PGND. See “QFN

Thermal Pad” on page 16 for more information.

CS3511

6DS845PP2

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND = DGND = PGND = 0 V; All voltages with respect to ground. (Note 1)

Notes:

1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits

may adversely affect device reliability.

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = PGND = 0 V; All voltages with respect to ground.

WARNING:Operation at or beyond these limits may result in permanent damage to the device.

Notes:

2. The outputs will stop switching at the VP Under-Voltage Error Falling Trigger Point. See “DC Electrical Char-

acteristics” on page 8.

3. Any pin except supplies. Transient currents of up to ±100 mA on the INxx pins will not cause SCR latch-up.

4. The maximum over/under voltage is limited by the input current.

Parameters Symbol Min Typ Max Units

DC Power Supply

Supply Voltage VP 8.5 12 13.2 V

Temperature

Ambient Temperature TA-10 - +70 °C

Junction Temp erature TJ-10 - +150 °C

Parameters Symbol Min Max Units

DC Power Supply

Outputs Switching and Under Load (Note 2) VP - 13.2 V

No Output Switching VP -0.3 14.0

Inputs

Input Current (Note 3) Iin -±10mA

Digital Input Voltage (Note 4) VIND -0.3 V5D + 0.3 V

Temperature

Ambient Operating Temperature (power applied) TA-20 +85 °C

Sto r age Temperature Tstg -65 +150 °C

CS3511

DS845PP2 7

AC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground;

TA= 25°C; VP = 12 V; RL=8Ω full-bridge; GAIN1 = 0, GAIN0 = 1; 10 Hz to 20 kHz Measurement Bandwidth; Per-

formance measurements taken with a differential 997 Hz sine wave and AES17 measurement filter; Stereo Full-

Bridge measurements taken through the Full-Bridge Output Filter shown in Figure 4 on page 15.

Notes:

5. See Figure 5 on page 17.

6. dBi is referenced to the input signal amplitude resulting in the specified output power at THD+N<1%. See

“Parameter Definitions” on page 21 for more information.

7. See Section 4.2 “Dynamic DC Offset Calibration” on page 12.

Parameters Symbol Test Conditions Min Typ Max Units

Output Power (Continuous Average/Channel)

(Note 5)

THD+N = 1% RL = 8 Ω

RL = 6 Ω

-7.5

9.1 -

-W

THD+N = 7% RL = 8 Ω

RL = 6 Ω

-8.8

10.8 -

-W

THD+N = 10% RL = 8 Ω

RL = 6 Ω

-9.4

11.4 -

-W

Total Harmonic Distortio n + Noise (Note 5) THD+N PO = 1 W, RL = 8 Ω

PO = 5 W, RL = 8 Ω -

-0.019

0.025 -

Dynamic Range (Note 6) DYR Vin = -60 dBi A-Weighted

Unweighted -

-99

96 -

-dB

Signal to Noise Ratio (Note 6) SNR Inputs AC coupled to AGND

A-Weighted

Unweighted -

-99

96 -

-dB

Power Supply Rejection Ratio PSRR 200 mv p-p from

20 Hz ≤f≤1 kHz, inputs AC

coupled to AGND -55-dB

IHF Intermodulation Distortion IHF-IMD 19 kHz, 20 kHz, 1:1 (IHF),

PO = 1 W -0.20-%

Channel Separation CS PO=1 W, f = 1 kHz

20 Hz ≤ f ≤ 20 kHz -

-104

78 -

-dB

Output Offset Voltage (Note 7) VOFFSET MUTE = low -50-mV

Efficiency ηPO = 2 x 9.4 W, RL = 8 Ω-85-%

PWM Output Over-Current Error Trigger Point ICE -2.7-A

Junction Thermal Error Rising Trigger Point TTERISE -155-°C

Junction Thermal Error Falling Trigger Point TTEFALL -135-°C

Turn On Time ton SLEEP = VIL -155-ms

Turn Off Time toff SLEEP = VIH -3-ms

Amplifier Gain Gain1 = 0, Gain0 = 0 - 13.6 - dB

Gain1 = 0, Gain0 = 1 - 19.5 - dB

Gain1 = 1, Gain0 = 0 - 23.8 - dB

Gain1 = 1, Gain0 = 1 - 27.3 - dB

Gain Matching Between output channels - 0.1 - %

Input Impedance Gain1 = 0, Gain0 = 0 36.8 46.0 55.2 kΩ

Gain1 = 0, Gain0 = 1 18.4 23.0 27.6 kΩ

Gain1 = 1, Gain0 = 0 11.0 13.8 16.6 kΩ

Gain1 = 1, Gain0 = 1 7.3 9.2 11.1 kΩ

CS3511

8DS845PP2

DC ELECTRICAL CHARACTERISTICS

Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground;

TA= 25°C; VP = 12 V; RL=8Ω full-bridge; GAIN1 = 0, GAIN0 = 1; Stereo Full-Bridge measurements taken

through the Full-Bridge Output Filter shown in Figure 4 on page 15.

DIGITAL INTERFACE SPECIFICATIONS

AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified.

Notes:

8. Levels between VIH and VIL are invalid. The transition period between VIH and VIL should not exceed tI.

Parameters Symbol Test Conditions Min Typ Max Units

Sleep Supply Current ICC(sleep)

SLEEP = VIH -5.2-mA

SLEEP = VIH; no load, filter , or

snubber -5.2-mA

Mute Supply Current ICC(mute)

MUTE = VIH -38-mA

MUTE = VIH; no load, filter, or

snubber -38-mA

Quiescent Current

ICC

VIN = 0 V; SLEEP = VIL,

MUTE = VIL

-68-mA

VIN = 0 V; SLEEP = VIL,

MUTE = VIL; no load, filte r, or

snubber

-85-mA

MOSFET On Resistance (each FET) RDS(ON) Id= 0.5 A, TJ=50°C - 325 - mΩ

5VGEN Nominal Voltage - 5.2 - V

5VGEN DC current source - - 70 mA

REF Nominal V oltage -1.2 -V

BIASCAP Nominal Voltage - 2.5 - V

VP Under-Voltage Error Falling Trigger Point VUVVPFALL -7.56-V

VP Under-Vol tage Error Rising Trigger Point VUVVPRISE -8.08-V

V5A Under-Voltage Error Falling Trigger Point VUV5VFALL -4.1-V

V5A Under-Voltage Error Rising Trigger Point VUV5VRISE -4.3-V

Charge Pump Under-Vo ltage Error Falling

Trigger Point VUVCPFALL - 1.55*VP -

Charge Pump Under-Vo ltage Error Rising

Trigger Point VUVCPRISE - 1.62*VP -

Parameters Symbol Min Max Units

High-Level Input Voltage (MUTE, SLEEP) (Note 8) VIH V5D - 2 - V

High-Level Input Vol tage (GAIN1, GAIN0) VIH V5D - 0.8 - V

Low-Level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0) (Note 8) VIL -1V

Transition Time Between VIH and VIL (MUTE, SLEEP) (Note 8) tI- 500 ns

High-Level Output Voltage (STATUS) IO=250μAVOH V5D - 0.5 - V

Low-Level Output Voltage (STATUS) IO=250μAVOL -0.5V

Input Leakage Current (MUTE, SLEEP) Iin -±10μA

Input Leakage Current (GAIN1, GAIN0) Iin -±300μA

CS3511

DS845PP2 9

DIGITAL I/O PIN CHARACTERISTICS

The logic level for each input is set by its corresponding power supply and sh ould not exceed the ma ximum ratings.

Power

Supply Pin

Number Pin Name I/O Driver Receiver

5VD

3 GAIN0 Input - 5.0 V; Internal 50 kΩ pull-down

22 GAIN1 Input - 5.0 V; Internal 50 kΩ pull-down

7 MUTE Input - 5.0 V

6 SLEEP Input - 5.0 V

8 STATUS Output 5.0 V -

35 OUT1+ Output 8.5 V - 13.2 V Power MOSFET -

32 OUT1- Output 8.5 V - 1 3.2 V Power MOSFET -

29 OUT2+ Output 8.5 V - 13.2 V Power MOSFET -

26 OUT2- Output 8.5 V - 1 3.2 V Power MOSFET -

Ta ble 1. I/O Power Rails

CS3511

10 DS845PP2

3. TYPICAL CONNECTION DIAGRAMS

Figure 1. Typical Connection Diagram - Stereo Amplifier with Differential Inputs

OUT1+

OUT1-

1IN1+

32 IN1-

1.0 µf

Differential

Analog Input s

Note(R1=R2)

GAIN0

6SLEEP

GAIN1

MUTE

8STATUS

27 AGND

System

Control

Logic

1.0 µf

24 IN2+

25 IN2-

1.0 µf

28 V5A

31 C1

26 C2

29 BIASCAP

30 AGND

18 CPUMP

19 DCAP

20 VP

21 5VGEN

23 AGND

2V5D

5REF

4DGND

1.0 µf 0.1 µf

0.1 µf 0.1 µf

1 µf 20 KΩ

0.1 µf

220uF

0.1 µf

OUT2+

OUT2-

PGND

CS3511

1 µf 10 µf 10 µf 1 µf

PGND

Full-Bridge

Output Filter RL

Channel 1

Audio Output

Full-Bridge

Output Filter RL

Channel 2

Audio Output

Differential

Analog Inputs

Note(R3=R4) 6 Ω to 8 Ω

6 Ω to 8 Ω

220 uF

PGND

(Note 1)

1. See Section 4.11 for typical full-bridge output filter.

2. Incorrectly connecting the external charge pump circu itry can result in permanent damage to the device.

(Note 2)

CS3511

DS845PP2 11

Figure 2. Typical Connection Diagram - Stereo Amplifier with Single-Ended Inputs

OUT1+

OUT1-

1IN1+

32 IN1-

1.0 µf

Single-Ended

Analog Input

Note(R1=R2)

GAIN0

6SLEEP

GAIN1

MUTE

8STATUS

27 AGND

System

Control

Logic

1.0 µf

24 IN2+

25 IN2-

1.0 µf

28 V5A

31 C1

26 C2

29 BIASCAP

30 AGND

18 CPUMP

19 DCAP

20 VP

21 5VGEN

23 AGND

2V5D

5REF

4DGND

1.0 µf 0.1 µf

0.1 µf 0.1 µf

1 µf 20 KΩ

0.1 µf

VP 220 uF

0.1 µf

VP 220 uF

OUT2+

OUT2-

PGND

CS3511

1 µf 10 µf 10 µf 1 µf

PGND

Full-Bridge

Output Filter RL

Channel 1

Audio Output

Full-Bridge

Output Filter RL

Channel 2

Audio Output

Single-Ended

Analog Input

Note(R3=R4) 6 Ω to 8 Ω

6 Ω to 8 Ω

PGND

Important: See (Note 3)

1. See Section 4.11 for typical full-bridge output filter.

2. Incorrectly connecting the external charge pump circu itry can result in permanent damage to the device.

3. See Sec tio n 4. 1 for important information regarding using Single-Ended inputs with the CS3511.

(Note 1)

(Note 2)

CS3511

12 DS845PP2

4. APPLICATIONS

4.1 CS3511 Input Stage

The input stage of the CS3511 is configured as a differ ential r eceiver to maximize co mmon-m ode reje ction

in typical audio circuits. To maximize this benefit, the INx+ and INx- pins should be driven with differential

signals from sources that have the same output impedance. Also, the signals should be routed parallel to

one another from their source to the analog inputs of the CS3511.

In some instances, there will be a necessity to drive the CS3511 with a single-ended input signal. In this

case, the unused input should be AC coupled to ground using the same value of CI implemented for the

driven channel. Either input, INx+ or INx-, can be used for the signal input. To mi nimize the effects of ground

noise in the system, CI should be terminated at the ground connection through a resistor, RI. Please refer

to Figure 3. The value of the resistor should match the output impedance of the audio source.

Figure 3. CS3511 Input Stage

4.2 Dynamic DC Offset Calibration

Abrupt changes in DC output offset level are a known cause of audi ble turn-on and tur n-off pops. Typically,

when a system turns on (begins switching), the potent ial across th e speake r changes a bruptly from 0 V to

the steady-state DC offset voltage of the system. Similarly, when the system turns off, the potential changes

abruptly from the steady-state DC offset voltag e to 0 V. These abrupt changes are heard as a pop.

The CS3511 employs a patented method for reducing this pop. Immediately before the outputs begin to

switch, a calibration circuit dynamically minimizes the amplifier’s internal offsets. With these offsets at a min-

imum, the outputs begin to switch and the CS3511 begins to slowly ramp the DC output offse t potential to

the steady-state DC offset voltage. This ramp is slow enough to keep the speaker movement in the subsonic

range. Durin g turn-off, this procedure is rever sed. The static DC offset voltag e is ramped down to a dynam-

ically minimized DC offset level before output switching is stopped.

Dynamic offset cancellatio n requires equal impedan ces on the positive and negative inputs. If a single-end-

ed audio source with a 600 Ω output impedance is connected to the IN1+ (through a DC blocking capacitor),

IN1- must be terminated to ground with a 600 Ω resistor (also through a DC blocking capacitor. (See

Figure 3).

Audio Source CS35 11

INx-

RI = ZOUT

INx+

ZOUT

CS3511

DS845PP2 13

4.3 CS3511 Amplifier Gain

The closed-loop gain of the CS3511 is externally configured via two input pins, GAIN0 and GAIN1. The “AC

Electrical Characteristics” on page 7 shows the four different gain values a vailable based o n the pin voltag-

es at GAIN0 and GAIN1. Th e GAIN0 a nd GAIN1 in put pi ns have weak internal pu ll-down resistors; so they

should be driven high when set to a logic high. Internally, different input resistor values are used to imple-

ment the four gain settings. Thus, the input impedance will change based on the gain setting. The gain track-

ing is very tightly matched within each device, but the absolute input impedance will vary due to process

variations. This variation must b e considered when ch oosing the proper value of CI. The low-frequency roll-

off characteristic is dedicated by the choice of CI and RI.

The -3 dB frequency is:

On the CRD3511, a valu e of 1.0 µF is used for CI; this value provides a nearly flat response down to 2 0 Hz,

even for the highest gain setting. In many cases, a lower value of CI can be used due to a lower ga in setting

or because the speakers used do not have the ability to reproduce low-frequency signals.

4.4 MUTE Pin

The MUTE pin must be dr iven to a logic low or logic high sta te for proper oper ation. To enable the amplifier,

connect the MUTE pin to a logic low. To enable the mute function, connect the MUTE pin to a logic high

signal.

When in mute, the internal processor bias voltages remain active in the CS3511. This state maintains the

bias on the input coupling capacitor to prevent audible transients which would be caused by the charging

and discharging of this capacitor. It is recommended that the MUTE pin be held high during power-up or

power-down to eliminate audible transients.

If power-up and/or power-down pops are present with a CS3511 amplifier, th e cause may be othe r circuitry

external to the CS3 511 , su ch as a n aud io p ro cesso r o r pre amp. If th e CS35 11 is in the active state ( MUTE

pin is low), these audible pops will be amplified and output to the speakers. To eliminate this problem, acti-

vate the MUTE pin before the power supply collap ses during a power-down sequence.

4.5 SLEEP Pin

When pulled high, the SLEEP pin puts the device into a low quiescent current mode. To disable sleep mode,

the SLEEP pin should be grounded. While the device is in low power mode the STATUS pin will be in a logic

high state to indicate that the device is not ready to produce audio.

4.6 Power Up and Power Down Sequence

To minimize power-on and power-off transients, the device should be held in the MUTE state while powering

up or powering down the CS3511. The SLEEP pin can be held in either the logic high state or logic low state

during power- up or po we r- do wn .

4.6.1 R ecommended Power-Up Sequence

1. Apply power to the system.

2. Hold the MUTE pin in the logic high state until the power supply is stable. In this state, all associated

outputs are held in a high-impedance state.

3. Set the MUTE pin to a logic low sta te to begi n normal ope ration. If the SLEEP pin is held high during

power-on (optional), it should be set low before the MUTE pin is set low.

fc - 3 dB = 1

2π CI RI

CS3511

14 DS845PP2

4.6.2 R ecommended Power-Down Sequence

1. Set the MUTE pin to the logic high state. This will mute the amplifier outputs and hold them in a high-

impedance state.

2. Optionally, the SLEEP pin can now be set to a logic high state to place the device into low power

mode.

3. The powe r supplies can now be removed.

4.7 Protection Circuits

The CS3511 is protected against under-voltage, over-current, and over-temperature conditions. If one of

these fault conditions are present the amplifier will be muted, the outputs will be tri-stated, and the STATUS

pin will remain in a logic high state until the condition clears. The amplifier will automatically attempt to re-

cover from a detected fault condition.

4.7.1 Under-Voltage Protection

An under-voltage fault occurs if the voltage sensed on the VP terminals, the charge pump, or on V5A

drops below the corresponding falling trigger point seen in the DC Electrical Characteristics table. The

under-voltage fault will automatically clear once the voltage exceeds the associated rising trigger point.

V5GEN, V5A, and V5D must be connected together in order to properly monitor V5D and V5GEN. (See

Figure 1 and Figure 2).

4.7.2 Over-Temperature Protection

An over-temperature fault occurs if the junction temperature of the device exceeds the rising junction ther-

mal error trigger point seen in th e AC Electrical Characteristics table. The thermal hysteresis of the device

will cause the fault to automatically clear when the junction temperature drops below the falling junction

thermal error trigger point.

4.7.3 Over-Current Protection

An over-current fault occurs if more current than the over-current error trigger point flows from any of the

amplifier output pins, see AC Electrical Characteristics. Over current can occur if the speaker wires are

shorted together, if one side of the speaker is shorted to gr ound, or if the speaker impedance is too low.

WARNING: The outputs of the CS3511 sh ould never be shorted to VP. Doing so can result in p ermanent

damage to the de vice .

4.8 Integrated 5 V Regulator

The CS3511 includes an in ternal 5 V regulator in order to provide a sup ply to the internal digital an d analog

circuitry. The output of the regulator is present on the 5VGEN pin. The regulator output pin should have a

bypass capacitor connected to AGND and be connected to the digital and analog supply pins a s sh own in

the Typical Connection Diag rams in Section 3. The r egulator ou tput can be used to set the SLEEP, MUTE,

GAIN0, an d GAIN1 p ins to a lo gic high st ate. T he regulator is able to source the maximum current shown

in the DC Electrical Characteristics table.

4.9 Power Dissipation De-Rating

As a result of high-efficiency and good package thermal characteristics, the CS3511 can operate at elevated

ambient temperatures without having to de-rate the output power, assuming 8 Ω output loads or higher. The

exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability

of the CS3511 package. Soldering will minimize the likelihood of an over-temperature fault occurring during

CS3511

DS845PP2 15

continuous heavy load conditio ns. There should be vias for connecting the exposed p ad to the copper a rea

on the printed circuit board. The pad must be electrically connecte d to PGND. See Section 5.2 for more in-

formation on the thermal pad and Section 9.1 for more information on ther mal dissipation for the CS3511.

4.10 Performance Measurements of the CS3511

The CS3511 operates by generating a high-frequency switching signal based on the audio input. This signal

is sent through a low-pass filter (external to the CS3511 amplifier) that reco ve rs an ampl ifie d version of th e

audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100 kHz

and 1.0 MHz, which is well above the 10 Hz – 20 kHz audio band. The pattern itself does not alter or distort

the audio input signal, but it doe s introduce some inaudible components outside of the audio band.

The measurements of certain performance parameters, particularly noise-related specifications such as

THD+N, are significantly affected by the design of the low- pass filter used on the output as we ll as the band-

width setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the

audio band or the bandwidth of the measurement instrument is limited, some of the inaudible components

introduced by the CS3511 amplifier’s switching pattern will degrade the measurement result.

One feature of the CS3511 is that it does not require large multi-pole filters to achieve excellent performance

in listening tests, usua lly a more critical factor than pe rforman c e measur eme nts. The CRD35 11 Eva luatio n

Board uses the filter described in Section 4.11, which has a simple two-pole outpu t filter and excellent per-

formance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited

bandwidth setting in the measurement instrument.

4.11 Full-Bridge Output Filter

Figure 4 shows the output filter for a full-bridge configuration. The transient-voltage suppression circuit

(snubber circuit) is comprised of a resistor (5.6 Ω) and capacitor (680 pF) and should be placed as close

as possible to the correspondi ng PWM output pins to gre atly reduce radia ted EMI. The inductors, L1 an d

L2, and capacitor, C1, comprise the low-pass filter. Along with the nominal load impedance of the speaker,

these values set the cutoff freque ncy of the filter. Table 2 sh ows the component values base d on nominal

speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz.

Load L1, L2 C1

8Ω22 µH 0.47 µF

6Ω15 µH 0.47 µF

Table 2. Low-Pass Filter Components

OUTx+

OUTx-

680 pF

5.6 Ω

680 pF

Figure 4. Output Filter

CS3511

16 DS845PP2

5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT

5.1 Power Supply and Grounding

The CS3511 requires careful attention to power supply and grounding arrangements if its potential perfor-

mance is to be realized.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. It is necessary to de-couple the power supply by placing capacitors directly

between the power and grou nd of the CS351 1. Decoupling capa citors sh ould be as close to the pin s of the

CS3511 as possible. The lowest valu e ceramic capacitor sh ould be closest to the pin an d should be moun t-

ed on the same side of the board as the CS3511 to minimize inductance effects. The CRD3511 reference

design demonstrates the optimum layout and power supply arrangements.

5.1.1 M aximum Supply Voltage

The absolute maximum allowable voltage on the VP supply pins (pins 10, 15 and 20) is shown in the Ab-

solute Maximum Ratings table. De vice damage can occur ab ove this volta ge. Please note th at the abso-

lute maximum voltage does not represent a valid operating condition. The maximum voltage on the VP

pins during operation is shown in the Recommended Operating Conditions table.

During normal oper ation, the o utput pins (pins 9, 12 , 13, and 16) may exp erience overshoot voltages du e

to inductive kickback. Care should be taken to properly de-couple the VP pins becau se over shoot on th e

output pins can travel through the CS3511 output devices and appear on the VP pins. Without proper

power supply decoupling, this can cause ripple voltages on the VP pins that might exceed their absolute

maximum voltage shown in the Absolute Maximum R atings table. However, this will only happen in ex-

treme cases and can be prevented by placing the high-frequency decoup ling cap acitors c lose t o the VP

pins.

5.2 QFN Thermal Pad

The CS3511 is available in a compact QFN package. The underside of the QFN package reveals a large

metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with

an equally dimensioned copper pad on the PCB and must be electrically connected to PGND. A series of

thermal vias should be us ed to connect this co ppe r pad to o ne or more larger gr ound p lane s on oth er PCB

layers; the copper in these ground planes will act as a heat sink for the CS3511. The CRD3511 reference

design demonstrates the optimum thermal pad an d via configuration.

5.3 Layout Considerations

The CS3511 is a power (high current) amplifier that operates at relatively high switching frequencies. The

outputs of the amplifier switch be tween the supply voltage and ground, at high speeds, while driving high

currents. This high-frequen cy digital signa l is passed through an LC low-pass filter to recover the amplified

audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier

outputs can be pulled above the supply voltage and below ground by the energy in the output inductance.

Additionally, the CS3511’s junction temper ature rises when supplying power to loads and relies on the PCB

for heat sinking.

To avoid subjecting the CS3511 to potentially damaging voltage stress and output-power-limiting elevated

junction temperatures, it is critical to have a good printed circuit board layout. It is strongly recommended

that the Cirrus CRD3511 layout be used fo r all applications and only be deviated from after careful analysis

of the effects of any changes. Please refer to Cirrus Logic application note AN315 for further information

regarding the layout of the CS3511.

CS3511

DS845PP2 17

6. TYPICAL AUDIO PERFORMANCE PLOTS

Test Conditions (unless otherwise specified): All plots were taken using the CRD3511 Reference Design Board

sourced with a differential input; TA= 25°C; 10 Hz to 20 kHz Measurement Bandwidth; Performance measurements

taken with a 997 Hz sine wave and AES17 measurement filter; GAIN1 = 0, GAIN0 = 1; VP = 12 VDC.

0.01

0.02

0.05

0.1

0.2

0.5

10m 2020m 50m 100m 200m 500m 1 2 5 10

0.01

0.02

0.05

0.1

0.2

0.5

10m 2020m 50m 100m 200m 500m 1 2 5 10

Figure 5. THD+N vs. Output Power (RL= 8 Ω) Figur e 6. THD+N vs. Output Power (RL= 6 Ω)

9.0 V

12.0 V

9.0 V

12.0 V

0.007

0.01

0.02

0.05

0.1

0.2

0.5

10m 2020m 50m 100m 200m 500m 1 2 5 10

0.007

0.01

0.02

0.05

0.1

0.2

0.5

1m 202m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10

Figure 7. THD+N vs. Output Power (RL= 8 Ω) Figure 8. THD+N vs. Output Power (RL= 6 Ω)

100 Hz 1 kHz

10 kHz

100 Hz 1 kHz

10 kHz

0.01

0.02

0.05

0.1

0.2

0.5

10m 2020m 50m 100m 200m 500m 1 2 5 10

0.01

0.02

0.05

0.1

0.2

0.5

10m 2020m 50m 100m 200m 500m 1 2 5 10

Figure 9. THD+N vs. Output Power (RL= 8 Ω) Figure 10. THD+N vs. Output Power (RL= 6 Ω)

GAIN=11

GAIN=10

GAIN=00

GAIN=11

GAIN=10

GAIN=01 GAIN=01

CS3511

18 DS845PP2

0.5

1.5

2.5

02468101214161820

Total Output Power (Watts)

Supply Current (A)

0.5

1.5

2.5

02468101214161820

Total Output Power (Watts)

Supply Current (A)

Figure 11. Supply Current vs. POUT (RL= 8 Ω) Figure 12. Supply Current vs. POUT (RL= 6 Ω)

Figure 13. THD+N vs. Freq uency (RL= 8 Ω) Figure 14. THD+N vs. Frequency (RL= 6 Ω)

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

20 20k50 100 200 500 1k 2k 5k 10k

0.5 W

1.0 W 5.0 W

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

20 20k50 100 200 500 1k 2k 5k 10k

0.5 W

1.0 W 5.0 W

-5

-4

-3

-2

-1

-0

20 20k50 100 200 500 1k 2k 5k 10k

-5

-4

-3

-2

-1

-0

20 20k50 100 200 500 1k 2k 5k 10k

Figure 15. Frequency Response (POUT = 1 W, RL= 8 Ω) Figure 16. Frequenc y Response (POUT = 1 W, RL= 6 Ω)

See Note below.

Note: The full-bridge output filter found on the CRD3511 reference design board implements 22µH inductors

and is optimized for an 8 Ω load.

CS3511

DS845PP2 19

Figure 17. Cro s sta lk vs. Frequency (RL= 8 Ω) Figure 18 . Cr os stalk vs. Fre quency (RL= 6 Ω)

-140

-40

-120

-100

-80

-60

20 20k50 100 200 500 1k 2k 5k 10k

CH1 to CH2

CH2 to CH1

-140

-40

-120

-100

-80

-60

20 20k50 100 200 500 1k 2k 5k 10k

CH1 to CH2

CH2 to CH1

Figure 19. Output FFT (POUT = 1 W, RL= 8 Ω) Figure 20. Output FFT (POUT = 1 W, RL= 6 Ω)

-140

+20

-120

-100

-80

-60

-40

-20

20 20k50 100 200 500 1k 2k 5k 10k

-140

+20

-120

-100

-80

-60

-40

-20

20 20k50 100 200 500 1k 2k 5k 10k

Figure 21. Output FFT (POUT = 5 W, RL= 8 Ω) Figure 22. Output FFT (POUT = 5 W, RL= 6 Ω)

-140

+20

-120

-100

-80

-60

-40

-20

20 20k50 100 200 500 1k 2k 5k 10k

-140

+20

-120

-100

-80

-60

-40

-20

20 20k50 100 200 500 1k 2k 5k 10k

CS3511

20 DS845PP2

100

012345678910

Output Power Per Channel (Watts)

Efficiency (%)

100

012345678910

Output Power Per Channel (Watts)

Efficiency (%)

Figure 23. Efficiency (RL= 8 Ω) Figure 24 . Effici ency (RL= 6 Ω)

CS3511

DS845PP2 21

7. PARAMETER DEFINITIONS

Signal to Noise Ratio (SNR)

The ratio of the RM S value of the output si gnal, where Pout is equivalent to the specified output power at

THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the spec-

ified bandwidth, typically 20 Hz to 20 kHz. Expressed in decibels.

Dynamic Range (DYR)

The ratio of the RMS value of the output signal produced when Pout is equivalent to the specified output

power at THD +N<1% to the RMS sum of a ll oth e r spectral compone nt s ov er th e sp ec ifie d b an dw idt h, ty p i-

cally 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement made with a -60 dBi input

signal where dBi is referenced to the input signal amplitude resulting in the specified output power at

THD+N<1%. This technique ensures that the distortion components are below the noise level and do not

effect the measurement. Expressed in decibels.

Total Harmonic Distortion + Noise (THD+N)

The ratio of the RMS value o f the signal to the RMS sum of all other sp ectral components over the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

CS3511

22 DS845PP2

8. PACKAGE DIMENSIONS

1. Dimensioning and tolerance per ASME Y 14.5M-1994.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.25 mm and 0.30 mm

from the terminal tip.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A 0.031 0.033 0.035 0.80 0.85 0.90 1

A1 0.00 -- 0.05 0.00 -- 0.05 1

A3 - 0.008 REF - - 0.203 REF -

b 0.008 0.010 0.012 0.20 0.25 0.30 1,2

D - 0.2362 BSC - - 6.00 BSC - 1

D2 0.177 0.181 0.185 4.50 4.60 4.70 1

E 0.2362 BSC 6.00 BSC 1

E2 0.177 0.181 0.185 4.50 4.60 4.70 1

e 0.026 BSC 0.65 BSC 1

L 0.014 0.016 0.018 0.35 0.40 0.45 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Side View

Bottom View

Top View

Pin #1 Corner

be Pin #1 Corner

32L QFN (6 X 6 mm BODY) PACKAGE DRAWING

CS3511

DS845PP2 23

9. THERMAL CHARACTERISTICS

9.1 Thermal Flag

This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane

on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be cou-

pled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB.

In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those

immediately surrounding the CS3511. In addition to improving in electrical performance, this practice also

aids in heat dissipation.

The heat dissipation capability required of the metal plane for a given output power can be calculated as

follows:

θCA = [(TJ(MAX) - TA) / PD] - θJC

where,

θCA = Thermal resistance of the metal plane in °C/Watt

TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C

TA = Ambient temperature in °C

PD = RMS power dissipation of the device, equal to 0.176*PRMS-OUT (assuming 85% efficiency)

θJC = Junction-to-c ase thermal resista n ce of the device in °C/Watt, equal to 1 °C/Watt

Parameter Symbol Min Typ Max Units

Junction to Case Thermal Impedance θJC -1-°C/Watt

CS3511

24 DS845PP2

10.ORDERING INFORMATION

Product Description Package Pb-Free Grade Temp Range Container Order#

CS3511 S tereo, 10W High-Efficiency

Class-D Audio Amplifier 32-QFN Yes Commercial -10° to +70°C Rail CS3511-CNZ

Tape and

Reel CS3511-CNZR

CRD3511-Q1 2x10W, 4Layer / 1oz.

Copper Reference Design - - - - - CRD3511-Q1

CS3511

DS845PP2 25

11.REVISION HISTORY

Release Changes

A1 Initial Release

A2 – Updated cover diagram.

– R emoved Dynamic Output Offset Voltage specification.

– Updated Section 4.2 on page 12.

A3 – Updated PWM Output Over-Current specification in “AC Electrical Characteristics” table on page 7 and

in the General Descripti on on the front page.

– F AULT pin (8) name updated to STATUS.

– Updated Section 4.7 on page 14.

– Updated “Under-Voltage Protection” table on page 14 and “DC Electrical Characteristics” table on

page 8 from V5GEN to V5A for 5 V voltage sensing.

– U pdated Input Impedance specification in “AC Electrical Characteristics” table on page 7.

PP1 – Updated front page Features and Common Applications.

– Updated DC Power Supply specification in “Absolute Maximum Ratin gs” table on page 6.

– Updated THD+N, Dynamic Range, SNR, PSRR, Channel Separation, Amplifier Gain, Gain Match ing,

and Efficiency specifications in “AC Ele ctrical Characteristics” table on pag e 7.

– U pdated Sleep Supply Current, Mute Supply Current, Quiescent Current, 5VGEN Nominal Voltage,

REF Nominal Voltage, and BIASCAP Nominal Voltage in “DC Electrical Characteristics” table on

page 8.

– Updated Leakage Current specification in “Digital Interface Specifications” table on page 8.

– Updated the typical audio performance plots in Section 6.

PP2 – Added SLEEP and MUTE pin transition time specification and in formation to the “DC Electrical

Characteristics” table on page 8.

– Added Section 4.6, Section 4.6.1, and Section 4.6.2.

– Updated the typical audio performance plots in Section 6.

– U pdated Input Impedance specifications in “AC Electrical Characteristics” table on pa ge 7.

– Updated front page Features, “AC Electrical Charac teristics” table on page 7, and Section 4.3 to

reference four GAIN settings.

CS3511

26 DS845PP2

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

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is provi ded “AS IS” withou t warranty of any kind (expre ss or implied). Customers are advi sed to obtain t he latest ver sion of relevant information to verify, before

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