ICS85311AMILFT - Integrated Device Technology

DATA SHEET

Low Skew, 1-to-2, Differential-to-LVPECL/ECL

Fanout Buffer

ICS85311I

General Description

The ICS85311I is a low skew, high performance 1-to-2

Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer

and a member of the HiPerClockS™ family of High

Performance Clock Solutions from IDT. The CLK,

nCLK pair can accept most standard differential input

levels.The ICS85311I is characterized to operate from either a 2.5V

or a 3.3V power supply. Guaranteed output and part-to-part skew

characteristics make the ICS85311I ideal for those clock distribution

applications demanding well defined performance and repeatability.

Features

•Two differential 2.5V/3.3V LVPECL / ECL outputs

•One CLK, nCLK input pair

•CLK, nCLK pair can accept the following differential input levels:

LVDS, LVPECL, LVHSTL, SSTL, HCSL

•Maximum output frequency: 1GHz

•Translates any single ended input signal to 3.3V LVPECL levels

with resistor bias on nCLK input

•Output skew: 20ps (maximum)

•Part-to-part skew: 350ps (maximum)

•Propagation delay: 2.1ns (maximum)

•Additive phase jitter, RMS: 0.14ps (typical), 3.3V

•LVPECL mode operating voltage supply range:

VCC = 2.375V to 3.465V, VEE = 0V

•ECL mode operating voltage supply range:

VCC = 0V, VEE = -2.375V to -3.465V

•-40°C to 85°C ambient operating temperature

•Available in lead-free (RoHS 6) package

HiPerClockS™

ICS

nQ0

nQ1

CLK

nCLK Pullup

Pulldown

VCC

CLK

nCLK

VEE

nQ1

nQ0

ICS85311I

8-Lead SOIC

3.90mm x 4.903mm x 1.37mm package body

M Package

Top View

Pin Assignment

Block Diagram

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels.

3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels.

EE Power Negative supply pin.

6 nCLK Input Pullup Inverting differential clock input.

7 CLK Input Pulldown Non-inverting differential clock input.

CC Power Positive supply pin.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C

Table 3B. Differential DC Characteristics, VCC = 3.3V±5% or 2.5V±5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode voltage is defined as VIH.

Item Rating

Supply Voltage, VCC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuos Current

Surge Current

50mA

100mA

Storage Temperature, TSTG -65°C to 150°C

Package Thermal Impedance, θJA 103°C/W (0 lfpm)

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Positive Supply Voltage 3.135 3.3 3.465 V

2.375 2.5 2.625 V

IEE Power Supply Current 25 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current nCLK VCC = VIN = 3.465V or 2.625V 5 µA

CLK VCC = VIN = 3.465V or 2.625V 150 µA

IIL Input Low Current nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA

CLK VCC = 3.465V or 2.625V, VIN = 0V -5 µA

VPP

Peak-to-Peak Input Voltage;

NOTE 1 0.15 1.3 V

VCMR

Common Mode Input Voltage;

NOTE 1, 2 VEE + 0.5 VCC – 0.85 V

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Table 3C. LVPECL DC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs terminated with 50Ω to VCC – 2V.

Table 3D. LVPECL DC Characteristics, VCC = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs terminated with 50Ω to VCC – 2V.

AC Electrical Characteristics

Table 4A. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

All parameters are measured 500MHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Current; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Current; NOTE 1 VCC – 2.0 VCC – 1.7 V

VSWING Peak-to-Peak Output Voltage Swing 0.65 1.0 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Current; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Current; NOTE 1 VCC – 2.0 VCC – 1.5 V

VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Maximum Output Frequency 1GHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 1GHz 0.9 2.1 ns

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section

156.25MHz, Integration Range

(12kHz – 20MHz) 0.14 ps

tsk(o) Output Skew; NOTE 2, 4 20 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 350 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 300 700 ps

odc Output Duty Cycle 45 55 %

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Table 4B. AC Characteristics, VCC = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

All parameters are measured 500MHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Maximum Output Frequency 1GHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 1GHz 0.9 2.1 ns

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section

156.25MHz, Integration Range

(12kHz – 20MHz) 0.135 ps

tsk(o) Output Skew; NOTE 2, 4 25 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 250 700 ps

odc Output Duty Cycle 45 55 %

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Additive Phase Jitter (3.3V)

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

Offset Frequency (Hz)

SSB Phase Noise dBc/Hz

Additive Phase Jitter @ 156.25MHz

12kHz to 20MHz = 0.14ps (typical)

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information

3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit

Differential Input Level

Part-to-Part Skew

2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit

Output Skew

Propagation Delay

SCOPE

nQx

LVPECL

VEE

VCC

-1.3V ± 0.165V

VCMR

Cross Points

VPP

VCC

VEE

nCLK

CLK

tsk(pp)

Part 1

Part 2

nQx

nQy

SCOPE

nQx

LVPECL

VEE

VCC

-0.5V ± 0.125V

tsk(o)

nQx

nQy

tPD

nCLK

CLK

nQ[0:1]

Q[0:1]

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information, continued

Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VCC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 =

0.609.

Figure 1. Single-Ended Signal Driving Differential Input

nQ[0:1]

Q[0:1]

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

20%

80% 80%

20%

tRtF

VSWING

nQ[0:1]

Q[0:1]

V_REF

Single Ended Clock Input

VCC

CLK

nCLK

0.1u R2

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both VSWING and VOH must meet the VPP

and VCMR input requirements. Figures 2A to 2F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 2A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 2A. HiPerClockS CLK/nCLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 2C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

HiPerClockS

Input

125

3.3V

Zo = 50Ω

CLK

nCLK

3.3V

LVPECL HiPerClockS

Input

HCSL

*R3 33

*R4 33

CLK

nCLK

2.5V 3.3V

Zo = 50Ω

HiPerClockS

Input

*Optional – R3 and R4 can be 0Ω

CLK

nCLK

HiPerClockS

Input

LVPECL

3.3V

Zo = 50Ω

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50Ω

CLK

nCLK

HiPerClockS

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Recommendations for Unused Output Pins

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination

3.3V

VCC - 2V

50Ω

RTT

Zo = 50Ω

RTT = * Zo

((VOH + VOL) / (VCC – 2)) – 2

3.3V

LVPECL Input

84Ω

3.3V

125Ω

Zo = 50Ω

LVPECL Input

3.3V

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Termination for 2.5V LVPECL Outputs

Figure 4A and Figure 4B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating 50Ω

to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground

level. The R3 in Figure 4B can be eliminated and the termination is

shown in Figure 4C.

Figure 4A. 2.5V LVPECL Driver Termination Example

Figure 4C. 2.5V LVPECL Driver Termination Example

Figure 4B. 2.5V LVPECL Driver Termination Example

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

250

62.5

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

–

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS85311I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS85311I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW

• Power (outputs)MAX = 30mW/Loaded Output pair

If all outputs are loaded, the total power is 2 * 30mW = 60mW

Total Power_MAX (3.3V, with all outputs switching) = 86.6mW + 60mW = 146.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 103°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.147W * 103°C/W = 100.1°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 5. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection

θJA vs. Air Flow

Linear Feet per Minute 0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 103°C/W 94°C/W 89°C/W

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 5.

Figure 5. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of

VCC – 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCC_MAX – VOH_MAX) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V

(VCC_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

VOUT

VCC

- 2V

50Ω

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Reliability Information

Table 6. θJA vs. Air Flow Table for a 8 Lead SOIC

Transistor Count

The transistor count for ICS85311I is: 225

Package Outline and Package Dimensions

Package Outline - M Suffix for 8 Lead SOIC Table 7. Package Dimensions

Reference Document: JEDEC Publication 95, MS-012

θJA by Velocity

Linear Feet per Minute 0200500

Multi-Layer PCB, JEDEC Standard Test Boards 103°C/W 94°C/W 89°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.35 1.75

A1 0.10 0.25

B0.33 0.51

C0.19 0.25

D4.80 5.00

E3.80 4.00

e1.27 Basic

H5.80 6.20

h0.25 0.50

L0.40 1.27

α0° 8°

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Ordering Information

Table 8. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

85311AMILF 85311AIL “Lead-Free” 8 Lead SOIC Tube -40°C to 85°C

85311AMILFT 85311AIL “Lead-Free” 8 Lead SOIC 2500 Tape & Reel -40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

ICS85311I Data Sheet LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT

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