Evaluation Board Document
µPG2250T5N-ZBT-EV-A
Evaluation Board
o Circuit Description
o Typical Performance Data
o Circuit Schematic and Assembly Drawing
o Appendix: Evaluation Board Document of the uPG2250T5N-EVAL-A
uPG2214TB uPG2179TB
uPG2250T5N
RF IN
path 2 (thru)
path 1
RF OUT
Circuit Description:
This evaluation board provides a quick and convenient means of evaluating the performance of
the NEC uPG2250T5N power amplifier and two RF switches, uPG2214TB and uPG2179TB, for
a “range extension” application at 2.4GHz ISM band (such as for Bluetooth or ZigBee
applications). The circuit provides two paths for a transmit signal of a Bluetooth or Zigbee RF
transceiver: either through the amplifier or direct pass through two switches. The functional
diagram of this board is shown below:
The two paths are selected by the logic levels at the two control pin-connectors, VA and VT,
(refer to the schematic for the connector designation) according to the following truth table:
VA VT Path 1
(PA)
Path 2
(Thru)
0 V 3.0 V OFF ON
3.0 V 0 V ON OFF
The matching and bias circuits for the uPG2250T5N are based on those used in the CEL’s
evaluation circuit board, uPG2250T5N-EVAL-A with some changes on a few component values
to accommodate the difference in layout. For more information on the PA circuit design, refer to
the Evaluation Board Document of uPG2250T5N-EVAL-A in the appendix.
The PCB is FR4 four layer board. The top and bottom dielectric layers are 8mils thick. The total
board thickness is 62mils. The dielectric constant of FR4 is 4.3.
Typical Performance Data
Path 1:
Test conditions:
F=2.45GHz, Vdd=3V, Vcont=1.8V
The output power, Pout, supply current, Idd, and power added efficiency, PAE, as a function of
input power, Pin, are shown in the following plot.
0
5
10
15
20
25
30
35
40
45
-30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4
Pin (dBm)
Pout (dBm), PAE (%)
60
80
100
120
140
160
180
200
220
Current (mA)
Pout 3.0V
PAE 3.0V
Current 3.0V
Path 2:
The insertion of the “thru” path is 1.2dB.
Evaluation Board Document
µPG2250T5N-EVAL-A
Evaluation Board
o Circuit Description
o Performance data
o Circuit schematic and assembly drawing
2
Circuit Description
The circuit schematic and assembly drawing are shown on the last two pages.
Matching and Bias Circuits
The inductor L1 is for input matching and should be placed close to the device.
The output matching is realized mainly with the capacitor C6. C6 can be placed as close as
possible to the device without much sacrifice of the performance when the layout space is tight.
On the other hand the output power can be increased by a fraction of dB by moving C6 away
from the device. The trace length between C6 and the device on this evaluation board is about
100 mil. Because of the gradual change in its width, the effect of this section of trace cannot be
simply represented by a set of parameters of transmission line impedance and electrical length.
It is recommended that the designer leave some space for tuning on this trace length in the initial
prototype board layout if an optimal output power is desirable.
The uPG2250T5N has three gain stages, each being biased by an external voltage supply. The
DC feed lines are not completely isolated from the RF path on the chip, and as a result care
needs to be taken in the board layout for these DC lines.
The inductor L2 on the Vdd1 line provides the DC feed for the first stage and is part of the inter-
stage matching between stage 1 and 2 as well. The value of this inductor may need to be adjusted
on the application board to have the optimized performance. Generally it should be placed close
to the device and immediately followed by the capacitor C2 as shown in the assembly drawing of
this evalboard.
The length of trace TL1 on the Vdd2 line has significant impact on the output power and the
value shown in the schematic should be used in the application board layout.
The inductor L3 is for the last stage DC feed and functions as an RF choke. Its value and
location are not critical.
The three shunt capacitors on the DC lines (C2, C8 and C9) provide a low RF impedance at their
respective locations. Their value should be in the range of 10 to 30pF. These low RF impedance
spots adequately isolate the RF circuit from the rest of DC feed lines beyond the point of shunt
capacitors. This arrangement is particularly beneficial in transferring the evaluation circuit to the
end products because the RF characteristic of a DC feed line usually cannot be well controlled in
a practical board design. The other three 0.01uF capacitors, C1, C3 and C5, are general bypass
capacitors and the user can select their values and locations according the design requirements.
PCB Material
The PCB is Getek two layer board. The board thickness is 28mil.
Typical Performance Data
Test Conditions:
f=2.45GHz; Pin= -5dBm; Vcont =1.8V
For VDD1,2,3 =1.8V
Quiescent current Idsq: 55mA;
Output Power Pout: 21dBm;
Supply Current IDD: 130mA;
Efficiency PAE: 55%;
For VDD1,2,3 =3V
Quiescent current Idsq: 80mA;
Output Power Pout: 25dBm;
Supply Current IDD: 200mA;
Efficiency PAE: 55%;
Pout and PAE vs Pin are shown in the following plot.
0
2
4
6
8
10
12
14
16
18
20
22
24
26
-30-28-26-24-22-20-18-16-14-12-10 -8 -6
Pi n (dBm)
Pout ( dBm)
0
10
20
30
40
50
60
PAE ( % )
Pout 1.8V
Pout 3.0V
PAE 1.8V
PAE 3.0V
3
