CM3202-00DE - ON Semiconductor

April, 2011 − Rev. 3

1Publication Order Number:

CM3202−00/D

CM3202-00

DDR VDDQ and VTT

Termination Voltage

Regulator

Product Description

The CM3202−00 is a dual−output low noise linear regulator

designed to meet SSTL−2 and SSTL−3 specifications for

DDR−SDRAM VDDQ supply and termination voltage VTT supply.

With integrated power MOSFET’s, the CM3202−00 can source up to

2 A of VDDQ continuous current, and source or sink up to 2 A VTT

continuous current. The typical dropout voltage for VDDQ is 500 mV

at 2 A load current.

The CM3202−00 provides fast response to transient load changes.

Load regulation is excellent, from no load to full load. It also has

built−in over−current limits and thermal shutdown at 170°C.

The CM3202−00 supports Suspend−To−RAM (STR) and ACPI

compliance with shutdown mode which tri−states VTT to minimize

quiescent system current.

The CM3202−00 is packaged in an easy−to−use WDFN8. Low

thermal resistance allows it to withstand high power dissipation at

85°C ambient. It operates over the industrial ambient temperature

range of –40°C to 85°C.

Features

•Two Linear Regulators

♦Maximum 2 A Current from VDDQ

♦Source and Sink Up to 2 A VTT Current

•1.7 V to 2.8 V Adjustable VDDQ Output Voltage

•500 mV Typical VDDQ Dropout Voltage at 2 A

•VTT Tracking at 50% of VDDQ

•Excellent Load and Line Regulation, Low Noise

•Fast Transient Response

•Meet JEDEC DDR−I and DDR−II Memory Power Spec.

•Linear Regulator Design Requires No Inductors and Has Low

External Component Count

•Integrated Power MOSFETs

•Dual Purpose ADJ/Shutdown Pin

•Built−In Over−Current Limit and Thermal Shutdown for VDDQ

and VTT

•Fast Transient Response

•Low Quiescent Current

•These Devices are Pb−Free and are RoHS Compliant

Applications

•DDR Memory and Active Termination Buses

•Desktop Computers, Servers

•Residential and Enterprise Gateways

•DSL Modems

•Routers and Switchers

•DVD Recorders

•3D AGP Cards

•LCD TV and STB

MARKING DIAGRAM

Device Package Shipping†

ORDERING INFORMATION

http://onsemi.com

CM3202−00DE WDFN8

(Pb−Free)

3000/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

CM320 200DE = CM3202−00DE

CM320

200DE

WDFN8

DE SUFFIX

CASE 511BH

CM3202−00

http://onsemi.com

TYPICAL APPLICATION

VIN = 3.3 V to 3.6 V

CIN

220 mF/

10 V

CTT

4.7 mF/

10 V

cer

VTT = 1.25 V/2 A

VIN

VTT

CM3202

VDDQ

ADJSD

GND

S/D

10 kW

VDDQ = 2.5 V/2 A

Chip

Set

VDDQ

CDDQ

DL0

DLn

VDDQ

RT0

RTn

DDR

REF MEMORY

VTT

0.1 mF/10 V

cer

4.7 mF/10 V

cer

220 mF/

10 V

4.7 mF/10 V, cer

220 mF/

10 V

1 kW

1.25 V, 2.5 A

VREF

10 kW

FUNCTIONAL BLOCK DIAGRAM

VIN ADJSD VDDQ

VTT

GND

Current

Limit

OTP &

Shutdown

UVLO &

Bandgap

CM3202

Current

Limit

1.22 V

0.49*

VDDQ

0.51*

VDDQ

Current

Limit

CM3202−00

http://onsemi.com

PACKAGE / PINOUT DIAGRAMS

Top View

(Pins Down View)

CM320

200DE

Thermal Pad

Pin 1

Marking

VIN

VTT

VDDQ

ADJSD

GND

8−Lead WDFN Package

CM3202−00DE

GND

PAD

Bottom View

(Pins Up View)

Table 1. PIN DESCRIPTIONS

Lead(s) Name Description

1 VIN Input supply voltage pin. Bypass with a 220 mF capacitor to GND.

2 NC Not internally connected. For better heat flow, connect to GND (exposed pad).

3 VTT VTT regulator output pin, which is preset to 50% of VDDQ.

4 NC Not internally connected. For better heat flow, connect to GND (exposed pad).

5 GND Ground pin (analog).

6 GND Ground pin (power).

7 ADJSD

This pin is for VDDQ output voltage adjustment. It is available as long as VDDQ is enabled.

During Manual/Thermal shutdown, it is tightened to GND. The VDDQ output voltage is set

using an external resistor divider connected to ADJSD:

VDDQ = 1.25 V ×((R1 + R2) / R2)

Where R1 is the upper resistor and R2 is the ground−side resistor. In addition, the ADJSD pin functions as

a Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode.

When ADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low−leakage Schottky

diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting.

8 VDDQ VDDQ regulator output voltage pin.

EPad GND The backside exposed pad which serves as the package heatsink. Must be connected to GND.

CM3202−00

http://onsemi.com

SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

VIN to GND [GND − 0.3] to +6.0 V

Pin Voltages

VDDQ, VTT to GND

ADJSD to GND

[GND − 0.3] to +6.0

Output Current

VDDQ / VTT, Continuous (Note 1)

VDDQ / VTT, Peak

VDDQ Source + VTT Source

2.0 / ±2.0

2.8 / ±2.8

Temperature

Operating Ambient

Operating Junction

Storage

–40 to +85

–40 to +170

–40 to +150

°C

Thermal Resistance, RJA (Note 2)

WDFN8, 3 mm x 3 mm

55 °C / W

Continuous Power Dissipation (Note 2)

WDFN8, TA = 25°C / 85°C2.6 / 1.5

ESD Protection (HBM) 2000 V

Lead Temperature (Soldering, 10 sec) 300 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling these under all

conditions. Limited by the package thermal resistance, the maximum output current of the device cannot exceed the limit imposed by the

maximum power dissipation value.

2. Measured with the package using a 4 in2 / 2 layers PCB with thermal vias.

Table 3. STANDARD OPERATING CONDITIONS

Parameter Rating Units

Ambient Operating Temperature Range –40 to +85 °C

VDDQ Regulator

DDR−1 Supply Voltage, VIN

Load Current, Continuous

Load Current, Peak (1 s)

CDDQ

3.1 to 3.6

0 to 2

2.5

220

VTT Regulator

DDR−1 Supply Voltage, VIN

Load Current, Continuous

Load Current, Peak (1 s)

CTT

3.1 to 3.6

0 to ±2.0

±2.50

220

VIN Supply Voltage Range 3.10 to 3.60 V

VDDQ Source + VTT Source

Load Current, Continuous

Load Current, Peak (1 s)

2.5

3.5

Junction Operating Temperature Range –40 to +150 °C

CM3202−00

http://onsemi.com

SPECIFICATIONS (Cont’d)

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)

Symbol Parameter Conditions Min Typ Max Units

General

IQQuiescent Current IDDQ = 0, ITT = 0 8 15 mA

ISHDN Shutdown Current VADJSD = 3.3 V (Shutdown) 0.1 0.5 mA

SHDN_H ADJSD Logic High (Note 2) 2.7 V

SHDN_L ADJSD Logic Low 1.50 V

UVLO Under−Voltage Lockout Hysteresis = 100 mV 2.40 2.70 2.90 V

TOVER Thermal SHDN Threshold 150 170 °C

THYS Thermal SHDN Hysteresis 50 °C

TEMPCO VDDQ, VTT TEMPCO 150 ppm/°C

VDDQ Regulator

VDDQ DEF VDDQ Output Voltage IDDQ = 100 mA 2.450 2.500 2.550 V

VDDQ LOAD VDDQ Load Regulation 10 mA ≤ IDDQ ≤ 2 A (Note 3) 10 25 mV

VDDQ LINE VDDQ Line Regulation 3.1 V ≤ VIN ≤ 3.6 V, IDDQ = 0.1 A 5 25 mV

VDROP VDDQ Dropout Voltage IDDQ = 2 A (Note 4) 500 mV

IADJ ADJSD Bias Current 0.8 3.0 mA

IDDQ LIM VDDQ Current Limit 2.0 2.5 A

VTT Regulator

VTT DEF VTT Output Voltage ITT = 100 mA 1.225 1.250 1.275 V

VTT LOAD VTT Load Regulation Source, 0 ≤ ITT ≤ 2 A (Note 3)

Sink, −2A ≤ ITT ≤ 0 (Note 3) –30

–10

30 mV

VTT LINE VTT Line Regulation 3.1 V ≤ VIN ≤ 3.6 V, ITT = 0.1 A 5 15 mV

ITT LIM ITT Current Limit Source / Sink (Note 3) ±2.0 ±2.5 A

IVTT OFF VTT Shutdown Leakage Current Thermal Shutdown Enabled 10 mA

1. VIN = 3.3 V, VDDQ = 2.50 V, VTT = 1.25 V (default values), CDDQ = CTT = 47 mF, TA = 25°C unless otherwise specified.

2. he SHDN Logic High value is normally satisfied for full input voltage range by using a low leakage current (bellow 1 mA). Schottky diode at

ADJSD control pin.

3. Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. Changes in output

voltage due to heating effects must be taken into account separately. Load and line regulation values are guaranteed up to the maximum

power dissipation.

4. Dropout voltage is input to output voltage differential at which output voltage has dropped 100 mV from the nominal value obtained at 3.3 V

input. It depends on load current and junction temperature.

CM3202−00

http://onsemi.com

TYPICAL OPERATING CHARACTERISTICS

0.75

0.85

0.95

1.05

1.15

1.25

1.35

1.45

1.55

1.65

1.5 1.75 2 2.25 2.5 2.75 3 3.25

2.490

2.495

2.500

2.505

2.510

−40 −20 0 20 40 60 80 100 120 140

0 0.5 1.0 1.5 2.0 2.50 1.0 2.0 3.0 4.0

100

200

300

400

500

600

0.5

1.0

1.5

2.0

2.5

3.0

0.5

1.0

1.5

2.0

2.5

TEMPERATURE (5C)

VDDQ (V)

VDDQ vs. Temperature

VTT vs. VDDQ

VDDQ (V)

VTT (V)

VDDQ vs. Load Current

IDDQ (A)

VDDQ (V)

VIN = 3.3 V

TA = 25°C

VDDQ Dropout vs. IDDQ

IDDQ (A)

Dropout Voltage (mV)

TA = 25°C

VTT vs. Load Current

ITT (A)

VTT (V)

Startup into Full Load

TIME (1 ms/div)

UVLO

Vin

2 V/div

VTT

1 V/div

Vin

2 V/div

VDDQ

1 V/div

0 1.0 2.0 3.0 4.0

CM3202−00

http://onsemi.com

TYPICAL OPERATING CHARACTERISTICS (Cont’d)

VIN

IDDQ

0.5A/div

VDDQ

0.1V/div

ITT

0.5A/div

VTT

0.1V/div

TIME (0.2 ms/div)

-0.75A

VDDQ Transient Response VTT Transient Response

VIN = 3.3V

TIME (0.2 ms/div)

APPLICATION INFORMATION

Powering DDR Memory

Double−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic

systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle

versus one. DDR SDRAM’s transmit data at both the rising and falling edges of the memory bus clock.

DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while

reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management

architecture than previous RAM technology.

Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface

signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by

lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use

of a termination voltage, VTT. SSTL_2 is an industry standard defined in JEDEC document JESD8−9. SSTL_2 maintains

high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM

specification in JESD79C.

DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Typical DDR terminations, Class II). In

a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5 V with a tolerance of ±200 mV. The active

bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, ±1%, and is compared

with the VTT terminated signal at the receiver. VTT must be within ±40 mV of VREF

Figure 1. Typical DDR Terminations, Class II

−

VDDQ VTT (=VDDQ/2) VDDQ

VREF (=VDDQ/2)

Receiver

Transmitter

LineRs = 25

Rt = 25

CM3202−00

http://onsemi.com

APPLICATION INFORMATION (Cont’d)

The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but

does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume

16.2 mA to achieve the 405 mV minimum over VTT needed at the receiver:

Iterminaton +405mV

Rt(25W)+16.2mA

A typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum VTT supply current up

to ±2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if

they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the

continuous average VTT current level in normal operation is less than ±200 mA.

The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers

and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending

on memory size and the computing operations being performed.

The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for

powering DDR SDRAM.

CM3202−00 Regulator

The CM3202−00 dual output linear regulator provides all of the power requirements of DDR memory by combining two

linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant VTT

termination regulator has current sink and source capability to ±2 A. The VDDQ linear regulator uses a PMOS pass element

for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of VDDQ can be set by an external voltage

divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any

change of the load, from high current to low current or inversely. The second output, VTT, is regulated at VDDQ/2 by an internal

resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The VTT regulator

can source, as well as sink, up to 2 A current. The CM3202−00 is designed for optimal operation from a nominal 3.3 VDC bus,

but can work with VIN as high as 5 V. When operating at higher VIN voltages, attention must be given to the increased package

power dissipation and proportionally increased heat generation.

VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF

can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass

capacitor can also be added for improved noise performance.

Input and Output Capacitors

The CM3202−00 requires that at least a 220 mF electrolytic capacitor be located near the VIN pin for stability and to maintain

the input bus voltage during load transients. An additional 4.7 mF ceramic capacitor between the VIN and the GND, located

as close as possible to those pins, is recommended to ensure stability.

At a minimum of a 220 mF electrolytic capacitor is recommended for the VDDQ output. An additional 4.7 mF ceramic

capacitor between the VDDQ and GND, located very close to those pins, is recommended.

At a minimum of a 220 mF electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR

to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good

choice. In addition, place a 4.7 mF ceramic capacitor between the VTT pin and GND, located very close to those pins. The total

ESR must be low enough to keep the transient within the VTT window of 40 mV during the transition for source to sink.

An average current step of ±0.5 A requires:

ESR t40mV

1A+40mW

Both outputs will remain stable and in regulation even during light or no load conditions.

CM3202−00

http://onsemi.com

APPLICATION INFORMATION (Cont’d)

Adjusting VDDQ Output Voltage

The CM3202−00 internal bandgap reference is set at 1.25 V. The VDDQ voltage is adjustable by using a resistor divider, R1

and R2:

VDDQ +VADJ R1)R2

where VADJ = 1.25 V. For best regulator stability, we recommend that R1 and R2 not exceed 10 kW each.

Shutdown

ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri−state

and could sink/source less than 10 mA. During shutdown, the quiescent current is reduced to less than 0.5 mA, independent

of output load.

It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal

to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202−00

is again enabled.

Current Limit, Foldback and Over−temperature Protection

The CM3202−00 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output

current to approximately 2 A and VTT limits the output current to approximately ±2 A. When VTT is current limiting into a hard

short circuit, the output current folds back to a lower level, about 1 A, until the over−current condition ends. While current

limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the

package. If the junction temperature of the device exceeds 170°C (typical), the thermal protection circuitry triggers and

tri−states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120°C the CM3202−00

returns to normal operation.

Thermal Considerations

Typical Thermal Characteristics

The overall junction to ambient thermal resistance (qJA) for device power dissipation (PD) primarily consists of two paths

in the series. The first path is the junction to the case (qJC) which is defined by the package style and the second path is case

to ambient (qCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any

condition can be estimated by the following thermal equation:

TJUNC +TAMB )PD (qJC))PD (qCA)

+TAMB )PD (qCA)

When a CM3202−00 using WDFN8 package is mounted on a double−sided printed circuit board with four square inches

of copper allocated for “heat spreading,” the qJA is approximately 55°C/W. Based on the over temperature limit of 170°C with

an ambient temperature of 85°C, the available power of the package will be:

PD+170° C*85° C

55° CńW+1.5W

CM3202−00

http://onsemi.com

APPLICATION INFORMATION (Cont’d)

PCB Layout Considerations

TheCM3202−00 has a heat spreader attached to the bottom of the WDFN8 package in order for the heat to be transferred

more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself.

By positioning the matching pad on the PCB top layer to connect to the spreader during the manufacturing, the heat will be

transferred between the two pads. See the Thermal Layout, the CM3202−00 shows the recommended PCB layout. Please be

noted that there are four vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers

of the PCB. Vias can be placed underneath the chip, but this can be resulted in blocking of the solder. The ground and power

planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from

the edge of the PCB, and not near other heat−dissipating devices. A good thermal link from the PCB pad to the rest of the PCB

will assure the best heat transfer from the CM3202−00 to ambient, qJA, of approximately 55°C/W.

Figure 2. Thermal Layout for WDFN8 Package

Vias (0. 3 mm Diameter)

Thermal PAD

Solder Mask

Pin Solder Mask

Top Layer Copper

Connects to Heat Spreader

Bottom Layer

Ground Plane

Top View

CM3202−00

http://onsemi.com

PACKAGE DIMENSIONS

WDFN8, 3x3, 0.65P

CASE 511BH−01

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇ

C0.10

PIN ONE

REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

C0.10

C0.08

A1 SEATING

PLANE

NOTE 3

0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.70 0.80

A1 0.00 0.05

b0.25 0.35

D3.00 BSC

D2 2.20 2.40

E3.00 BSC

E2 1.40 1.60

e0.65 BSC

L0.20 0.40

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65

PITCH

1.66 3.30

DIMENSIONS: MILLIMETERS

0.53

NOTE 4

0.40

DETAIL A

A3 0.20 REF

DETAIL B

DETAIL A

ALTERNATE

CONSTRUCTIONS

ÉÉ

ÇÇ

ÇÇÇ

ÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS

L1 −−− 0.15

OUTLINE

PACKAGE

RECOMMENDED

K0.45 REF

2.46

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

CM3202−00/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative