General Description
The MAX1146–MAX1149 low-power, 14-bit, multichan-
nel, analog-to-digital converters (ADCs) feature an
internal track/hold (T/H), voltage reference, and clock.
The MAX1146/MAX1148 operate from a single +4.75V
to +5.25V supply, and the MAX1147/MAX1149 operate
from a single +2.7V to +3.6V supply. All analog inputs
are software configurable for unipolar/bipolar and sin-
gle-ended/differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The serial strobe output (SSTRB) allows conve-
nient connection to digital signal processors. The
MAX1146–MAX1149 use an internal clock or an exter-
nal serial-interface clock to perform successive-approx-
imation analog-to-digital conversions.
The MAX1146/MAX1148 include an internal +4.096V
reference, while the MAX1147/MAX1149 include an
internal +2.500V reference. All devices accept an exter-
nal reference from 1.5V to VDD.
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes. Using the soft-
ware power-down modes allows the devices to be pow-
ered down between conversions. When powered down,
accessing the serial interface automatically powers up
the devices. The quick turn-on time allows power-down
between all conversions. This technique reduces sup-
ply current to under 120µA for quick turn-on.
The MAX1146–MAX1149 are available in a 20-pin
TSSOP package.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
Features
♦8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1148/MAX1149)
♦4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1146/MAX1147)
♦Internal Multiplexer and T/H
♦Single-Supply Operation
4.75V to 5.25V Supply (MAX1146/MAX1148)
2.7V to 3.6V Supply (MAX1147/MAX1149)
♦Internal Reference
+4.096V (MAX1146/MAX1148)
+2.500V (MAX1147/MAX1149)
♦116ksps Sampling Rate
♦Low Power
1.1mA (116ksps)
120µA (10ksps)
12µA (1ksps)
300nA (Power-Down Mode)
♦SPI-/QSPI-/MICROWIRE Compatible
♦20-Pin TSSOP
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information/Selector Guide
19-3488; Rev 2; 1/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
PKG
CODE
MAX1146BCUP 0°C to +70°C 20 TSSOP ±2 4 +4.096 U20-3
MAX1146BEUP -40°C to +85°C 20 TSSOP ±2 4 +4.096 U20-3
MAX1147BCUP 0°C to +70°C 20 TSSOP ±2 4 +2.500 U20-3
MAX1147BEUP -40°C to +85°C 20 TSSOP ±2 4 +2.500 U20-3
MAX1148BCUP 0°C to +70°C 20 TSSOP ±2 8 +4.096 U20-3
MAX1148BEUP -40°C to +85°C 20 TSSOP ±2 8 +4.096 U20-3
MAX1149BCUP 0°C to +70°C 20 TSSOP ±2 8 +2.500 U20-3
MAX1149BEUP -40°C to +85°C 20 TSSOP ±2 8 +2.500 U20-3
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND..........................-0.3V to (VDD + 0.3V)
REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD + 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA= +70°C)
20 TSSOP (derate 10.9mW/°C above +70°C) .............879mW
Operating Temperature Ranges
MAX114_ BC_ _ ..................................................0°C to +70°C
MAX114_ BE_ _ ...............................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DC ACCURACY (Note 1)
Resolution 14 Bits
Relative Accuracy (Note 2) INL
±0.7
±2 LSB
Differential Nonlinearity DNL No missing codes over temperature
-1.0 ±0.5 +1.5
LSB
Offset Error
±10
LSB
Offset Temperature Coefficient 0.3
ppm/°C
Gain Error (Note 3)
±20
LSB
Gain Temperature Coefficient
±0.8
ppm/°C
Channel-to-Channel Offset
Matching ±1 LSB
Channel-to-Channel Gain
Matching ±1 LSB
DYNAMIC SPECIFICATIONS (1kHz sine-wave input, 2.5VP-P, full-scale analog input, 116ksps, 2.1MHz external clock)
Signal-to-Noise Plus Distortion
Ratio SINAD 77 81 dB
Total Harmonic Distortion THD Up to the 5th harmonic -96 -88 dB
Spurious-Free Dynamic Range SFDR 84 98 dB
Channel-to-Channel Crosstalk (Note 4) -85 dB
Small-Signal Bandwidth SSBW -3dB point 3.0
MHz
Full-Power Bandwidth FPBW SINAD > 68dB 2.0
MHz
CONVERSION RATE
External clock, 2.1MHz 15 SCLK cycles 7.2
Conversion Time (Note 5) tCONV Internal clock 6 8 µs
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
18 clocks/conversion 60.3
Internal clock mode,
fSCLK = 2.1MHz
24 clocks/conversion 51.5
18 clocks/conversion 116.66
Throughput Rate
fSAMPLE External clock mode,
fSCLK = 2.1MHz
24 clocks/conversion 87.50
ksps
T/H Acquisition Time tACQ 1.4 µs
Aperture Delay tAD 20 ns
Aperture Jitter tAJ
<50
ps
External clock mode 0.1 2.1
Serial Clock Frequency fSCLK Internal clock mode 0 2.1
MHz
Internal Clock Frequency 2.1
MHz
ANALOG INPUTS (CH0–CH7, COM)
Unipolar, COM = 0 0
VREF
Input Voltage Range, Single-
Ended and Differential (Note 6) Bipolar, COM = VREF / 2, single-ended
±VREF / 2
V
Multiplexer Leakage Current On/off-leakage current, VCH_ = 0 to VDD
±0.01
±1 µA
Input Capacitance 18 pF
INTERNAL REFERENCE (CREF = 2.2µF, CREFADJ = 0.01µF)
MAX1147/MAX1149, TA = +25°C
2.480 2.500 2.520
REF Output Voltage VREF MAX1146/MAX1148, TA = +25°C
4.076 4.096 4.116
V
REF Short-Circuit Current IREFSC REF = DGND 20 mA
MAX114_ BC _ _
±30 ±50
VREF Tempco (Note 7) MAX114_ BE _ _
±40 ±60
ppm/°C
Load Regulation 0 to 0.2mA output load (Note 8) 2.0 mV
Capacitive Bypass at REF 2µF
Capacitive Bypass at REFADJ
0.01
µF
REFADJ Output Voltage
1.250
V
REFADJ Input Range
±18
mV
REFADJ Logic High Pull REFADJ high to disable the internal
bandgap reference and reference buffer
VDD -
0.25V
V
MAX1147/MAX1149
2.000
Reference Buffer Voltage Gain MAX1146/MAX1148
3.277
V/V
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V (MAX1146/MAX1148), VDD = 3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
EXTERNAL REFERENCE AT REF
REF Input Voltage Range VREF 1.5 VDD +
50mV
V
125
450
REF Input Current IREF Shutdown
0.01
10 µA
REF Input Resistance 68 kΩ
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
VDD < 3.6V 2.0
Input High Voltage VIH VDD > 3.6V 3.0 V
Input Low Voltage VIL 0.8 V
Input Hysteresis VHYST 0.2 V
Input Leakage IIN ±1 µA
Input Capacitance CIN 10 pF
DIGITAL OUTPUT (DOUT, SSTRB)
Output-Voltage Low VOL ISINK = 2mA 0.4 V
Output-Voltage High VOH ISOURCE = 2mA
VDD - 0.5
V
Tri-State Leakage Current ILCS = VDD
±10
µA
Tri-State Output Capacitance COUT CS = VDD 10 pF
POWER REQUIREMENTS
MAX1147/MAX1149 2.7 3.6
Positive Supply Voltage VDD MAX1146/MAX1148
4.75 5.25
V
116ksps 1.1 1.5
10ksps
0.12
External
reference 1ksps
0.012
mA
Supply Current (Note 8) IDD
Normal
operation, full-
scale input Internal reference at
116ksps 1.9 2.4 mA
Fast power-down
120
Full power-down 0.3
Shutdown Supply Current
(Note 8) SHDN = DGND 0.3 10
µA
Power-Supply Rejection (Note 9)
PSR External reference
±0.2
mV
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
_______________________________________________________________________________________ 5
Note 1: Tested at VDD = 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled. Measured with external reference.
Note 4: “On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Digital inputs equal VDD or DGND.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the
MAX1146/MAX1148. VDD = 3.6V to 2.7V for MAX1147/MAX1149 and VDD = 5.25V to 4.75V for the MAX1146/MAX1148.
TIMING CHARACTERISTICS
(VDD = 4.75V to 5.25V (MAX1146/MAX1148), VDD = 2.7V to 3.6V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, CREF = 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA= TMIN to TMAX, unless otherwise noted.
Typical values are at TA= +25°C.) (Figures 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DIN to SCLK Setup Time tDS 50 ns
DIN to SCLK Hold Time tDH 0ns
SCLK Fall to Output Data Valid tDOV CLOAD = 50pF 10 80 ns
CS Fall to DOUT Enable tDOE CLOAD = 50pF 120 ns
CS Rise to DOUT Disable tDOD CLOAD = 50pF 120 ns
SHDN Rise CS Fall to SCLK Rise
Time tCSS 50 ns
SHDN Rise CS Fall to SCLK Rise
Hold Time tCSH 50 ns
External clock mode 0.1 2.1
SCLK Clock Frequency fSCLK Internal clock mode 0 2.1
MHz
SCLK Pulse-Width High tCH Internal clock mode
100
ns
SCLK Pulse-Width Low tCL Internal clock mode
100
ns
CS Fall to SSTRB Output Enable
tSTE External clock mode only 120 ns
CS Rise to SSTRB Output Disable
tSTD External clock mode only 120 ns
SSTRB Rise to SCLK Rise tSCK Internal clock mode only 0 ns
SCLK Fall to SSTRB Edge tSCST 80 ns
CS Pulse Width tCSW
100
ns
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
6 _______________________________________________________________________________________
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
HIGH-Z
SCLK
DIN START SEL2 SEL1 SEL0 PD1 PD0
189
tACQ
SSTRB
(INTERNAL CLOCK MODE)
SSTRB
(EXTERNAL CLOCK MODE)
DOUT D13 D12 D11 D10
HIGH-Z
tCSH
tCH
tCL
tCSS
tDS tDH
1
fSCLK
tDOE
tSTE
tDOV
24
D2 D1 D0
tDOD
tSTD
tCSW
HIGH-Z
HIGH-Z
tSCK
tSCST
tSCST
CS
SGL/DIF UNI/BIP
Figure 3. Detailed Operating Characteristics
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
_______________________________________________________________________________________ 7
INL vs. OUTPUT CODE
MAX1146 toc01
OUTPUT CODE
INL (LSB)
1228881924096
-1.0
-0.5
0
0.5
1.0
1.5
-1.5
0 16384
DNL vs. OUTPUT CODE
MAX1146 toc02
OUTPUT CODE
DNL (LSB)
1228881924096
-1.0
-0.5
0
0.5
1.0
1.5
-1.5
0 16384
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
2.7 3.6
INTERNAL REFERENCE
EXTERNAL REFERENCE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
4.75 5.25
INTERNAL REFERENCE
EXTERNAL REFERENCE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc05
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (µA)
3.53.43.2 3.32.9 3.0 3.12.8
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2.7 3.6
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1146 toc07
CONVERSION RATE (ksps)
SUPPLY CURRENT (µA)
1001010.1
200
400
600
800
1000
1200
0
0.01 1000
FAST POWER-DOWN
FULL
POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
MAX1146 toc08
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
0.5
1.0
1.5
2.0
2.5
0
-40 85
MAX1146/MAX1148 INTERNAL REFERENCE
MAX1147/MAX1149 INTERNAL REFERENCE
MAX1146/MAX1148 EXTERNAL REFERENCE
MAX1147/MAX1149 EXTERNAL REFERENCE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1146 toc09
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
603510-15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
-40 85
MAX1146/MAX1148
MAX1147/MAX1149
Typical Operating Characteristics
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA= +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (µA)
5.155.054.954.85
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0
4.75 5.25
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
8 _______________________________________________________________________________________
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc10
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
5.155.054.85 4.95
4.0945
4.0950
4.0955
4.0960
4.0965
4.0970
4.0975
4.0980
4.0940
4.75 5.25
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc11
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
3.33.0
2.4985
2.4990
2.4995
2.5000
2.5005
2.5010
2.5015
2.5020
2.4980
2.7 3.6
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1146/MAX1148)
MAX1146 toc12
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
603510-15
4.091
4.092
4.093
4.094
4.095
4.096
4.097
4.098
4.099
4.100
4.090
-40 85
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1147/MAX1149)
MAX1146 toc13
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
603510-15
2.498
2.499
2.500
2.501
2.502
2.503
2.497
-40 85
REFERENCE BUFFER POWER-UP DELAY
vs. TIME IN SHUTDOWN
MAX1146 toc14
TIME IN SHUTDOWN (s)
DELAY (µs)
10.10.01
500
1000
1500
2000
2500
0
0.001 10
CREF = 4.7µF
CREFADJ = 0.01µF
FFT PLOT
MAX1146 toc15
FREQUENCY (Hz)
AMPLITUDE (dB)
50004000300020001000
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
-120
0
fIN = 1kHz
fSAMPLE = 116ksps
VDD = 5V/3V
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
MAX1146 toc16
FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
4637281910
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
13.0
12.0
155
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA= +25°C, unless otherwise noted.)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
_______________________________________________________________________________________ 9
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc19
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
3.33.0
-4
-2
0
2
4
6
-6
2.7 3.6
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc20
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
5.155.054.85 4.95
-4
-2
0
2
4
6
-6
4.75 5.25
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc21
SUPPLY VOLTAGE (V)
GAIN MATCHING (LSB)
3.33.0
-4
-2
0
2
4
6
-6
2.7 3.6
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
XMAX1146 toc22
SUPPLY VOLTAGE (V)
GAIN MATCHING (LSB)
5.155.054.954.85
-4
-2
0
2
4
6
-6
4.75 5.25
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc17
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
3.33.0
-4
-2
0
2
4
6
-6
2.7 3.6
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc18
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
5.155.054.954.85
-7
-4
-5
-6
-2
-3
-1
0
-8
4.75 5.25
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
10 ______________________________________________________________________________________
OFFSET ERROR vs. TEMPERATURE
MAX1146 toc28
TEMPERATURE (°C)
OFFSET ERROR (LSB)
6035-15 10
-4
-2
0
2
4
6
-6
-40 85
Typical Operating Characteristics (continued)
(VDD = +5.0V (MAX1146/MAX1148), VDD = +3.3V (MAX1147/MAX1149), SHDN = VDD, VCOM = 0, fSCLK = 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ = VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF = 2.2µF, CLOAD = 50pF, TA= +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
MAX1146 toc26
TEMPERATURE (°C)
OFFSET MATCHING (LSB)
6035-15 10
-4
-2
0
2
4
6
-6
-40 85
GAIN ERROR vs. TEMPERATURE
MAX1146 toc27
TEMPERATURE (°C)
GAIN ERROR (LSB)
6035-15 10
-4
-2
0
2
4
6
-6
-40 85
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc24
SUPPLY VOLTAGE (V)
OFFSET MATCHING (LSB)
3.33.0
-4
-2
0
2
4
6
-6
2.7 3.6
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc25
SUPPLY VOLTAGE (V)
OFFSET MATCHING (LSB)
5.155.054.85 4.95
-4
-2
0
2
4
6
-6
4.75 5.25
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
MAX1146 toc23
TEMPERATURE (°C)
GAIN MATCHING (LSB)
6035-15 10
-4
-2
0
2
4
6
-6
-40 85
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 11
PIN
MAX1148
MAX1149
MAX1146
MAX1147
NAME
FUNCTION
1 1 CH0
2 2 CH1
3 3 CH2
4 4 CH3
5 — CH4
6 — CH5
7 — CH6
8 — CH7
Analog Inputs
9 9 COM Common Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.
10 10 SHDN Active-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current
to 0.2µA. Driving shutdown high enables the devices.
11 11 REF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.
12 12
REFADJ
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01µF
capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and reference-
buffer amplifier.
13 13
AGND
Analog Ground
14 14
DGND
Digital Ground
15 15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.
16 16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).
17 17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.
18 18 CS Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19 19 SCLK Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed
in external clock mode. (Duty cycle must be 40% to 60%.)
20 20 VDD Positive Supply Voltage. Bypass to AGND with a 0.1µF capacitor.
— 5–8 N.C. No Connection. Not internally connected.
Pin Description
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
12 ______________________________________________________________________________________
Detailed Description
The MAX1146–MAX1149 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy inter-
face to microprocessors (µPs). Figure 4 shows the typi-
cal application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
True-Differential Analog Input and
Track/Hold
The MAX1146–MAX1149 analog input architecture con-
tains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
CT/H+ and CT/H- track the analog input signal. At the
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retain-
ing the charge on CT/H+ and CT/H- as a sample of the
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF ×(VIN+ - VIN-) from
CT/H+ and CT/H- to the binary-weighted capacitive
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is com-
plete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisi-
tion time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (tACQ) in which the T/H capacitance
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (RSOURCE) should be mini-
mized to allow the T/H capacitance to charge within
this allotted time.
tACQ = 11.5 ×(RSOURCE + RIN) ×CIN
where RSOURCE is the analog input source impedance,
RIN is 2.6kΩ(which is the sum of the analog input MUX
and T/H switch resistances), and CIN is 18pF (which is
the sum of CT/H+, CT/H-, and input stray capacitance).
To minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
Figure 4. Typical Application Circuit
Figure 5. Functional Diagram
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 13
Input Bandwidth
The MAX1146–MAX1149 feature input tracking circuitry
with a 3.0MHz small-signal bandwidth. The 3.0MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes clamp the analog input to
VDD and AGND. These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (VDD + 0.3V) without
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV below
AGND or above VDD.
Note: If the analog input exceeds 50mV beyond the sup-
ply rails, limit the current to 2mA.
Quick Look
Use the circuit of Figure 7 to quickly evaluate the
MAX1148/MAX1149. The MAX1148/MAX1149 require a
control byte to be written to DIN using SCLK before
each conversion. Connecting DIN to VDD and clocking
SCLK feeds in a control byte of $FF HEX (see Table 1).
Trigger single-ended unipolar conversions on CH7 in
external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for two clock periods before the MSB of the
14-bit conversion result is shifted out of DOUT. Varying
the analog input to CH7 alters the sequence of bits
from DOUT. A total of 18 clock cycles are required per
conversion (Figure 10). All transitions of the SSTRB and
DOUT outputs occur on the falling edge of SCLK.
MAX1148
MAX1149
CH0
ANALOG INPUT MUX
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
IN+
IN-
TRACK
HOLD
CT/H+
CT/H-
TRACK
TRACK
REF
14-BIT
CAPACITIVE
DAC
14-BIT
CAPACITIVE
DAC
REF
HOLD
HOLD
Figure 6. Equivalent Input Circuit
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
14 ______________________________________________________________________________________
BIT NAME DESCRIPTION
7 (MSB)
START
Start bit. The first logic 1 bit after CS goes low defines the beginning of the control byte.
6 SEL2
5 SEL1
4 SEL0
Channel-select bits. The channel-select bits select which of the eight channels are used for the conversion
(Tables 2, 3, 4, and 5).
3
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-ended mode,
input signal voltages are referred to COM. In differential mode, the voltage difference between two channels
is measured.
2
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, connect COM to
AGND to perform conversion from 0 to VREF. In bipolar mode, connect COM to VREF/2 to perform conversion
from 0 to VREF. See Table 7.
1 PD1
0 (LSB)
PD0
Selects clock and power-down modes.
PD1 = 0 and PD0 = 0 selects full power-down mode*.
PD1 = 0 and PD0 = 1 selects fast power-down mode*.
PD1 = 1 and PD0 = 0 selects internal clock mode.
PD1 = 1 and PD0 = 1 selects external clock mode.
Table 1. Control Byte Format
MAX1148
MAX1149
OSCILLOSCOPE
CH1 CH2 CH3 CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF HEX
SCLK
SSTRB
DOUT*
DOUT
SSTRB
SCLK
DIN
VDD
DGND
AGND
COM
0.01µF
0.01µF
2.2µF
EXTERNAL CLOCK
CH7
REFADJ
REF
MAX1149 VREF = +2.500V
MAX1148 VREF = +4.096V
VREF
AIN
VDD
10Ω
10Ω
VCOM ≤ AIN ≤ VREF
SHDN
CS
0.1µF 4.7µF
Figure 7. Quick-Look Circuit
*The start bit resets power-down modes.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 15
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1146–MAX1149 in internal
clock mode, making the MAX1146–MAX1149 ready to
convert with SSTRB high. No conversions should be
performed until the power supply is stable. The first log-
ical 1 on DIN with CS low is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, a rising edge on SCLK latches a bit from
DIN into the MAX1146–MAX1149 internal shift register.
After CS falls, the first logic 1 bit defines the control
byte’s MSB. Until this start bit arrives, any number of
logic 0 bits can be clocked into DIN with no effect.
Table 1 shows the control-byte format.
The MAX1146–MAX1149 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters. Set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI transmit a byte and receive a byte at the same
time. Using the Typical Application Circuit (Figure 4), the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the 14-bit conversion result).
SEL2
SEL1
SEL0
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
000+ -
100 + -
001 + -
101 + -
010 + -
110 + -
011 +-
111 +-
Table 2. MAX1148/MAX1149 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
000+-
001 +-
010 +-
011 +-
100- +
101 - +
110 - +
111 -+
Table 3. MAX1148/MAX1149 Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
COM
000+ -
100 + -
001 + -
101 +-
Table 4. MAX1146/MAX1147 Channel
Selection in Single-Ended Mode
(SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
000+-
001 +-
100-+
101 -+
Table 5. MAX1146/MAX1147 Channel
Selection in Differential Mode
(SGL/DIF = 0)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
16 ______________________________________________________________________________________
Digital Output
In unipolar input mode, the digital output is straight
binary (Figure 14). For bipolar input mode, the digital
output is two’s complement binary (Figure 15). Data is
clocked out on the falling edge of SCLK in MSB-first
format.
Clock Modes
The MAX1146–MAX1149 can use either the external
serial clock or the internal clock to drive the succes-
sive-approximation conversion. The external clock
shifts data in and out of the MAX1146–MAX1149.
External clock mode allows the fastest throughput rate
(116ksps) and serial clock frequencies from 0.1MHz to
2.1MHz. Internal clock mode provides the best noise
performance because the digital interface can be idle
during conversion. The internal clock mode serial clock
frequency can range from 0 to 2.1MHz. Internal clock
mode allows the CPU to request a conversion and
clock back the results.
Bits PD1 and PD0 of the control byte program the clock
and power-down modes. The MAX1146–MAX1149 power
up in internal clock mode with all circuits activated.
Figures 8–11 illustrate the available clocking modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, but it also drives the analog-to-
digital conversion. SSTRB pulses high for two clock
periods after the last bit of the control byte. Successive-
approximation bit decisions are made and the results
appear at DOUT on each of the next 14 SCLK falling
edges (Figures 8 and10). SSTRB and DOUT go into a
high-impedance state when CS is high.
Use internal clock mode if the serial clock frequency is
less than 100kHz or if serial clock interruptions could
cause the conversion interval to exceed 140µs. The
conversion must complete in 140µs, or droop on the
T/H capacitors can degrade conversion results.
Internal Clock
When configured for internal clock mode, the
MAX1146–MAX1149 generate an internal conversion
clock. This frees the µP from the burden of running the
SAR conversion clock and allows the conversion results
to be read back at the processor’s convenience, at any
clock rate up to 2.1MHz. SSTRB goes low at the start of
the conversion and then goes high when the conver-
sion is complete. SSTRB is low for a maximum of 8.0µs,
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is in
progress. SCLK clocks the data out of this register at any
time after the conversion is complete. After SSTRB goes
high, the second falling SCLK clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits in MSB-first format (Figures 9 and 11).
For the most accurate conversion, the MAX1146–
MAX1149 digital I/O should remain inactive during the
internal clock conversion interval (tCONV). Do not pull
CS high during conversion. Pulling CS high aborts the
current conversion. To ensure that the next start bit is
recognized, clock in 18 zeros at DIN. When internal
clock mode is selected, SSTRB does not go into a high-
impedance state when CS goes high. A rising edge on
SSTRB indicates that the MAX1146–MAX1149 have fin-
ished the conversion. The µP can then read the conver-
sion results at its convenience.
SCLK
SSTRB
DIN START SEL2 SEL1 SEL0 PD1 PD0
HIGH-Z
HIGH-Z
18916 24
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS CONTROL BYTE SET TO CB1
TRACK TRACKHOLD
HIGH-Z
DOUT
tACQ
HIGH-Z
tCONV
CB1
OPEN RESET TO CB1
D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0D7
CS
SGL/DIF UNI/BIP
Figure 8. External Clock Mode—24 Clocks/Conversion Timing
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 17
Applications Information
Idle Mode
The device is considered idle when all the bits have been
clocked out or 18 zeros have been clocked in on DIN.
Start Bit
The falling edge of CS alone does not start a conver-
sion. The first logic high clocked into DIN with CS low is
interpreted as a start bit and defines the first bit of the
control byte. The device begins to track on the fifth
falling edge of SCLK after a start bit has been recog-
nized. A conversion starts on the eighth falling edge of
SCLK as the last bit of the control byte is being clocked
in. The start bit is defined as follows:
1) The first high bit clocked into DIN with CS low any
time the converter is idle.
or
2) The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto DOUT
(Figures 10 and 11).
Toggling CS before the current conversion is complete
aborts the conversion and clears the output register.
The fastest the MAX1146–MAX1149 can run with CS held
low between conversions is 18 clocks per conversion.
Figures 10 and 11 show the serial-interface timing neces-
sary to perform a conversion every 18 SCLK cycles.
SCLK
SSTRB
DIN START SEL2 SEL1 SEL0 PD1 PD0
18916 24
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS CONTROL BYTE SET TO CB1
TRACK TRACKHOLD
HIGH-Z
DOUT
tACQ
HIGH-Z
tCONV
CB1
OPEN RESET TO CB1
D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D0D7
CS
SGL/DIF UNI/BIP
Figure 9. Internal Clock Mode Timing—24 Clocks/Conversion Timing
SCLK
SSTRB
DIN START SEL2 SEL1 SEL0 PD1 PD0
18
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS
CONTROL BYTE
TRACK HOLD
DOUT
HIGH-Z
14
TRACK
10 1811
HOLD
14
D13 D12
10
D5 D4
11
SET TO CB2
SET TO CB1
START SEL2 SEL1 SEL0 PD1 PD0
D13 D12 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0
START SEL2 SEL1 SEL0
15
HOLD
CS
CB1 CB2
tACQ tCONV tACQ
SGL/DIF UNI/BIP UNI/BIP
SGL/DIF UNI/BIP
SGL/DIF
Figure 10. External Clock Mode—18 Clocks/Conversion Timing
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
18 ______________________________________________________________________________________
Shutdown and Power-Down Modes
The MAX1146–MAX1149 provide a hardware shutdown
and two software power-down modes.
Pulling SHDN low places the converter in hardware
shutdown. The conversion is immediately terminated
and the supply current is reduced to 300nA. Allow 2ms
for the device to power-up when the internal reference
buffer is used with CREFADJ = 0.01µF and CREF =
2.2µF. Larger capacitors on CREFADJ and CREF
increase the power-up time (Table 6). No wake-up time
is needed for the device to power-up from fast power-
down when using an external reference.
Select a software power-down mode through the PD1
and PD0 bits of the control byte (Table 1). When the
conversion in progress is complete, software power-
down is initiated. The serial interface remains active
and the last conversion result can be clocked out. In
full power-down mode, only the serial interface remains
operational and the supply current is reduced to
300nA. In fast power-down mode, only the bandgap
reference and the serial interface remain operational,
and the supply current is reduced to 600µA.
The MAX1146–MAX1149 automatically wake up from
software power-down when they receive the control
byte’s start bit (Table 1). Allow 2ms for the device to
power-up when the internal reference buffer is used
with CREFADJ = 0.01µF and CREF = 2.2µF. Larger
capacitors on CREFADJ and CREF increase the power-
up time (Table 6). No wake-up time is needed for the
device to power-up from fast power-down when using
an external reference.
Reference Voltage
The MAX1146–MAX1149 can be used with an internal
or external reference voltage. The reference voltage
determines the ADC input range. The reference deter-
mines the full-scale output value (Table 7).
Internal Reference
The MAX1146–MAX1149 contain an internal 1.250V
bandgap reference. This bandgap reference is connect-
ed to REFADJ through a 20kΩresistor. Bypass REFADJ
with a 0.01µF capacitor to AGND. The MAX1146/
MAX1148 reference buffer has a 3.277V/V gain to pro-
vide +4.096V at REF. The MAX1147/MAX1149 reference
buffer has a 2.000V/V gain to provide +2.500V at REF.
Bypass REF with a minimum 2.2µF capacitor to AGND
when using the internal reference.
External Reference
An external reference can be applied to the
MAX1146–MAX1149 in two ways:
1) Disable the internal reference buffer by connecting
REFADJ to VDD and apply the external reference to
REF (Figure 12).
2) Utilize the internal reference buffer by applying an
external reference to REFADJ (Figure 13).
SCLK
SSTRB
DIN START SEL2 SEL1 SEL0 PD1 PD0
18
INPUT MUX
INPUT T/H
SET ACCORDING TO PREVIOUS
CONTROL BYTE
TRACK HOLD
tCONV tCONV
DOUT
HIGH-Z
tACQ
14
TRACK
D13 D12
10 18
D5 D4 D3 D2 D1 D0
11
HOLD
14
D13 D12
START
10
D5 D4
SEL2
11
TRACK
CB1 CB2
SET TO CB2SET TO CB1 RESET TO CB1
OPEN RESET TO CB2OPEN
CS
START SEL2 SEL1 SEL0 PD1 PD0
SGL/DIFUNI/BIP SGL/DIF UNI/BIP
tACQ
Figure 11. Internal Clock Mode—18 Clocks/Conversion Timing
CREFADJ*
CREF POWER-UP TIMES FROM AN
EXTENDED POWER-DOWN
0.01µF 4.7µF 2ms
0.1µF 10µF 25ms
Table 6. Internal Reference Buffer Power-
Up Times vs. Bypass Capacitors
*Power-up times are dominated by CREFADJ.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 19
Method 1 allows the direct application of an external
reference from 1.5V to VDD + 50mV. The REF input
impedance is typically 10kΩ. During conversion, an
external reference at REF must deliver up to 210µA and
have an output impedance less than 10Ω. Bypass REF
with a 0.1µF capacitor to AGND to improve its output
impedance.
Method 2 utilizes the internal reference buffer to reduce
the external reference load. The REFADJ input imped-
ance is typically 20kΩ. During a conversion, an external
reference at REFADJ must deliver at least 100µA and
have an output impedance less than 100Ω. The
MAX1146/MAX1148 reference buffer has a 3.277V/V
gain and the MAX1147/MAX1149 has a gain of
2.000V/V. The external reference voltage at REFADJ
multiplied by the reference buffer gain is the SAR ADC
reference voltage. This reference appears at REF and
must be from 1.5V to VDD + 50mV. Bypass REFADJ
with a 0.01µF capacitor and bypass REF with a 2.2µF
capacitor to AGND.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Output data coding for the MAX1146–MAX1149 is bina-
ry in unipolar mode and two’s complement binary in
bipolar mode with 1 LSB = (VREF/2N), where N is the
number of bits (14). Code transitions occur halfway
between successive-integer LSB values. Figure 14 and
Figure 15 show the input/output (I/O) transfer functions
for unipolar and bipolar operations, respectively.
Serial Interfaces
The MAX1146–MAX1149 feature a serial interface that
is fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the
serial clock for the ADCs. Select a clock frequency up
to 2.1MHz.
SPI and MICROWIRE Interface
When using an SPI (Figure 16a) or MICROWIRE interface
(Figure 16b), set CPOL = CPHA = 0. Two 8-bit readings
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
Figure 12. External Reference Applied to REF
Figure 13. Reference Adjust Circuit
UNIPOLAR MODE BIPOLAR MODE
INPUT AND OUTPUT
MODES ZERO SCALE FULL SCALE NEGATIVE FULL
SCALE ZERO SCALE POSITIVE FULL
SCALE
Single-Ended Mode VCOM VREF + VCOM VCOM
Differential Mode VIN- VREF + VIN- VIN-
Table 7. Full Scale and Zero Scale
Note: The common mode range for the analog inputs is from AGND to VDD.
−+
VV
REF COM
2
−+−
VV
REF IN
2
++
VV
REF COM
2
++−
VV
REF IN
2
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
20 ______________________________________________________________________________________
edge and is clocked into the µP on SCLK’s rising edge.
The first 8-bit data stream contains the first 8-bits of
DOUT starting with the MSB. The second 8-bit data
stream contains the remaining 6 result bits.
QSPI Interface
Using the high-speed QSPI interface (Figure 17) with
CPOL = 0 and CPHA = 0, the MAX1146–MAX1149 sup-
port a maximum fSCLK of 2.1MHz. One 16-bit reading is
necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µP on SCLK’s rising edge.
The first 14 bits are the data.
PIC16/PIC17 SSP Module Interface
The MAX1146–MAX1149 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial-port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure
18 and configure the PIC16/PIC17 as system master.
Initialize the synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 8 and 9.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings are necessary
to obtain the entire 14-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge and is
clocked into the µC on SCLK’s rising edge. The first 8-
bit data stream contains the first 8 data bits starting
with the MSB. The second data stream contains the
remaining bits, D5 through D0.
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function
Figure 16a. SPI Connections
Figure 16b. MICROWIRE Connections
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 21
Figure 17. QSPI Connections
Figure 18. SPI Interface Connection for a PIC16/PIC17
Controller
CONTROL BIT PICI6/PICI7
SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL Bit 7 X Write collision detection bit.
SSPOV Bit 6 X Receive overflow detect bit.
SSPEN Bit 5 1
Synchronous serial port enable bit:
0: Disables serial port and configures these pins as I/O port pins.
1: E nab l es ser i al p or t and confi g ur es S C K, S D O, and S C I p i ns as ser i al - p or t p i ns.
CKP Bit 4 0 Clock polarity select bit. CKP = 0 for SPI master mode selection.
SSPM3 Bit 3 0
SSPM2 Bit 2 0
SSPM1 Bit 1 0
SSPM0 Bit 0 1
Synchronous serial port mode select bit. Sets SPI master mode and selects
FCLK = fOSC / 16.
Table 8. Detailed SSPCON Register Content
CONTROL BIT
MAX1146–MAX1149
SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP Bit 7 0 SPI data input sample phase. Input data is sampled at the middle of the data
output time.
CKE Bit 6 1 SPI clock edge select bit. Data is transmitted on the rising edge of the serial
clock.
D/A Bit 5 X Data address bit.
P Bit 4 X Stop bit.
S Bit 3 X Start bit.
R/W Bit 2 X Read/write bit information.
UA Bit 1 X Update address.
BF Bit 0 X Buffer full status bit.
Table 9. Detailed SSPSTAT Register Content
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
22 ______________________________________________________________________________________
TMS32OLC3x Interface
Figure 19 shows an application circuit to interface the
MAX1146–MAX1149 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 20. Use the following steps to initiate a
conversion in the MAX1146–MAX1149 and to read the
results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected together with the MAX1146–MAX1149
SCLK input.
2) Drive the CS of the MAX1146–MAX1149 low
through the XF_ I/O port of the TMS320 to clock
data into the MAX1146–MAX1149 DIN.
3) Write an 8-bit word (1XXXXX11) to the
MAX1146–MAX1149 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1146–MAX1149 SSTRB output is moni-
tored by the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the con-
version is in progress and data is ready to be
received from the MAX1146–MAX1149.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 14-bit conversion result followed by 2
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1146–MAX1149
until the next conversion is initiated.
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
performance. Boards should have separate analog and
digital ground planes. Ensure that digital and analog
signals are separated from each other. Do not run ana-
log and digital (especially clock) lines parallel to one
another, or digital lines underneath the device pack-
age.
Figure 4 shows the recommended system ground con-
nections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground point to the analog ground point directly at the
device. For lowest noise operation, the ground return to
the star ground’s power supply should be low imped-
ance and as short as possible.
Figure 19. MAX1146–MAX1149-to-TMS320 Serial Interface
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 PD1 PD0
MSB B12 B1 LSB
HIGH-Z
HIGH-Z
CS
SGL/DIF UNI/BIP
Figure 20. TMS320 Serial-Interface Timing Diagram
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
______________________________________________________________________________________ 23
High-frequency noise in the VDD power supply degrades
the device’s high-speed performance. Bypass the sup-
ply to the digital ground with 0.1µF and 4.7µF capacitors.
Minimize capacitor lead lengths for best supply-noise
rejection. Connect a 10Ωresistor in series with the 0.1µF
capacitor to form a lowpass filter when the power supply
is noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1146–MAX1149
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples. Aperture delay (tAD) is
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Chip Information
TRANSISTOR COUNT: 5589
PROCESS: BiCMOS
THD VVVV
V
log
=× +++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20 22324252
1
Revision History
Pages changed at Rev 2: 1, 20, 23, 25.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
24 ______________________________________________________________________________________
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
SCLK
DINCH3
CH1
CH0
TOP VIEW
SSTRB
DOUT
DGND
AGNDN.C.
N.C.
N.C.
N.C.
12
11
9
10
REFADJ
REF
COM
MAX1146
MAX1147
TSSOP
SHDN
CS
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
VDD
SCLK
DINCH3
CH2
CH1
CH0
SSTRB
DOUT
DGND
AGNDCH7
CH6
CH5
CH4
12
11
9
10
REFADJ
REF
COM
MAX1148
MAX1149
TSSOP
SHDN
CS
CH2
Pin Configurations
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
1
1
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MAX1146, MAX1147, MAX1148, MAX1149
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