HCPL-786J-500E - Avago Technologies

Description

The HCPL-7860/HCPL-786J Optically Isolated Modulator

and HCPL-0872 Digital Interface IC or digital lter together

form an isolated programmable two-chip analog-to-digital

converter. The isolated modulator allows direct measure-

ment of motor phase currents in power inverters.

In operation, the HCPL-7860/HCPL-786J Isolated Modula-

tor converts a low-bandwidth analog input into a high-

speed one-bit data stream by means of a Sigma-Delta

(6') over-sampling modulator. This modulation provides

for high noise margins and excellent immunity against

isolation-mode transients. The modulator data and on-

chip sampling clock are encoded and transmitted across

the isolation boundary where they are recovered and de-

coded into separate high-speed clock and data channels.

NOTE: A 0.1 F bypass capacitor must be connected between pins VDD1 and GND1 and between pins VDD2 and GND2.

SIGMA

DELTA

MOD./

ENCODE

DECODE

Input

Current

HCPL-0872

Digital Filter

MCU

DSP

HCPL-7860

HCPL-7860/HCPL-786J

Optically Isolated Sigma-Delta (S-D) Modulator

Data Sheet

Features

x12-bit Linearity

x200 ns Conversion Time

(Pre-Trigger Mode 2 with HCPL-0872)

x12-bit Eective Resolution with 5 Ps Signal Delay

(14-bit with 102 Ps) (with HCPL-0872)

xFast 3 Ps Over-Range Detection (with HCPL-0872)

x± 200 mV Input Range with Single 5 V Supply

x1% Internal Reference Voltage Matching

xOset Calibration (with HCPL-0872)

x-40°C to +85°C Operating Temperature Range

x15 kV/Ps Isolation Transient Immunity

xSafety Approval: UL 1577, CSA and IEC/EN/DIN EN

60747-5-2

Applications

x Motor Phase and Rail Current Sensing

x Data Acquisition Systems

x Industrial Process Control

x Inverter Current Sensing

x General Purpose Current Sensing and Monitoring

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation, which may be induced by ESD.

Pin Description

Symbol Description Symbol Description

VDD1 Supply voltage input (4.5 V to 5.5 V) VDD2 Supply voltage input (4.5 V to 5.5 V)

VIN+ Positive input (± 200 mV recommended) MCLK Clock output (10 MHz typical)

VIN- Negative input (normally connected to GND1) MDAT Serial data output

GND1 Input ground GND2 Output ground

HCPL-7860

VDD1

VIN+

VIN-

GND1

VDD2

MCLK

MDAT

GND2

SHIELD

ISOLATION

BOUNDARY

DECODE

SIGMA-

DELTA

MOD./

ENCODE

MDAT

710

NC NC

GND1 GND2

VDD1

VIN+

GND2

314

VIN- VDD2

413

NC MCLK

SIGMA-

DELTA

MOD./

ENCODER

DECODER

HCPL-786J

Ordering Information

HCPL-7860 is UL Recognized with 3750 Vrms for 1 minute per UL1577. HCPL-786J is UL Recognized with 5000 Vrms for

1 minute per UL1577.

Part number

Option

Package

Surface

Mount

Gull

Wing

Tape

& Reel

IEC/EN/DIN EN

60747-5-2 Quantity

RoHS

Compliant

Non-RoHS

Compliant

HCPL-7860 -000E No option 300 mil

DIP-8

X 50 per tube

-300E #300 X X X 50 per tube

-500E #500 X X X X 1000 per reel

HCPL-786J -000E No option SO-16 X 45 per tube

-500E #500 X X X 850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

HCPL-7860-500E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN

EN 60747-5-2 Safety Approval in RoHS compliant.

Example 2:

HCPL-786J to order product of SO-16 package in tube packaging and non-RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS

compliant option will use ‘-XXXE’.

Note: NC = No connection. Leave oating.

Package Outline Drawings

8-pin DIP Package

9.80 ± 0.25

(0.386 ± 0.010)

PIN ONE

1.78 (0.070) MAX.

1.19 (0.047) MAX.

A 7860X

YYWW

DATE CODE

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

5° TYP.

7.62 ± 0.25

(0.300 ± 0.010)

5678

4321

REFERENCE VOLTAGE

MATCHING SUFFIX*

TYPE NUMBER

3.56 ± 0.13

(0.140 ± 0.005)

6.35 ± 0.25

(0.250 ± 0.010)

0.20 (0.008)

0.33 (0.013)

2.54 ± 0.25

(0.100 ± 0.010)

1.080 ± 0.320

(0.043 ± 0.013)

DIMENSIONS IN MILLIMETERS AND (INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20mils) MAX.

NOTE: INITIAL OR CONTINUED VARIATION IN THE COLOUR OF THE HCPL-7860/HCPL-786J’S WHITE MOLD

COMPOUND ISNORMAL AND DOES NOT AFFECT DEVICE PERFORMANCE OR RELIABILITY.

*ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER

REEL) HAVEA COMMON MARKING SUFFIX TO REPRESENT A REFERENCE VOLTAGE MATCHING OF ± 1%. AN

ABSOLUTEREFERENCE VOLTAGE TOLERANCE OF ± 4% IS GUARANTEED BETWEEN STANDARD PACKAGING

INCREMENTS.

8-pin Gull Wing Surface Mount Option 300

16-Lead Surface Mount

0.635 ± 0.25

(0.025 ± 0.010) 12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.51 ± 0.130

(0.020 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

9.80 ± 0.25

(0.386 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.27 (0.050)

10.9 (0.430)

2.0 (0.080)

LAND PATTERN RECOMMENDATION

1.080 ± 0.320

(0.043 ± 0.013)

3.56 ± 0.13

(0.140 ± 0.005)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.540

(0.100)

BSC

0.20 (0.008)

0.33 (0.013)

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

DIMENSIONS IN MILLIMETERS (INCHES).

TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01

xx.xxx = 0.005

LEAD COPLANARITY

MAXIMUM: 0.102 (0.004)

7.493 ± 0.254

(0.295 ± 0.010)

10111213141516

87654321

0.457

(0.018)

3.505 ± 0.127

(0.138 ± 0.005)

9°

10.312 ± 0.254

(0.406 ± 0.10)

10.363 ± 0.254

(0.408 ± 0.010)

0.025 MIN.

0.203 ± 0.076

(0.008 ± 0.003)

STANDOFF

8.763 ± 0.254

(0.345 ± 0.010)

0-8°

0.457

(0.018)

1.270

(0.050)

ALL LEADS

TO BE

COPLANAR

± 0.002

A 786J

YYWW

TYPE NUMBER

DATE CODE

DIMENSIONS IN MILLIMETERS AND (INCHES).

NOTE: Initial and continued variation in the color of the HCPL-786J's white mold compound is normal

and does not aect device performance or reliability.

NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.

11.63 (0.458)

2.16 (0.085)

0.64 (0.025)

LAND PATTERN RECOMMENDATION

Solder Reow Temperature Prole

Recommended Lead Free IR Prole

217˚C

RAMP-DOWN

6˚C/SEC. MAX.

RAMP-UP

3˚C/SEC. MAX.

150 - 200˚C

260 +0/-5˚C

t 25˚C to PEAK

60 to 150 SEC.

20-40 SEC.

TIME WITHIN 5˚C of ACTUAL

PEAK TEMPERATURE

PREHEAT

60 to 180 SEC.

smax

smin

TIME (SECONDS)

TEMPERATURE (˚C)

NOTES:

THE TIME FROM 25˚C to PEAK TEMPERATURE = 8 MINUTES MAX.

smax

= 200˚C, T

smin

= 150˚C

Approval under UL 1577, component recognition pro-

gram. File E55361.

CSA

Approval under CSA Component Acceptance Notice #5,

File CA 88324.

IEC/EN/DIN EN 60747-5-2

Approved under:

IEC 60747-5-2:1997 + A1:2002

EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2

(VDE 0884 Teil 2):2003-01.

Regulatory Information

The HCPL-7860/HCPL-786J has been approved by the following organizations:

TIME (SECONDS)

TEMPERATURE (˚C)

200

100

50 150100 200 250

300

SEC.

50 SEC.

SEC.

160˚C

140˚C

150˚C

PEAK

TEMP.

245˚C

PEAK

TEMP.

240˚C

PEAK

TEMP.

230˚C

SOLDERING

TIME

200˚C

PREHEATING TIME

150˚C, 90 + 30 SEC.

2.5˚C ± 0.5˚C/SEC.

3˚C + 1˚C/-0.5˚C

TIGHT

TYPICAL

LOOSE

ROOM

TEMPERATURE

PREHEATING RATE 3˚C + 1˚C/-0.5˚C/SEC.

REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC.

Note: Use of non-chlorine-activated uxes is highly recommended.

Notes:

1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must

be ensured by protective circuits within the application. Surface Mount Classications is Class

A in accordance with CECC00802.

2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog,

under Product Safety Regulations section, (IEC/EN/DIN EN 60747-5-2) for a detailed descrip-

tion of Method a and Method b partial discharge test proles.

3. Refer to the following gure for dependence of PS and IS on ambient temperature.

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics[1]

Description Symbol HCPL-7860 HCPL-786J Unit

Installation classication per DIN VDE 0110/1.89, Table 1

for rated mains voltage d 300 Vrms

for rated mains voltage d 450 Vrms

for rated mains voltage d 600 Vrms

for rated mains voltage d 1000 Vrms

I - IV

I - III

I - II

I - IV

I - III

Climatic Classication 40/85/21 40/85/21

Pollution Degree (DIN VDE 0110/1.89) 2 2

Maximum Working Insulation Voltage VIORM 891 1230 Vpeak

Input to Output Test Voltage, Method b [2]

VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,

Partial discharge < 5 pC

VPR 1670 2306 Vpeak

Input to Output Test Voltage, Method a[2]

VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec,

Partial discharge < 5 pC

VPR 1425 1968 Vpeak

Highest Allowable Overvoltage(Transient Overvoltage tini = 60 sec) VIOTM 6000 8000 Vpeak

Safety-limiting values - maximum values allowed in the event of a failure.

Case Temperature

Input Current [3]

Output Power [3]

IS, INPUT

PS, OUTPUT

175

400

600

175

400

600

°C

Insulation Resistance at TS, VIO = 500 V RS>109>109:

Insulation and Safety Related Specications

Option 300 - surface mount classication is Class A in accordance with CECC 00802.

Parameter Symbol DIP-8 SO-16 Units Conditions

Minimum External Air Gap

(Clearance)

L(101) 7.4 8.3 mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking

(Creepage)

L(102) 8.0 8.3 mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic

Gap (Internal Clearance)

0.5 0.5 mm Through insulation distance conductor to conductor,

usually the straight line distance thickness between

the emitter and detector.

Tracking Resistance

(Comparative Tracking

Index)

CTI >175 >175 V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

OUTPUT POWER - P

, INPUT CURRENT - I

- CASE TEMPERATURE -

20050

400

12525 75 100 150

600

800

200

100

300

500

700

175

(mW)

(mA)

Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note

Storage Temperature TS-55 125 °C

Ambient Operating Temperature TA-40 85 °C

Supply Voltages VDD1, VDD2 0 5.5 V

Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 + 0.5 V 1

Two Second Transient Input Voltage -6.0

Output Voltages MCLK, MDAT -0.5 VDD2 + 0.5 V

Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

Solder Reow Temperature Prole See Maximum Solder Reow Thermal Prole section

Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note

Ambient Operating Temperature TA-40 +85 °C

Supply Voltages VDD1, VDD2 4.5 5.5 V

Input Voltage VIN+, VIN- -200 +200 mV 1

Electrical Specications (DC)

Unless otherwise noted, all specications are at VIN+ = 0 V and VIN- = 0 V, all Typical specications are at TA = 25°C and

VDD1 = VDD2 = 5 V, and all Minimum and Maximum specications apply over the following ranges: TA = -40°C to +85°C,

VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

Average Input Bias Current IIN -0.8 µA 1 3

Average Input Resistance RIN 450 k :3

Input DC Common-Mode

Rejection Ratio

CMRRIN 60 dB 4

Output Logic High Voltage VOH 3.9 4.9 V IOUT = -100 µA

Output Logic Low Voltage VOL 0.1 0.6 V IOUT = 1.6 mA

Output Short Circuit Current |IOSC|30 mAV

OUT = VDD2

or GND2

Input Supply Current IDD1 10 15 mA VIN+ = -350 mV

to +350 mV

Output Supply Current IDD2 10 15 mA 3

Output Clock Frequency fCLK 8.2 10 13.2 MHz 4

Data Hold Time tHDDAT 15 ns 6

Electrical Specications (Tested with HCPL-0872 or Sinc3 Filter)

Unless otherwise noted, all specications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical specications are

at TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specications apply over the following ranges: TA =

-40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.

STATIC CHARACTERISTICS

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

Resolution 15 bits 7

Integral Nonlinearity INL 3 30 LSB 5 8

0.01 0.14 % 6 8

Dierential Nonlinearity DNL 1 LSB 9

Uncalibrated Input Oset VOS -3 0 3 mV VIN+ = 0 V 7

Oset Drift vs. Temperature dVOS/dTA2 10 µV/°C VIN+ = 0 V 7 10

Oset drift vs. VDD1 dVOS/dVDD1 0.12 mV/V VIN+ = 0 V 7

Internal Reference Voltage VREF 320 mV 8

Absolute Reference Voltage Tolerance -4 4 % 8 2

Reference Voltage

Matching

HCPL-7860 -1 1 % TA = 25°C. 8 2

HCPL-786J -2 2 %

VREF Drift vs. Temperature dVREF/dTA60 ppm/°C. 8

VREF Drift vs. VDD1 dVREF/dVDD1 0.2 % 8

Full Scale Input Range -VREF +VREF mV 11

Recommended Input Voltage Range -200 +200 mV

DYNAMIC CHARACTERISTICS (Digital Interface IC HCPL-0872 is set to Conversion Mode 3.)

Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note

Signal-to-Noise Ratio SNR 62 73 dB VIN+ = 35 Hz,

400 mVpk-pk

(141 mVrms)

sine wave.

9,10

Total Harmonic Distortion THD -67 dB

Signal-to-(Noise + Distortion) SND 66 dB

Eective Number of Bits ENOB 10 12 bits 11 12

Conversion Time tC2 0.2 0.8 µs Pre-Trigger Mode 2 1,12 13

tC1 19 23 µs Pre-Trigger Mode 1 1,12 13

tC0 39 47 µs Pre-Trigger Mode 0 1,12

Signal Delay tDSIG 19 23 µs 13 14

Over-Range Detect Time tOVR1 2.0 3.0 4.2 µs VIN+ = 0 to 400mV

step waveform

14 15

Threshold Detect Time (default

conguration)

tTHR1 10 µs 16

Signal Bandwidth BW 18 22 kHz 15 17

Isolation Transient Immunity CMR 15 20 kV/µs VISO = 1 kV 18

Package Characteristics

Parameter Symbol Device Min. Typ. Max. Units Conditions Note

Input-Output Momentary

Withstand Voltage*

VISO HCPL-7860 3750 Vrms RH ≤ 50%, t = 1 min;

TA = 25°C

19, 20

HCPL-786J 5000

Input-Output Resistance RI-O 1012 1013 :VI-O = 500 Vdc 20

1011 TA = 100°C

Input-Output Capacitance CI-O 1.4 pF f = 1 MHz 20

Input IC Junction-to-Case

Thermal Resistance

Tjci 96 °C/W Thermocouple located at center

underside of package

Output IC Junction-to-Case

Thermal Resistance

Tjco 114 °C/W

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage

rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level

safety specication, or Avago Technologies Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”

Notes:

1. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test mode is not

intended for customer use.

2. All units within each HCPL-7860 standard packaging increment (either 50 per tube or 1000 per reel) have a Reference Voltage Matching of ± 1%.

An Absolute Reference Voltage Tolerance of ± 4% is guaranteed between standard packaging increments.

3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.

4. CMRRIN is dened as the ratio of the gain for dierential inputs applied between VIN+ and VIN- to the gain for common-mode inputs applied to both

VIN+ and VIN- with respect to input ground GND1.

5. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or GND2. Use under these conditions is not

recommended.

6. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.

7. Resolution is dened as the total number of output bits. The useable accuracy of any A/D converter is a function of its linearity and signal-to-noise

ratio, rather than how many total bits it has.

8. Integral nonlinearity is dened as one-half the peak-to-peak deviation of the best-t line through the transfer curve for VIN+ = -200 mV to +200 mV,

expressed either as the number of LSBs or as a percent of measured input range (400 mV).

9. Dierential nonlinearity is dened as the deviation of the actual dierence from the ideal dierence between midpoints of successive output codes,

expressed in LSBs.

10. Data sheet value is the average magnitude of the dierence in oset voltage from TA =25°C to TA= 85°C, expressed in microvolts per °C. Three

standard deviation from typical value is less than 6 PV/°C.

11. Beyond the full-scale input range the output is either all zeroes or all ones.

12. The eective number of bits (or eective resolution) is dened by the equation ENOB = (SNR-1.76)/6.02 and represents the resolution of an ideal,

quantization-noise limited A/D converter with the same SNR.

13. Conversion time is dened as the time from when the convert start signal CS is brought low to when SDAT goes high, indicating that output data

is ready to be clocked out. This can be as small as a few cycles of the isolated modulator clock and is determined by the frequency of the isolated

modulator clock and the selected Conversion and Pre-Trigger modes. For determining the true signal delay characteristics of the A/D converter for

closed-loop phase margin calculations, the signal delay specication should be used.

14. Signal delay is dened as the eective delay of the input signal through the Isolated A/D converter. It can be measured by applying a -200 mV to

± 200 mV step at the input of modulator and adjusting the relative delay of the convert start signal CS so that the output of the converter is at mid

scale. The signal delay is the elapsed time from when the step signal is applied at the input to when output data is ready at the end of the conver-

sion cycle. The signal delay is the most important specication for determining the true signal delay characteristics of the A/D converter and should

be used for determining phase margins in closed-loop applications. The signal delay is determined by the frequency of the modulator clock and

which Conversion Mode is selected, and is independent of the selected Pre-Trigger Mode and, therefore, conversion time.

15. The minimum and maximum overrange detection time is determined by the frequency of the channel 1 isolated modulator clock.

16. The minimum and maximum threshold detection time is determined by the user-dened conguration of the adjustable threshold detection circuit

and the frequency of the channel 1 isolated modulator clock. See the Applications Information section for further detail. The specied times apply

for the default conguration.

17. The signal bandwidth is the frequency at which the magnitude of the output signal has decreased 3 dB below its low-frequency value. The signal

bandwidth is determined by the frequency of the modulator clock and the selected Conversion Mode.

18. The isolation transient immunity (also known as Common-Mode Rejection) species the minimum rate-of-rise of an isolation-mode signal applied

across the isolation boundary beyond which the modulator clock or data signals are corrupted.

19. In accordance with UL1577, for devices with minimum VISO specied at 3750 Vrms(HCPL-7860) or 5000 Vmrs (HCPL-786J) , each isolated modulator

(optocoupler) is proof-tested by applying an insulation test voltage greater than 4500 Vrms (HCPL-7860) or 6000 Vrms (HCPl-786J) for one second.

This test is performed before the Method b, 100% production test for partial discharge shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristics

Table.

20. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.

Figure 1. IIN vs. VIN. Figure 2. IDD1 vs. VIN.

Figure 3. IDD2 vs. VIN. Figure 4. Clock Frequency vs. Temperature.

Figure 5. INL (Bits) vs. Temperature Figure 6. INL (%) vs. Temperature

IIN - mA

VIN - V

-4

-5

-4

-9

-2

-6 6-2 2

-1

-3

-8

-6

-7

IDD1 - mA

VIN - mV

9.0

8.5

-200

10.5

200

8.0

9.5

-40 °C

10.0

-400 4000

25 °C

85 °C

IDD2 - mA

VIN - mV

8.6

8.2

-200

9.4

200

8.0

8.8

-40 °C

9.2

-400 4000

25 °C

85 °C

8.4

9.0

CLOCK FREQUENCY - MHz

TEMPERATURE - °C

9.2

-15

10.0

8.6

9.4

9.8

-40 8510 35

8.8

9.0

9.6

VDD1 = 4.5 V

VDD1 = 5.0 V

VDD1 = 5.5 V

INL-LSB

TEMPERATURE - °C

-15

VDD1 = 4.5 V

-40 8510 35

VDD1 = 5.0 V

VDD1 = 5.5 V

INL-%

TEMPERATURE - °C

0.012

-15

0.02

0.006

0.014

VDD1 = 4.5 V

0.016

-40 8510 35

VDD1 = 5.0 V

VDD1 = 5.5 V

0.008

0.018

0.01

Figure 10. SNR vs. Conversion Mode.

Figure 11. Eective Resolution vs. Conversion Mode. Figure 12. Conversion Time vs. Conversion Mode.

Figure 7. Oset Change vs. Temperature Figure 8. VREF Change vs. Temperature

Figure 9. SNR vs. Temperature

OFFSET CHANGE - μV

TEMPERATURE - °C

-50

-15

150

-150

VDD1 = 4.5 V

100

-40 8510 35

VDD1 = 5.0 V

VDD1 = 5.5 V

-100

VREF CHANGE - %

TEMPERATURE - °C

-15

0.8

-0.4

0.2

VDD1 = 4.5 V

0.6

-40 8510 35

VDD1 = 5.0 V

VDD1 = 5.5 V

-0.2

0.4

SNR

TEMPERATURE - °C

-15

VDD1 = 4.5 V

-40 8510 35

VDD1 = 5.0 V

VDD1 = 5.5 V

SNR

CONVERSION MODE #

EFFECTIVE RESOLUTION (# BITS)

CONVERSION MODE #

CONVERSION TIME - μs

CONVERSION MODE #

100

200

140

PRE-TRIGGER MODE 2

180

160

120

PRE-TRIGGER MODE 0

PRE-TRIGGER MODE 1

Application Information

Digital Current Sensing

As shown in Figure 16, using the Isolated 2-chip A/D con-

verter to sense current can be as simple as connecting a

current-sensing resistor, or shunt, to the input and reading

output data through the 3-wire serial output interface.

By choosing the appropriate shunt resistance, any range

of current can be monitored, from less than 1 A to more

than 100 A.

Even better performance can be achieved by fully utilizing

the more advanced features of the Isolated A/D converter,

such as the pre-trigger circuit, which can reduce conver-

sion time to less than 1 Ps, the fast over-range detector

for quickly detecting short circuits, dierent conversion

modes giving various resolution/speed trade-os, oset

calibration mode to eliminate initial oset from measure-

ments, and an adjustable threshold detector for detecting

non-short circuit overload conditions.

Figure 16. Typical Application Circuit.

RSHUNT

0.02

INPUT

CURRENT

VDD1

ISOLATED

+ 5 V

VIN+

VIN-

GND1

VDD2

MCLK

MDAT

GND2

0.1 μF

+CDAT SCLK

CCLK V DD

CLAT CHAN

MCLK1 SDAT

MDAT1 CS

MCLK2 THR1

MDAT2 OVR1

GND RESET

NON-ISOLATED

+ 5 V

10 μF

HCPL-7860/

HCPL-786J

3-WIRE

SERIAL

INTERFACE

0.1 μF

HCPL-0872

Figure 13. Signal Delay vs. Conversion Mode. Figure 14. Over-Range and Threshold Detect Times.

Figure 15. Signal Bandwidth vs. Conversion Mode.

SIGNAL DELAY - μs

CONVERSION MODE #

100

45 2 μs/DIV.

VIN+ (200 mV/DIV.)

OVR1 (200 mV/DIV.)

THR1

(2 V/DIV.)

SIGNAL BANDWIDTH - kHz

CONVERSION MODE #

100

Product Description

The HCPL-7860/HCPL-786J Isolated Modulator (optocou-

pler) uses sigma-delta modulation to convert an analog

input signal into a high-speed (10 MHz) single-bit digital

data stream; the time average of the modulator’s single-

bit data is directly proportional to the input signal. The

isolated modulator’s other main function is to provide

galvanic isolation between the analog input and the digital

output. An internal voltage reference determines the full-

scale analog input range of the modulator (approximately

± 320 mV); an input range of ± 200 mV is recommended

to achieve optimal performance.

HCPL-7860/HCPL-786J can be used together with HCPL-

0872, Digital Interface IC or a digital lter. The primary

functions of the HCPL-0872 Digital Interface IC are to de-

rive a multi-bit output signal by averaging the single-bit

modulator data, as well as to provide a direct microcon-

troller interface. The eective resolution of the multi-bit

output signal is a function of the length of time (measured

in modulator clock cycles) over which the average is taken;

averaging over longer periods of time results in higher

resolution. The Digital Interface IC can be congured for

ve conversion modes, which have dierent combina-

tions of speed and resolution to achieve the desired level

of performance. Other functions of the HCPL-0872 Digital

Interface IC include a Phase Locked Loop based pre-trigger

circuit that can either give more precise control of the ef-

fective sampling time or reduce conversion time to less

than 1 Ps, a fast over-range detection circuit that rapidly

indicates when the magnitude of the input signal is be-

yond full-scale, an adjustable threshold detection circuit

that indicates when the magnitude of the input signal is

above a user adjustable threshold level, an oset calibra-

tion circuit, and a second multiplexed input that allows a

second Isolated Modulator to be used with a single Digital

Interface IC.

The digital output format of the Isolated A/D Converter is

15 bits of unsigned binary data. The input full-scale range

and code assignment is shown in Table 1 below. Although

the output contains 15 bits of data, the eective resolution

is lower and is determined by selected conversion mode as

shown in Table 2 below.

Table 1. Input Full-Scale Range and Code Assignment.

Analog Input Voltage Input Digital Output

Full Scale Range 640 mV 32768 LSBs

Minimum Step Size 20 µV 1 LSB

+Full Scale +320 mV 111111111111111

Zero 0 mV 100000000000000

-Full Scale -320 mV 000000000000000

Table 2. Isolated A/D Converter Typical Performance Characteristics.

Conversion Mode

Signal-to-

Noise Ratio

(dB)

Eective

Resolution

(bits)

Conversion Time (μs)

Signal

Delay(μs)

Signal Band-

width (kHz)

Pre-Trigger Mode

012

1 83 13.5 205 102

0.2

102 3.4

2 79 12.8 103 51 51 6.9

3 73 11.9 39 19 19 22

4 66 10.7 20 10 10 45

5 53 8.5 10 5 5 90

Notes: Bold italic type indicates Default values.

Figure 17. Recommended Application Circuit.

MOTOR

HV-

HV+

SENSE

FLOATING

POSITIVE

SUPPLY

GATE DRIVE

CIRCUIT

DD1

IN+

IN-

GND1

DD2

MCLK

MDAT

GND2

CDAT SCLK

CCLK V

CLAT CHAN

MCLK1 SDAT

MDAT1 CS

MCLK2 THR1

MDAT2 OVR1

GND RESET

+ 5 V

HCPL-7860/

HCPL-786J

CONTROL

CIRCUIT

0.1 μF

0.01 μF

R2 39 Ω

5.1 V

HCPL-0872

Power Supplies and Bypassing

The recommended application circuit is shown in Figure

17. A oating power supply (which in many applications

could be the same supply that is used to drive the high-

side power transistor) is regulated to 5 V using a simple

zener diode (D1); the value of resistor R1 should be chosen

to supply sucient current from the existing oating sup-

ply. The voltage from the current sensing resistor or shunt

(Rsense) is applied to the input of the HCPL-7860/HCPL-

786J (U2) through an RC anti-aliasing lter (R2 and C2). And

nally, the output clock and data of the isolated modulator

are connected to the digital interface IC. Although the

application circuit is relatively simple, a few recommenda-

tions should be followed to ensure optimal performance.

The power supply for the isolated modulator is most

often obtained from the same supply used to power the

power transistor gate drive circuit. If a dedicated supply is

required, in many cases it is possible to add an additional

winding on an existing transformer. Otherwise, some sort

of simple isolated supply can be used, such as a line pow-

ered transformer or a high-frequency DC-DC converter.

An inexpensive 78L05 three-terminal regulator can also be

used to reduce the oating supply voltage to 5 V. To help

attenuate high-frequency power supply noise or ripple, a

resistor or inductor can be used in series with the input of

the regulator to form a low-pass lter with the regulator’s

input bypass capacitor.

As shown in Figure 17, 0.1 PF bypass capacitors (C1 and

C3) should be located as close as possible to the input

and output power-supply pins of the isolated modulator

(U2). The bypass capacitors are required because of the

high-speed digital nature of the signals inside the isolated

modulator. A 0.01 PF bypass capacitor (C2) is also recom-

mended at the input due to the switched-capacitor nature

of the input circuit. The input bypass capacitor also forms

part of the anti-aliasing lter, which is recommended to

prevent high-frequency noise from aliasing down to lower

frequencies and interfering with the input signal.

Figure 18. Motor Output Horsepower vs. Motor Phase Current and Supply

Voltage.

PC Board Layout

The design of the printed circuit board (PCB) should follow

good layout practices, such as keeping bypass capacitors

close to the supply pins, keeping output signals away

from input signals, the use of ground and power planes,

etc. In addition, the layout of the PCB can also aect the

isolation transient immunity (CMR) of the isolated modu-

lator, due primarily to stray capacitive coupling between

the input and the output circuits. To obtain optimal CMR

performance, the layout of the PC board should minimize

any stray coupling by maintaining the maximum possible

distance between the input and output sides of the circuit

and ensuring that any ground or power plane on the PC

board does not pass directly below or extend much wider

than the body of the isolated modulator.

Shunt Resistors

The current-sensing shunt resistor should have low re-

sistance (to minimize power dissipation), low inductance

(to minimize di/dt induced voltage spikes which could

adversely aect operation), and reasonable tolerance (to

maintain overall circuit accuracy). Choosing a particular

value for the shunt is usually a compromise between

minimizing power dissipation and maximizing accuracy.

Smaller shunt resistances decrease power dissipation,

while larger shunt resistances can improve circuit accuracy

by utilizing the full input range of the isolated modulator.

The rst step in selecting a shunt is determining how much

current the shunt will be sensing. The graph in Figure 18

shows the RMS current in each phase of a three-phase

induction motor as a function of average motor output

power (in horsepower, hp) and motor drive supply volt-

age. The maximum value of the shunt is determined by the

current being measured and the maximum recommended

input voltage of the isolated modulator. The maximum

shunt resistance can be calculated by taking the maximum

recommended input voltage and dividing by the peak cur-

rent that the shunt should see during normal operation.

For example, if a motor will have a maximum RMS current

of 10 A and can experience up to 50% overloads during

normal operation, then the peak current is 21.1 A (= 10 x

1.414 x 1.5). Assuming a maximum input voltage of 200

mV, the maximum value of shunt resistance in this case

would be about 10 m:.

The maximum average power dissipation in the shunt

can also be easily calculated by multiplying the shunt

resistance times the square of the maximum RMS current,

which is about 1 W in the previous example.

If the power dissipation in the shunt is too high, the resis-

tance of the shunt can be decreased below the maximum

value to decrease power dissipation. The minimum value

of the shunt is limited by precision and accuracy require-

ments of the design. As the shunt value is reduced, the

output voltage across the shunt is also reduced, which

means that the oset and noise, which are xed, become

a larger percentage of the signal amplitude. The selected

value of the shunt will fall somewhere between the mini-

mum and maximum values, depending on the particular

requirements of a specic design.

When sensing currents large enough to cause signicant

heating of the shunt, the temperature coecient (tempco)

of the shunt can introduce nonlinearity due to the sig-

nal dependent temperature rise of the shunt. The eect

increases as the shunt-to-ambient thermal resistance

increases. This eect can be minimized either by reducing

the thermal resistance of the shunt or by using a shunt

with a lower tempco. Lowering the thermal resistance can

be accomplished by repositioning the shunt on the PC

board, by using larger PC board traces to carry away more

heat, or by using a heat sink.

15 20 25 30

MOTOR PHASE CURRENT - A (rms)

MOTOR OUTPUT POWER - HORSEPOWER

5350

440

380

220

120

Table 3. Isotek (Isabellenhütte) Four-Terminal Shunt Summary.

Shunt Resistor

Part Number

Shunt Resistance Tol.

Maximum RMS Cur-

rent

Motor Power Range

120 VAC - 440 VAC

m:% A hp kW

PBV-R050-0.5 50 0.5 3 0.8 - 3 0.6 - 2

PBV-R020-0.5 20 0.5 7 2 - 7 0.6 - 2

PBV-R010-0.5 10 0.5 14 4 - 14 3 - 10

PBV-R005-0.5 5 0.5 25 [28] 7 - 25 [8 - 28] 5 - 19 [6 - 21]

PBV-R002-0.5 2 0.5 39 [71] 11 - 39 [19 - 71] 8 - 29 [14 - 53]

Note: Values in brackets are with a heatsink for the shunt.

For a two-terminal shunt, as the value of shunt resistance

decreases, the resistance of the leads becomes a signi-

cant percentage of the total shunt resistance. This has two

primary eects on shunt accuracy. First, the eective resis-

tance of the shunt can become dependent on factors such

as how long the leads are, how they are bent, how far they

are inserted into the board, and how far solder wicks up

the lead during assembly (these issues will be discussed in

more detail shortly). Second, the leads are typically made

from a material such as copper, which has a much higher

tempco than the material from which the resistive element

itself is made, resulting in a higher tempco for the shunt

overall. Both of these eects are eliminated when a four-

terminal shunt is used. A four-terminal shunt has two ad-

ditional terminals that are Kelvin-connected directly across

the resistive element itself; these two terminals are used

to monitor the voltage across the resistive element while

the other two terminals are used to carry the load current.

Because of the Kelvin connection, any voltage drops across

the leads carrying the load current should have no impact

on the measured voltage.

Several four-terminal shunts from Isotek (Isabellenhütte)

suitable for sensing currents in motor drives up to 71

Arms (71 hp or 53 kW) are shown in Table 3; the maximum

current and motor power range for each of the PBV series

shunts are indicated. For shunt resistances from 50 m:

down to 10 m:, the maximum current is limited by the

input voltage range of the isolated modulator. For the 5

m: and 2 m: shunts, a heat sink may be required due to

the increased power dissipation at higher currents.

When laying out a PC board for the shunts, a couple of

points should be kept in mind. The Kelvin connections

to the shunt should be brought together under the body

of the shunt and then run very close to each other to the

input of the isolated modulator; this minimizes the loop

area of the connection and reduces the possibility of stray

magnetic elds from interfering with the measured signal.

If the shunt is not located on the same PC board as the

isolated modulator circuit, a tightly twisted pair of wires

can accomplish the same thing.

Also, multiple layers of the PC board can be used to in-

crease current carrying capacity. Numerous plated-through

vias should surround each non-Kelvin terminal of the shunt

to help distribute the current between the layers of the PC

board. The PC board should use 2 or 4 oz. copper for the

layers, resulting in a current carrying capacity in excess of

20 A. Making the current carrying traces on the PC board

fairly large can also improve the shunt’s power dissipa-

tion capability by acting as a heat sink. Liberal use of vias

where the load current enters and exits the PC board is

also recommended.

Shunt Connections

The recommended method for connecting the isolated

modulator to the shunt resistor is shown in Figure 17. VIN+

(pin 2 of the HPCL-7860/HCPL-786J) is connected to the

positive terminal of the shunt resistor, while VIN- (pin 3) is

shorted to GND1 with the power-supply return path func-

tioning as the sense line to the negative terminal of the

current shunt. This allows a single pair of wires or PC board

traces to connect the isolated modulator circuit to the

shunt resistor. By referencing the input circuit to the nega-

tive side of the sense resistor, any load current induced

noise transients on the shunt are seen as a common-mode

signal and will not interfere with the current-sense signal.

This is important because the large load currents owing

through the motor drive, along with the parasitic induc-

tances inherent in the wiring of the circuit, can generate

both noise spikes and osets that are relatively large com-

pared to the small voltages that are being measured across

the current shunt.

If the same power supply is used both for the gate drive cir-

cuit and for the current sensing circuit, it is very important

that the connection from GND1 of the isolated modulator

to the sense resistor be the only return path for supply cur-

rent to the gate drive power supply in order to eliminate

potential ground loop problems. The only direct connec-

tion between the isolated modulator circuit and the gate

drive circuit should be the positive power supply line.

In some applications, however, supply currents owing

through the power-supply return path may cause oset

or noise problems. In this case, better performance may

be obtained by connecting VIN+ and VIN- directly across

the shunt resistor with two conductors, and connecting

GND1 to the shunt resistor with a third conductor for the

power-supply return path, as shown in Figure 19. When

connected this way, both input pins should be bypassed.

To minimize electromagnetic interference of the sense sig-

nal, all of the conductors (whether two or three are used)

connecting the isolated modulator to the sense resistor

should be either twisted pair wire or closely spaced traces

on a PC board.

The 39 : resistor in series with the input lead (R2) forms

a lowpass anti-aliasing lter with the 0.01 PF input bypass

capacitor (C2) with a 400 kHz bandwidth. The resistor per-

forms another important function as well; it dampens any

ringing which might be present in the circuit formed by

the shunt, the input bypass capacitor, and the inductance

of wires or traces connecting the two. Undamped ringing

of the input circuit near the input sampling frequency can

alias into the baseband producing what might appear to

be noise at the output of the device.

Figure 19. Schematic for Three Conductor Shunt Connection.

MOTOR

HV-

HV+

SENSE

FLOATING

POSITIVE

SUPPLY

GATE DRIVE

CIRCUIT

DD1

IN+

IN-

GND1

DD2

MCLK

MDAT

GND2

HCPL-7860/

HCPL-786J

0.1 μF

C2a

0.01 μF

R2a 39 Ω

5.1 V

C2b

0.01 μF

R2b 39 Ω

Voltage Sensing

The HCPL-7860/HCPL-786J Isolated Modulator can also

be used to isolate signals with amplitudes larger than its

recommended input range with the use of a resistive volt-

age divider at its input. The only restrictions are that the

impedance of the divider be relatively small (less than 1

k:) so that the input resistance (280 k:) and input bias

current (1 PA) do not aect the accuracy of the measure-

ment. An input bypass capacitor is still required, although

the 39 : series damping resistor is not (the resistance of

the voltage divider provides the same function). The low-

pass lter formed by the divider resistance and the input

bypass capacitor may limit the achievable bandwidth. To

obtain higher bandwidth, the input bypass capacitor (C2)

can be reduced, but it should not be reduced much below

1000 pF to maintain adequate input bypassing of the iso-

lated modulator.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

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AV02-0409EN - March 28, 2011