1
FEATURES
Two drivers and two receivers with individual enables
>400.0 Mbps (200 MHz) switching rates
+340mV differential signaling
3.3 V powe r supply
TTL compatible inputs
10mA LVDS output drivers
TTL compatible outputs
Cold spare all pins
Ultra low power CMOS technology
Operational environment; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 18-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-06202
- QML Q and V compliant part
INTRODUCTION
The UT54L VDM055L V Dual Driver/Dual Receiver is designed
for applications requiring ultra low power dissipation and high
data rates. The device is designed to support data rates in excess
of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential
Signaling (LVDS) technology.
The UT54LVDM055LV Driver accepts low voltage TTL input
levels and translates them to low voltage (350mV) differential
output signals. In addition, the driver supports a three-state
function that may be used to disable the output stage, disabling
the load current, and thus dropping the device to a low idle power
state.
The UT54L VDM055L V Receiver accepts low voltage (350mV)
differential input signals and translates them to 3V CMOS
output levels. The receiver supports a three-state function that
may be used to multiplex outputs. The receiver also supports
OPEN, shorted and terminated (35 Ω) input fail-safe. Receiver
output will be HIGH for all fail-safe conditions.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
Standard Products
UT54LVDM055LV Dual Driver and Receiver
Data Sheet
December 2008
www.aeroflex.com/lvds
Figure 1. UT54LVDM055LV Dual Driver and Receiver Block Diagram
+
R1
-
RIN1+
RIN1-
RIN2+
RIN2-
DEN2
ROUT1
ROUT2
DIN1
DIN2
+
R2
-
D2
D1
DEN1
DOUT2-
DOUT2+
DOUT1+
DOUT1-
REN1
REN2
2
TRUTH TABLE
PIN DESCRIPTION
Enables Input Output
DEN DIN DOUT+ DOUT-
L X Z Z
H L L H
H H L
Enables Input Output
REN RIN+ - RIN-R
OUT
LXZ
HV
ID > 0.1V H
VID < -0.1V L
Full Fail-safe
OPEN/SHORT or
Terminated
H
Figure 2. UT54LVDM055LV Pinout
UT54LVDM055LV
Driver/Receiver
18
17
16
15
14
13
12
REN1
ROUT1
ROUT2
GND
VDD
DEN2
DIN2
1
RIN1-
2
RIN1+ 3
RIN2+
4
RIN2- 5
REN2
6
DOUT2-
7
DOUT2+ 8
9
DOUT1+
DOUT1-
11 DIN1
10 DEN1
Pin No. Name Description
11, 12 DIN Driver input pin, TTL/CMOS
compatible
7, 8 DOUT+ Non-inverting driver output pin,
LVDS levels
6, 9 DOUT-Inverting driver output pin,
LVDS levels
10, 13 DEN Driver active high enable pin
2, 5 RIN+ Non-inverting receiver input pin
1, 4 RIN- Inverting receiver input pin
16, 17 ROUT Receiver output pin
5, 18 REN Receiver active high enable pin
14 VDD Power supply pin, +3.3 + 0.3V
15 VSS Ground pin
3
APPLICATIONS INFORMATION
The UT54LVDM055LV prov ides two drivers and two receiv-
ers in the same package. Each driver and each receiver has a
dedicated output enable pin. This allows maximum flexibility
for the device.
The intended application of these devices and signaling tech-
nique is for both point-to-point (singl e termination) and multi-
point (double termination) data transmissions over controlled
impedance media. The transmission media may be printed-cir-
cuit board traces, backplanes, or cables. (Note: The ultimate
rate and distance of data transfer is dependent upon the attenu-
ation characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.)
The UT54LVMS055LV differential line driver is a balanced
current source design. A current mode driver, has a high out-
put impedance and supplies a constant current for a range of
loads (a voltage mode driver on the other hand supplies a con-
stant voltage for a range of loads). Current is switched through
the load in one direction to produce a logic state and in the
other direction to produce the other logic state. The current
mode requires that a resistive termination be employed to ter-
minate the signal and to complete the loop as shown in Figure
3. AC or unterminated configurations are not allowed. The
10mA loop current will develop a differential voltage of
350mV across the 35Ω termination resistor which the receiver
detects with a 250mV minimum differential noise margin
neglecting resistive line losses (driven signal minus receiver
threshold (350mV - 100mV = 250mV)). The signal is centered
around +1.2V (Driver Offset, VOS) with respect to ground as
shown in Figure 4. Note: The steady-state volt age (VSS)
peak-to-peak swing is twice the differential voltage (VOD)
and is typically 700mV.
The UT54LVDM055LV receiver’s are capable of
detecting signals as low as 100mV, over a +/- 1V common-
mode range centered around +1.2V. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
The receiver is connected to the driver through a balanced
media which may be a standard twisted pair cable, a parallel
pair cable, or simply PCB traces. The termination resistor con-
verts the current sourced by the driver into voltages that are
detected by the receiver. Other configurations are possible
such as a multi-receiver configuration, but the ef fects of a mid-
stream connector(s), cable stub(s), and other impedance dis-
continuities, as well as ground shifting, noise margin limits,
and total termination loadi ng must be taken into account.
Receiver Fail-Safe
The UT54LVDM055LV receiver is a high gain, high speed
device that amplifies a small dif ferential signal (20mV) to TTL
logic levels. Due to the high gain and tight threshold of the
receiver , care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection (a
stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
Open Input Pins. The UT54LVDM055LV is a dual receiver
device, and if an application requires only 1 receiver, the unused
channel inputs should be left OPEN. Do not tie unused receiver
inputs to ground or any other voltages. The input is biased by
internal high value pull up and pull down resistors to set the
output to a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a three-state or power-off
condition, the receiver output will again be in a HIGH state,
even with the end of cable 35Ω termination resistor across the
input pins. The unplugged cable can become a floating antenna
which can pick up noise. If the cable picks up more than 10mV
of differential noise, the receiver may see the noise as a valid
signal and switch. To insure that any noise is seen as common-
mode and not differential, a balanced interconnect should be
used. Twisted pair cable offers better balance than flat ribbon
cable.
Shorted Inputs . If a fault condition occurs that shorts the
receiver inputs together, thus resulting in a 0V differential input
voltage, the receiver output remains in a HIGH state. Shorted
input fail-safe is not supported across the common-mode range
of the device (VSS to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage app l ied.
ENABLE
DATA
INPUT
LVDS Driver
LVDS Receiver
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 35Ω
4
OPERATIONAL ENVIRONMENT
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cau se permanent damage to the device. This is a stress ra ting only , and functional operation of the d evice
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Ionizing Dose (T ID) 1.0E6 rad(Si)
Single Event Latchup (SEL) >100 MeV-cm2/mg
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3 to 4.0V
VI/O Voltage on any pin during operation -0.3 to (VDD + 0.3V)
Voltage on any pin during cold spare -.3 to 4.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.25 W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125°C
VIN DC input voltage, receiver inputs
DC input voltage, logic inputs 2.4V
0 to VDD
5
DC ELECTRICAL CHARACTERISTICS DRIVER *1, 2,4
(VDD = 3.3V + 0.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates directio n on ly.
3. Guaranteed by characterization
4. Receivers are included for parameters ICCL and ICCZ.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL Low-level output voltage RL = 35Ω0.855 V
VOH High-level output voltage RL = 35Ω1.750 V
IIN Input leakage current VIN = VDD or GND, VDD = 3.6V -5 +5 μA
ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -10 +10 μΑ
VOD1Differential Output Voltage RL = 35Ω(figure 5) 250 400 mV
ΔVOD1Change in Magnitude of VOD for
Complementary Output States RL = 35Ω(figure 5) 35 mV
VOS Offset Voltage RL = 35Ω, VOS = 1.055 1.550 V
ΔVOS Change in Magnitude of VOS for
Complementary Output States RL = 35Ω(figure 5) 35 mV
VCL Input clamp voltage ICL = +18mA -1.5 V
IOS2, 3 Output Short Circuit Current VIN = VDD, VOUT+ = 0V or
VIN = GND, VOUT- = 0V, DEN = VDD
40 mA
IOZ Output Three-State Current DEN = 0.8V
VOUT = 0V or VDD, VDD = 3.6V
-5 +5 μΑ
ICCL4Loaded supply current, drivers and
receivers enabled RL = 35Ω all channels
REN = DEN = VDD
VIN = VDD or VSS(all inputs)
40.0 mA
ICCZ4Loaded supply current, drivers and
receivers disabled DIN = VDD or VSS
REN = DEN = VSS 15.0 mA
VOH VOL+
2
---------------------------------
⎝⎠
⎛⎞
6
AC SWITCHING CHARACTERISTICS DRIVER*1, 2, 3
(VDD = +3.3V + 0.3V, TC = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr < 1ns, and tf < 1ns.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter.
SYMBOL PARAMETER MIN MAX UNIT
tPHLD6Differential Propagation Delay High to Low
(figures 5 and 6) 0.5 1.8 ns
tPLHD6Differential Propagation Delay Low to High
(figures 5 and 6) 0.5 1.8 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 5 and 6) 0 0.4 ns
tSK11Channel-to-Channel Skew (figures 5 and 6) 0 0.5 ns
tSK25Chip-to-Chip Skew (figure 5 and 6) 1.3 ns
tTLH4Rise Time (figures 5 and 6) 1.5 ns
tTHL4Fall Time (figures 5 and 6) 1.5 ns
tPHZ Disable Time High to Z (figures 7 and 8) 5 ns
tPLZ Disable Time Low to Z (figures 7 and 8) 5 ns
tPZH Enable Time Z to High (figures 7 and 8) 7.0 ns
tPZL Enable Time Z to Low (figures 7 and 8) 7.0 ns
7
DC ELECTRICAL CHARACTERISTICS RECEIVER*1,2,4
(VDD = 3.3V + 0.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only , minus sign indicates direction only . Only one output should be shorted at a time, do not exceed 1 second.
3. Guaranteed by characterization.
4. Refer to driver DC characteristics for ICCL and ICCZ.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL Low-level output voltage IOL = 2mA, VDD = 3.0V 0.25 V
VOH High-level output voltage IOH = -0.4mA, VDD = 3.0V 2.7 V
IIN Logic input leakage current Enables = REN = 0 and 3.6V,
VDD = 3.6
-5 +5 μA
IILV DS Receiver input Current VIN = 2.4V, VDD = 3.6 -15 +15 μΑ
ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -10 +10 μΑ
VTH3Differential Input High Threshold VCM = +1.2V +100 mV
VTL3Differential Input Low Threshold VCM = +1.2V -100 mV
IOZ3Output Three-State Current Disabled, VOUT = 0 V or VDD
REN = 0.8V
-5 +5 μΑ
VCL Input clamp voltage ICL = -18mA -1.5 V
IOS2, 3 Output Short Circuit Current Enabled, VOUT = 0 V2
REN = VDD
-75 mA
8
AC SWITCHING CHARACTERISTICS RECEIVER*1, 2, 3
(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured.
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50Ω, tr and tf (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter.
7. During tPZL the output ma y transition High before going Low.
SYMBOL PARAMETER MIN MAX UNIT
tPHLD6Differential Propagation Delay High to Low
(figures 9 and 10) 1.0 2.0 ns
tPLHD6Differential Propagation Delay Low to High
(figures 9 and 10) 1.0 2.0 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 9 and 10) 0 0.35 ns
tSK11Channel-to-Channel Skew (figures 9 and 10) 0 0.5 ns
tSK25Chip-to-Chip Skew (figures 9 and 10) 1.0 ns
tTLH4Rise Time (figures 9 and 10) 1.2 ns
tTHL4Fall Time (figures 9 and 10) 1.2 ns
tPHZ Disable Time High to Z (figures 11 and 12) 4.0 ns
tPLZ Disable Time Low to Z (figures 11 and 12) 4.0 ns
tPZH Enable Time Z to High (figures 11 and 12) 3.0 ns
tPZL7Enable Time Z to Low (figures 11 and 12) 3.0 ns
9
Figure 4. Driver VOD and VOS Test Circuit or Equivalent Circuit
D
DIN
DOUT-
DOUT+
40pF
Driver Enabled
Generator
50Ω
RL = 35ΩVOD
40pF
D
DIN
DOUT-
DOUT+
Driver Enabled
Generator
50Ω
RL = 35Ω
Figure 5. Driver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
40pF
40pF
10
DIN
DOUT-
DOUT+
VDIFF
tPHLD
VDD
0V
VOH
VOL
0V
VDIFF = DOUT+ - DOUT-
0V (Differential)
VDD/2
tTHL
20%
80%
0V
20%
80%
tTLH
tPLHD
VDD/2
Figure 6. Driver Propagation Delay and Transition Ti me Waveforms or Equivalent Circuit
D
VDD
VSS
DIN
EN
Generator
50ΩEN
17.5Ω
DOUT+
DOUT-
Figure 7. Driver Three-State Delay Test Circuit or Equivalent Circuit or Equivalent Circuit
40pF
40pF
17.5Ω
11
12
R
RIN+ ROUT
Receiver Enabled
Generator
50Ω
Figure 9. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
RIN-
50Ω
40pF
RIN-
RIN+
ROUT
tPHLD
VOL
VOH
+1.1V
50%
+1.2V
tTHL
20%
80%
50%
20%
80%
tTLH
0V Differential
Figure 10. Receiver Propagation Delay and Transition Time Waveforms or Equivalent Circuits
tPLHD
VID = 200mV
+1.3V
13
14
Notes:
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Lead position and coplanarity are not measured.
5. ID mark symbol is vendor option and may be different than shown.
6. With solder, increase maximum by 0.003.
7. Package weight 0.8 grams.
Figure 13. 18-pin Ceramic Flatpack
15
ORDERING INFORMATION
UT54LVDM055LV DUAL DRIVER/RECEIVER:
UT 54LV DM055LV - * * * * *
Device Type:
UT54LVDM055LV LVDS Receiver
Access T i me:
Not applicable
Package Type:
(U) = 18-lead Flatpack (dual-in-line)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. T ested at 25°C only . Lead finish is GOLD ONLY.
Radiation neither tested nor guaranteed.
4. HiRel T emperature Rang e flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room
temp, and 125°C. Radiation neither tested nor guaranteed.
16
UT54LVDM055LV DUAL DRIVER/RECEIVER: SMD
5962 - ** *
Federal Stock Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
Drawing Number: 5962-06202
Device Type
01 - Dual driver receiver 100KRad(Si) 300KRad(Si)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(X) = 18 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
06202
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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to make changes to any products and services herein at any
time without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel