Updated September 23, 2014. ©2014 ADLINK Technology, Inc. All Rights Reserved. All specications are subject to change without further notice.
Features
■ x1 lane PCI Express® Interface
■ Maximum 50 MHz clock rate from internal timer or
100 MHz from external clock
■ 200 MB/s maximum throughput
■ Software selectable voltage level of 1.8 V, 2.5 V, and 3.3 V
■ 16-steps phase shift in external clock mode
■ Per group (8-Bit) input/output direction selectable
■ Supports I2C and SPI programmable serial interfaces for
external device communication
■ Scatter-gather DMA support
■ Flexible handshaking and external digital trigger modes
■ 8-channel auxiliary programmable I/O
■Supported Operating System
•Windows 7/8 x64/x86, Linux
■Driver and SDK
•LabVIEW, MATLAB, C/C++, Visual Basic,
Visual Studio.NET
50 MHz 32-CH High-Speed Digital I/O Card
PCIe-7350
Ordering Information
■ PCIe-7350
50 MHz 32-CH High-Speed Digital I/O PCI
Express
®
Card
Terminal Boards & Cables
■DIN-68H-01
Terminal Board with One 68-pin SCSI-VHDCI
Connector and 0 or 50 Ω Jumper Selectable
Impedance (Cables are not included.
■ACL-10279
68-pin SCSI-VHDCI Cable with 50 Ω Impedance
■SMB-SMB-1M
SMB to SMB Cable, 1M
* For more information about mating cables, please refer to
P3-48/49.
Logic Levels 1.8 V 2.5 V 3.3 V
Digital Input Min. input high voltage 1.2 V 1.6 V 2 V
Max. input low voltage 0.63 V 0.7 V 0.8 V
Digital Output
Min. output high voltage 1.6 V 2.3 V 3.1 V
Max. output low voltage 0.2 V 0.2 V 0.2 V
Max. output driving current 8 mA 16 mA 32 mA
High-Speed DIO
Specifications
Digital I/O
■
Number of channels:
32, per group (8-channel) input/output direction
selectable
■
Logic levels: 1.8 V, 2.5 V, 3.3 V (software selectable)
■
Power-up status: All digital inputs
■
Impedance:
•Input: 10 kΩ
•Output: 50 Ω
■
Input protection: -1 to 6 V
■
Data transfer: Programmable I/O, bus-mastering
DMA with scatter-gather
■
Maximum data transfer rate: 200 MB/s
■
Digital logic levels:
Clocking mode
■
Internal clock: Max. 50 MHz (100 MHz / N;
2<N<65535)
■
External clock: Max. 100 MHz (support 8/16-Bit
data width only, data throughput must be less than
200 MB/s)
■
Handshaking
■
Burst handshaking
Trigger sources
■
Software trigger
■
External digital trigger: AFI[0…7]
Trigger modes
■
Post trigger, Retrigger, Pattern match, Handshaking
Change of State Interrupt
■
Interrupt sources: Any of 32 channels or a pre-define
channel Change-of-State
Application Function I/O
■
Number of channels: 8
■
Supporting modes: static I/O, I
2
C or SPI master
node, external clock input/output, external digital
trigger input, handshaking
3-34
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