Publication# 14128 Rev. IAmendment/0
Issue Date: May 1995
Advanced
Micro
Devices
MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
FINAL COM’L: -7/10/12/15/20, Q-12/15/20 IND: -12/14/18/24
DISTINCTIVE CHARACTERISTICS
44 Pins
64 Macrocells
7.5 ns tPD Commercial
12 ns tPD Industrial
133 MHz fCNT
38 Inputs; 210A Inputs have built-in pull-up
resistors
Peripheral Component Interconnect (PCI)
compliant
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111,
MACH211, and MACH215
GENERAL DESCRIPTION
The MACH210 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately six times the logic macrocell capability of
the popular PAL22V10 without loss of speed.
The MACH210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH210 has two kinds of macrocell: output and
buried. The MACH210 output macrocell provides regis-
tered, latched, or combinatorial outputs with program-
mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH210 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in
synchronizing signals and reducing setup time require-
ments.
AMD
MACH210-7/10/12/15/20, Q-12/15/202
BLOCK DIAGRAM
Switch Matrix
I/O Cells
Macrocells
I/O Cells
Macrocells
8
8
8
I/O Cells
Macrocells
I/O0–I/O7
Macrocells
I/O Cells
Macrocells
8
8
8
8
8
888
8
I0–I1,
I3–I4
I/O8–I/O15
2
I/O16–I/O23 CLK0/I2,
CLK1/I5
I/O24–I/O31
14128I-1
44 x 68
AND Logic Array
and
Logic Allocator
22 22
22 22
44 x 68
AND Logic Array
and
Logic Allocator
4
2
8
44 x 68
AND Logic Array
and
Logic Allocator
44 x 68
AND Logic Array
and
Logic Allocator
8
2
OE
Macrocells
8
8
Macrocells Macrocells
OE
OE OE
AMD
3MACH210-7/10/12/15/20, Q-12/15/20
CONNECTION DIAGRAM
Top View
PLCC
14128I-2
I/O5
I/O6
I/O7
I0
I1
CLK0/I2
I/O8
I/O9
GND
I/O10
I/O11
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I3
I4
I/O24
CLK1/I5
GND
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
VCC
GND
I/O16
I/O15
I/O17
I/O18
I/O19
I/O20
7
8
9
10
11
12
13
15
16
14
17
561324 4443424140
29
30
31
32
33
34
35
36
37
38
39
18 282726252423222119 20
Note:
Pin-compatible with MACH110, MACH111, MACH211, and MACH215.
AMD
MACH210-7/10/12/15/20, Q-12/15/204
CONNECTION DIAGRAM
Top View
TQFP
1
2
3
4
5
6
7
8
9
10
11
I/O27
I/O26
I/O25
I/O24
CLK1/I5
GND
I4
I3
I/O23
I/O22
I/O21
33
32
31
30
29
28
27
26
25
24
23
I/O5
I/O6
I/O7
I0
I1
GND
CLK0/I2
I/O8
I/O9
I/O10
I/O11
44
43
42
41
40
39
38
37
36
35
34
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
12
13
14
15
16
17
18
19
20
21
22
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
14128I-3
Note:
Pin-compatible with MACH111 and MACH211.
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
AMD
MACH210-7/10/12/15/20, Q-12/15/20 (Com’l) 5
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
OPERATING CONDITIONS
C = Commercial (0°C to +70 °C)
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
SPEED
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
MACH210A-7
MACH210A-10
MACH210A-12
MACH210-12
MACH210-15
MACH210-20
MACH210AQ-12
MACH210AQ-15
MACH210AQ-20
MACH -7 J C
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con-
sult the local AMD sales office to confirm availability of
specific valid combinations or to check on newly re-
leased combinations.
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
210A
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins
210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors
210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors,
Quarter Power
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
JC
JC,
VC
AMD
6 MACH210-12/14/18/24 (Ind)
ORDERING INFORMATION
Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid
Combination) is formed by a combination of:
OPERATING CONDITIONS
I = Industrial (–40°C to +85 °C)
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
SPEED
-12 = 12 ns tPD
-14 = 14.5 ns tPD
-18 = 18 ns tPD
-24 = 24 ns tPD
MACH210A-12
MACH210A-14
MACH210-14
MACH210-18
MACH210-24
MACH -12 J I
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con-
sult the local AMD sales office to confirm availability of
specific valid combinations or to check on newly re-
leased combinations.
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
210A
DEVICE NUMBER
210 = 64 Macrocells, 44 Pins
210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
JI
AMD
7MACH210-7/10/12/15/20, Q-12/15/20
FUNCTIONAL DESCRIPTION
The MACH210 consists of four PAL blocks connected
by a switch matrix. There are 32 I/O pins and 4
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are two clock pins that
can also be used as dedicated inputs.
The MACH210A inputs and I/O pins have built-in pull-up
resistors. While it is always a good design practice to tie
unused pins high, the 210A pull-up resistors provide
design security and stability in the event that unused
pins are left disconnected.
The PAL Blocks
Each PAL block in the MACH210 (Figure 1) contains a
64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 22 inputs. This
makes the PAL block look effectively like an independ-
ent “PAL22V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
The Switch Matrix
The MACH210 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The Product-term Array
The MACH210 product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one pro-
vides asynchronous reset, and one provides asynchro-
nous preset.
The Logic Allocator
The logic allocator in the MACH210 takes the 64 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
Table 1. Logic Allocation
Available
Output Buried Clusters
M0C0, C1, C2
M1C0, C1, C2, C3
M2C1, C2, C3, C4
M3C2, C3, C4, C5
M4C3, C4, C5, C6
M5C4, C5, C6, C7
M6C5, C6, C7, C8
M7C6, C7, C8, C9
M8C7, C8, C9, C10
M9C8, C9, C10, C11
M10 C9, C10, C11, C12
M11 C10, C11, C12, C13
M12 C11, C12, C13, C14
M13 C12, C13, C14, C15
M14 C13, C14, C15
M15 C14, C15
Macrocell
The Macrocell
The MACH210 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip-
flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input is
LOW. The flip-flops can also be asynchronously initial-
ized with the common asynchronous reset and preset
product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
AMD
MACH210-7/10/12/15/20, Q-12/15/208
The I/O Cell
The I/O cell in the MACH210 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
PCI Compliance
The MACH210A-7/10 is fully compliant with the
PCI
Local Bus Specification
published by the PCI Special
Interest Group. The MACH210A-7/10’s predictable
timing ensures compliance with the PCI AC specifica-
tions independent of the design. On the other hand, in
CPLD and FPGA architectures without predictable
timing, PCI compliance is dependent upon routing and
product term distribution.
AMD
9MACH210-7/10/12/15/20, Q-12/15/20
14128I-4
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
8
I/O
Cell I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
CLK0
CLK1
2
2
2
2
2
2
2
2
2
16
0I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Buried
Macro 
cell
Output
Macro
cell
2
2
2
2
2
2
2
Buried
Macro
cell
Output
Macro
cell
Output
Macro
cell
Buried
Macro 
cell
Output
Macro
cell
Buried
Macro 
cell
Output
Macro
cell
Buried
Macro 
cell
Output
Macro
cell
Buried
Macro 
cell
Output
Macro
cell
Buried
Macro 
cell
Output
Macro
cell
Buried
Macro 
cell
I/O
Cell
Logic Allocator
63
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
M3
M6
M5
M4
M2
M1
M0
M9
M8
M7
M10
M11
M12
M13
M14
M15
Figure 1. MACH210 PAL Block
AMD
10 MACH210A-7 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current
(TA = 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 16 mA, V CC = Min 0.5 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, V CC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, V CC = Max 10 µA
Current HIGH VIN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, V CC = Max –100 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) 130 mA
VCC = 5.0 V, f = 25 MHz, TA = 25°C
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and
capable of being loaded, enabled, and reset.
AMD
11MACH210A-7 (Com’l)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Parameter
Symbol Parameter Description Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output 7.5 ns
tSSetup Time from Input, I/O or Feedback to Clock D-Type 5.5 ns
T-Type 6.5 ns
tHRegister Data Hold Time 0 ns
tCO Clock to Output 5ns
t
WL Clock Width LOW 3 ns
tWH HIGH 3 ns
D-Type 100 MHz
T-Type 91 MHz
fMAX D-Type 133 MHz
T-Type 125 MHz
166.7 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 ns
tHL Latch Data Hold Time 0 ns
tGO Gate to Output 6ns
t
GWL Gate Width LOW 3 ns
tPDL Input, I/O, or Feedback to Output Through 9.5 ns
Transparent Input or Output Latch
tSIR Input Register Setup Time 2 ns
tHIR Input Register Hold Time 2 ns
tICO Input Register Clock to Combinatorial Output 11 ns
tICS Input Register Clock to Output Register Setup D-Type 9 ns
T-Type 10 ns
tWICL Input Register Clock Width LOW 3 ns
tWICH HIGH 3 ns
fMAXIR Maximum Input Register Frequency 166.7 MHz
tSIL Input Latch Setup Time 2 ns
tHIL Input Latch Hold Time 2 ns
tIGO Input Latch Gate to Combinatorial Output 12 ns
tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 ns
tSLL Setup Time from Input, I/O, or Feedback Through 7.5 ns
Transparent Input Latch to Output Latch Gate
Maximum
Frequency
External Feedback
Internal Feedback (fCNT)
No Feedback
-7
AMD
12 MACH210A-7 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)
Parameter
Symbol Parameter Description Min Max Unit
tIGS Input Latch Gate to Output Latch Setup 10 ns
tWIGL Input Latch Gate Width LOW 3 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent 11.5 ns
Input and Output Latches
tAR Asynchronous Reset to Registered or Latched Output 12 ns
tARW Asynchronous Reset Width 8 ns
tARR Asynchronous Reset Recovery Time 8 ns
tAP Asynchronous Preset to Registered or Latched Output 12 ns
tAPW Asynchronous Preset Width 8 ns
tAPR Asynchronous Preset Recovery Time 8 ns
tEA Input, I/O, or Feedback to Output Enable 7.5 ns
tER Input, I/O, or Feedback to Output Disable 7.5 ns
-7
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
AMD
13
MACH210A-10/12 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = 0°C to +70°C) 200 mA. . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 16 mA, V CC = Min 0.5 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, V CC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, V CC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, V CC = Max 10 µA
Current HIGH V IN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –100 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Supply Current (Typical) VCC = 5V, TA = 25°C, f = 25 MHz 135 mA
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
AMD
MACH210A-10/12 (Com’l)
14
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output
(Note 3) 10 12 ns
D-Type 6.5 7 ns
T-Type 7.5 8 ns
tHRegister Data Hold Time 0 0 ns
tCO Clock to Output (Note 3) 6 8 ns
tWL Clock LOW 5 6 ns
tWH Width HIGH 5 6 ns
D-Type 80 66.7 MHz
T-Type 74 62.5 MHz
fMAX D-Type 100 83.3 MHz
T-Type 91 76.9 MHz
100 83.3 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 6.5 7 ns
tHL Latch Data Hold Time 0 0 ns
tGO Gate to Output (Note 3) 7 10 ns
tGWL Gate Width LOW 5 6 ns
tPDL Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch 12 14 ns
tSIR Input Register Setup Time 2 2 ns
tHIR Input Register Hold Time 2 2 ns
tICO Input Register Clock to Combinatorial Output 13 15 ns
tICS Input Register Clock to Output Register Setup D-Type 10 12 ns
T-Type 11 13 ns
tWICL Input Register LOW 5 6 ns
tWICH Clock Width HIGH 5 6 ns
fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 100 83.3 MHz
tSIL Input Latch Setup Time 2 2 ns
tHIL Input Latch Hold Time 2 2 ns
tIGO Input Latch Gate to Combinatorial Output 14 17 ns
tIGOL Input Latch Gate to Output Through Transparent
Output Latch 16 19 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 8.5 9 ns
tIGS Input Latch Gate to Output Latch Setup 11 13 ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback 1/(t S + t CO)
Internal Feedback (fCNT)
No Feedback 1/(tS + tH)
-10 -12
tS
AMD
15
MACH210A-10/12 (Com’l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tWIGL Input Latch Gate Width LOW 5 6 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches 14 16 ns
tAR Asynchronous Reset to Registered or Latched Output 25 16 ns
tARW Asynchronous Reset Width (Note 1) 10 12 ns
tARR Asynchronous Reset Recovery Time (Note 1) 10 8 ns
tAP Asynchronous Preset to Registered or Latched Output 15 16 ns
tAPW Asynchronous Preset Width (Note 1) 10 12 ns
tAPR Asynchronous Preset Recovery Time (Note 1) 10 8 ns
tEA Input, I/O, or Feedback to Output Enable (Note 3) 10 12 ns
tER Input, I/O, or Feedback to Output Disable (Note 3) 10 12 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 16 outputs switching.
-10 -12
AMD
MACH210A-12/14 (Ind)
16
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = 0°C to +70°C) 200 mA. . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Temperature (TA) Operating
in Free Air –40°C to +85°C. . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +4.5 V to +5.5 V. . . . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 16 mA, V CC = Min 0.5 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, V CC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, V CC = Max (Note 2) –100 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, V CC = Max 10 µA
Current HIGH V IN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –100 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Supply Current (Typical) VCC = 5V, TA = 25°C, f = 25 MHz 135 mA
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.
AMD
17
MACH210A-12/14 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance V IN = 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF
COUT Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tPD Input, I/O, or Feedback to Combinatorial Output
(Note 3) 12 14.5 ns
D-Type 8 8.5 ns
T-Type 9 10 ns
tHRegister Data Hold Time 0 0 ns
tCO Clock to Output (Note 3) 7.5 10 ns
tWL Clock LOW 6 7.5 ns
tWH Width HIGH 6 7.5 ns
D-Type 64 53 MHz
T-Type 59 50 MHz
fMAX D-Type 80 61.5 MHz
T-Type 72.5 57 MHz
80 66.5 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 8 8.5 ns
tHL Latch Data Hold Time 0 0 ns
tGO Gate to Output (Note 3) 8.5 12 ns
tGWL Gate Width LOW 6 7.5 ns
tPDL Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch 14.5 17 ns
tSIR Input Register Setup Time 2.5 2.5 ns
tHIR Input Register Hold Time 3 3 ns
tICO Input Register Clock to Combinatorial Output 16 18 ns
tICS Input Register Clock to Output Register Setup D-Type 12 14.5 ns
T-Type 13 16 ns
tWICL Input Register LOW 6 7.5 ns
tWICH Clock Width HIGH 6 7.5 ns
fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 80 66.5 MHz
tSIL Input Latch Setup Time 2.5 2.5 ns
tHIL Input Latch Hold Time 3 3 ns
tIGO Input Latch Gate to Combinatorial Output 17 20.5 ns
tIGOL Input Latch Gate to Output Through Transparent
Output Latch 19.5 23 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 10.5 11 ns
tIGS Input Latch Gate to Output Latch Setup 13.5 16 ns
Maximum
Frequency
(Note 1)
Setup Time from Input, I/O,
or Feedback to Clock
External Feedback 1/(t S + t CO)
Internal Feedback (fCNT)
No Feedback 1/(tS + tH)
-12 -14
tS
AMD
MACH210A-12/14 (Ind)
18
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Parameter
Symbol Parameter Description Min Max Min Max Unit
tWIGL Input Latch Gate Width LOW 6 7.5 ns
tPDLL Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches 17 19.5 ns
tAR Asynchronous Reset to Registered or Latched Output 19.5 19.5 ns
tARW Asynchronous Reset Width (Note 1) 12 14.5 ns
tARR Asynchronous Reset Recovery Time (Note 1) 12 10 ns
tAP Asynchronous Preset to Registered or Latched Output 18 19.5 ns
tAPW Asynchronous Preset Width (Note 1) 12 14.5 ns
tAPR Asynchronous Preset Recovery Time (Note 1) 12 10 ns
tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 14.5 ns
tER Input, I/O, or Feedback to Output Disable (Note 3) 12 14.5 ns
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
2. See Switching Test Circuit, for test conditions.
3. Parameters measured with 16 outputs switching.
-12 -14
AMD
19
MACH210-12/15/20 (Com’l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +150°C. . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Supply Voltage with
Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .
DC Input Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . .
DC Output or
I/O Pin Voltage –0.5 V to VCC + 0.5 V. . . . . . . . . . . .
Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .
Latchup Current (TA = 0°C to +70°C) 200 mA. . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) with
Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter
Symbol Parameter Description Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V
VIN = VIH or VIL
VOL Output LOW Voltage IOL = 16 mA, V CC = Min 0.5 V
VIN = VIH or VIL
VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V
Voltage for all Inputs (Note 1)
VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V
Voltage for all Inputs (Note 1)
IIH Input HIGH Leakage Current VIN = 5.25 V, V CC = Max (Note 2) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, V CC = Max (Note 2) –10 µA
IOZH Off-State Output Leakage VOUT = 5.25 V, V CC = Max 10 µA
Current HIGH V IN = VIH or VIL (Note 2)
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max –10 µA
Current LOW VIN = VIH or VIL (Note 2)
ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA
ICC Supply Current (Typical) VCC = 5V, TA = 25°C, f = 25 MHz 120 mA
(Note 4)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I
IL
and I
OZL
(or I
IH
and I
OZH
).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
OUT
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being
loaded, enabled, and reset.