O c t o b e r 2 00 6 S LIC -E / TS LIC -E S ub s c ri be r L in e I n t e rf a c e C i rc u it E nh an c ed F ea t ur e S et S LI C - E ( P E F 42 65 ), V er s io n 2 . 1 S LI C - E 2 (P E F 4 26 5- 2) , V e rs i on 2. 1 T S L I C - E ( P E F 4 36 5) , V er s i o n 2 . 1 P re li m in ar y D a ta S h e e t R e v is i o n 2 . 0 Communication Solutions Edition 2006-10-10 Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2006. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. SLIC-E / TSLIC-E PEF 4265 / PEF 4365 SLIC-E / TSLIC-E Subscriber Line Interface Circuit Enhanced Feature Set Revision History: 2006-10-10, Revision 2.0 Previous Version: Revision 1.0 Page Subjects (major changes since last revision) all Package P-/PG-VQFN-48-4 changed to PG-VQFN-48-15 all Package P-/PG-DSO-20-24 changed to PG-DSO-20-24 all Package P-/PG-DSO-36-10 changed to PG-DSO-36-15 Page 36 "Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package" on Page 36 modified. Trademarks ABM(R), ACE(R), AOP(R), Arcofi(R), ASM(R), ASP(R), BlueMoon(R), BlueNIX(R), C166(R), DuSLIC(R), ELIC(R), Epic(R), FALC(R), GEMINAX(R), Idec(R), INCA(R), IOM(R), Ipat(R)-2, IPVD(R), Isac(R), Itac(R), IWE(R), IWORX(R), M-GOLD(R), MUSAC(R), MuSLIC(R), OCTALFALC(R), OCTAT(R), POTSWIRE(R), QUADFALC(R), QUAT(R), SCOUT(R), SCT(R), SEROCCO(R), S-GOLD(R), SICAT(R), SICOFI(R), SIDEC(R), SIEGET(R), SLICOFI(R), SMARTI(R), SOCRATES(R), VDSLite(R), VINETIC(R), 10BaseS(R) are registered trademarks of Infineon Technologies AG. ConverGateTM, DIGITAPETM, DUALFALCTM, EasyPortTM, S-GOLDliteTM, S-GOLD2TM, S-GOLD3TM, VINAXTM, WildPassTM, 10BaseVTM, 10BaseVXTM are trademarks of Infineon Technologies AG. Microsoft(R) and Visio(R) are registered trademarks of Microsoft Corporation. Linux(R) is a registered trademark of Linus Torvalds. FrameMaker(R) is a registered trademark of Adobe Systems Incorporated. APOXI(R) is a registered trademark of Comneon GmbH & Co. OHG. PrimeCell(R), RealView(R), ARM(R) are registered trademarks of ARM Limited. OakDSPCore(R), TeakLite(R) DSP Core, OCEM(R) are registered trademarks of ParthusCeva Inc. IndoorGPSTM, GL-20000TM, GL-LN-22TM are trademarks of Global Locate. ARM926EJ-STM, ADSTM, Multi-ICETM are trademarks of ARM Limited. Preliminary Data Sheet 3 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 1.1 1.2 1.3 1.4 1.5 1.6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Version 2.1: Summary of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 2.1 2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Limitation / Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Typical Application Circuit for DuSLIC(R) and VINETIC(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 4.1 4.2 4.3 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foreign Line Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Currents and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Dependence of PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 6.1 6.2 6.2.1 6.3 6.3.1 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-DSO-20-24 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-VQFN-48-15 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package . . . . . . . . . . . . . . . . . . . . . . PG-DSO-36-15 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 22 23 23 25 27 29 35 35 36 36 37 38 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Preliminary Data Sheet 4 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Logic Symbol PEF 4265 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol PEF 4365 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration PG-DSO-20-24 Package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration PG-VQFN-48-15 Package (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Configuration PG-DSO-36-15 Package (dual channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Transversal and Longitudinal Line Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application Circuit DuSLIC(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application Circuit VINETIC(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR . . . . . . . . . . . . . . . . . . . . . 27 Typical Frequency Dependence of PSRR VBATL/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical Frequency Dependence of PSRR VBATH/VTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical Frequency Dependence of PSRR VHR/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical Frequency Dependence of PSRR VDD/VTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Output Resistance PDRH, PDRHL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current Outputs IT, IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Longitudinal to Transversal Rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Longitudinal to Transversal Rejection Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Transversal to Longitudinal Rejection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ring Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Package Outline for PG-DSO-20-24 (Plastic Green Dual Small Outline). . . . . . . . . . . . . . . . . . . . 35 Package Outline for PG-VQFN-48-15 (Plastic Green Very thin Profile Quad Flatpack No-lead) . . 36 Package Outline for PG-DSO-36-15 (Plastic Green Dual Small Outline). . . . . . . . . . . . . . . . . . . . 37 Footprint for PG-DSO-36-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Preliminary Data Sheet 5 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48-15 . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions PG-DSO-36-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-E Mode Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC-E Modes and Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Components DuSLIC(R) / VINETIC(R) for 2 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limits on Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel) . . . . . . . . . . . . . . . . . . . . Output Stage Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (VACP = VACN = 1.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Data Sheet 6 12 13 16 16 18 21 21 22 22 22 23 24 25 27 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description 1 General Description Infineon Technologies' new high voltage ringing Subscriber Line Interface Circuit SLIC-E (PEF 4265 V2.1) is the latest out of the well-known and broadly used SLIC-E family. It has been designed not only to cover all previous SLIC-E applications, but also for particular "ADSL friendliness" and thus enables the realization of highly cost optimized integrated voice data (IVD) systems. Special effort has been put on minimizing the influence of line voltage transients and distortions caused by mode transitions and the associated unavoidable impedance changes. As SLIC-E V2.1 is pin compatible with its previous versions, it can be operated with all codec devices of the DuSLIC(R) or VINETIC(R) chip sets. The highly flexible device offers 3.3 V compatibility and integrated balanced ringing up to 85 Vrms. Integrated supply switches allow the choice between two negative battery voltages for voice transmission, whereas in the ring mode an additional positive supply voltage is used. To minimize the average system power dissipation, a power-down mode can be utilized; the transmission part is switched off completely and off-hook supervision is provided by activating a simple line current sensor with negligible power consumption. SLIC-E V2.1 is available in a single (PEF 4265) channel version in either PG-DSO-20-24 or PG-VQFN-48-15 power packages, or in a dual channel version (PEF 4365), packaged in PG-DSO-36-15. 1.1 Version 2.1: Summary of Changes Compared with the previous version of SLIC-E, PEF 4265 V1.2, the new version V2.1 is characterized by the following changes: * * * * * * * Improved high-frequency noise and distortion performance Optimized mode transitions to minimize influence on ADSL data in IVD systems Compatible with both 3.3 and 5 V VDD supplies High impedance DC inputs Fully differential receive path - VCMS pin not required Fast current limitation for improved overvoltage behaviour Application circuit: - 100 nF / 50 V capacitor at CEXT - Per channel series diode in VBATL supply mandatory (no shared diodes) Preliminary Data Sheet 7 Revision 2.0, 2006-10-10 Subscriber Line Interface Circuit Enhanced Feature Set SLIC-E SLIC-E2 TSLIC-E PEF 4265 PEF 4265-2 PEF 4365 Version 2.1 1.2 Features * "ADSL-friendly" high voltage SLIC with integrated ringing * Compatible with both 3.3 and 5 V systems * Available in single and dual-channel versions * High-voltage line feed (long loop driving capability) * Sensing of transversal and longitudinal line currents * Two Battery voltages (-15 V ... -85 V) * Positive ring supply voltage up to +85 V * Total supply voltage up to 150 V * Integrated balanced ringing up to 85 Vrms * High longitudinal balance performance with SLIC-E2 (PEF 4265-2) * Power-saving active mode (ACTL) with reduced battery voltage * Power Down mode with negligible power consumption * Package options: P/PG-DSO-20-5 PG-DSO-20-24 PG-VQFN-48-15 - PG-DSO-20-24 - PG-VQFN-48-15 - PG-DSO-36-15 (dual channel) * PG-VQFN-48-15 Reliable Smart Power Technology (SPT170) P/PG-DSO-36-10, -12, -13, -14, -15, -16 PG-DSO-36-15 Product Name Product Type Package SLIC-E, SLIC-E2 PEF 4265 T, PEF 4265-2 T PG-DSO-20-24 SLIC-E, SLIC-E2 PEF 4265 V, PEF 4265-2 V PG-VQFN-48-15 TSLIC-E PEF 4365 T PG-DSO-36-15 Preliminary Data Sheet 8 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description 1.3 Logic Symbol Tip/Ring interface TIP CEXT RING IT IL PEF 4265 VDD AGND Power supply Figure 1 VHR BGND VBATL VBATH ACP ACN DCP DCN C1 C2 C3 Scaled line current outputs AC & DC input voltage Logic control Logic Symbol PEF 4265 Tip/Ring interface channel A CEXTA TIPA RINGA ITA ILA VDDA AGNDA channel A Power supply channel A VHRA BGNDA VBATH VBATLA Scaled line current outputs channel A ACPA ACNA DCPA DCNA AC & DC input voltage channel A C1A C2A Logic control channel A PEF 4365 Tip/Ring interface channel B RINGB ITB ILB VDDB AGNDB channel B Power supply channel B Figure 2 CEXTB TIPB VHRB BGNDB VBATH VBATLB Scaled line current outputs channel B ACPB ACNB DCPB DCNB AC & DC input voltage channel B C1B C2B Logic control channel B Logic Symbol PEF 4365 Preliminary Data Sheet 9 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description 1.4 Pin Configuration Pin counting is clockwise! IT Figure 4 1 RING IL 19 2 TIP C1 18 3 BGND C2 17 4 VHR C3 16 5 VDD DCP 15 6 VBATL SLIC-E PEF 4265 V2.1 PG-DSO-20-24 DCN 14 7 VBATH ACP 13 8 N.C. ACN 12 9 AGND N.C. 11 10 CEXT N.C. RING N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 36 35 34 33 32 31 30 29 28 27 26 25 Pin Configuration PG-DSO-20-24 Package (top view) N.C. 37 24 N.C. TIP 38 23 IT N.C. 39 22 IL BG ND 40 21 C1 VHR 41 20 C2 19 C3 18 DCP 17 DCN 16 ACP SLIC-E PEF 4265 V2.1 VDD 42 VBATL 43 VBATH 44 N.C. 45 N.C. 46 15 ACN AG ND 47 14 N.C. N.C. 48 13 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 CEXT N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. PG-VQFN-48-15 N.C. Figure 3 20 Pin Configuration PG-VQFN-48-15 Package (top view) Preliminary Data Sheet 10 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description Figure 5 RINGA 1 36 ITA TIPA 2 35 ILA BGNDA 3 34 C1A VHRA 4 33 C2A VDDA 5 32 DCPA VBATLA 6 31 DCNA 30 ACPA 29 ACNA 28 N.C. 27 ITB 26 ILB VBATH 7 AGNDA 8 CEXTA 9 RINGB 10 TIPB 11 BGNDB 12 25 C1B VHRB 13 24 C2B VDDB 14 23 DCPB VBATLB 15 22 DCNB TSLIC-E PEF 4365 V2.1 PG-DSO-36-15 VBATH 16 21 ACPB AGNDB 17 20 ACNB CEXTB 18 19 N.C. Pin Configuration PG-DSO-36-15 Package (dual channel) Preliminary Data Sheet 11 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description 1.5 Pin Definitions and Functions Table 1 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48-15 Pin No. DSO-20 Pin No. VQFN-48 Name Pin Type Function 1 35 RING I/O Subscriber loop connection RING 2 38 TIP I/O Subscriber loop connection TIP 3 40 BGND GND Battery ground: reference for TIP, RING, VBATH, VBATL and VHR 4 41 VHR PWR Auxiliary positive battery supply voltage used in ringing mode (5 V VHR 85 V) 5 42 VDD PWR Positive supply voltage (+3.3 or +5 V), referred to AGND 6 43 VBATL PWR Second negative battery supply voltage (-15 V VBATL VBATH) 7 44 VBATH PWR Most negative battery supply voltage; chip substrate potential (-20 V VBATH -85 V) 9 47 AGND GND Analog ground: reference for VDD and all signal and control pins except TIP and RING 10 2 CEXT O Common mode line potential with high output resistance (160 k); an external capacitance allows supply voltage filtering 12 13 15 16 ACN ACP I ACP - ACN: differential two-wire AC input voltage; at TIP/RING amplified by -6 14 15 17 18 DCN DCP I DCP - DCN: differential DC or ring input voltage; at TIP/RING amplified by -30 (ACTL, ACTH) and -60 (ACTR mode), respectively 16 19 C3 I Ternary logic input, controlling the operation mode internal pull-down (C3 = L, if not connected) 17 20 C2 I Ternary logic input, controlling the operation mode 18 21 C1 I/O Ternary logic input, controlling the operation mode in case of thermal overload (chip temperature exceeding 165 C) this pin sinks a current of typically 150 A. 19 22 IL O Current output: longitudinal line current scaled down by a factor of 100 20 23 IT O Current output: transversal line current scaled down by a factor of 50 8, 11 1) N.C. Not connected 1) For the PG-VQFN-48-15 package the following pins are not connected: 1,3,4,5,6,7,8,9,10,11,12,13,14,24,25,26,27,28,29,30,31,32,33,34,36,37,39,45,46,48 Preliminary Data Sheet 12 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description Table 2 Pin Definitions and Functions PG-DSO-36-15 Pin No. Name Pin Type Function 1 10 RINGA RINGB I/O Subscriber loop connection RING (Channel A) Subscriber loop connection RING (Channel B) 2 11 TIPA TIPB I/O Subscriber loop connection TIP 3 12 BGNDA BGNDB GND Battery ground: reference for TIP, RING, VBATH, VBATL and VHR 4 13 VHRA VHRB PWR Auxiliary positive battery supply voltage used in ringing mode (5 V VHR 85 V) 5 14 VDDA VDDB PWR Positive supply voltage (+3.3 or +5 V), referred to AGND 6 15 VBATLA VBATLB PWR Second negative battery supply voltage (-15 V VBATL VBATH) 7, 16 VBATH PWR Most negative battery supply voltage; chip substrate potential (-20 V VBATH -85 V) 8 17 AGNDA AGNDB GND Analog ground: reference for VDD and all signal and control pins except TIP and RING 9 18 CEXTA CEXTB O Common mode line potential with high output resistance (160 k); an external capacitance allows supply voltage filtering 29, 30 20, 21 ACNA, ACPA I ACNB, ACPB ACP - ACN: differential two-wire AC input voltage; at TIP/RING amplified by -6 31, 32 22, 23 DCNA, DCPA I DCNB, DCPB DCP - DCN: differential DC or ring input voltage; at TIP/RING amplified by -30 (ACTL, ACTH) and -60 (ACTR mode), respectively 33 24 C2A C2B I Ternary logic input, controlling the operation mode 34 25 C1A C1B I/O Ternary logic input, controlling the operation mode in case of thermal overload (chip temperature exceeding 165 C) this pin sinks a current of typically 150 A. 35 26 ILA ILB O Current output: longitudinal line current scaled down by a factor of 100 36 27 ITA ITB O Current output: transversal line current scaled down by a factor of 50 19, 28 N.C. Preliminary Data Sheet Not connected 13 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 General Description 1.6 Functional Block Diagram SLIC-E V2.1 AGND Off-hook BGND VHI (IT0 + I R0)/10 VDD VH switch (IT + I R)/100 Current Sensor PDRH BGND VHR IT (I T - IR)/200 IL IT0 ACN R/6 R VHI 5k + TIP IT R/30 *1 (*2) DCN VBI - + - V CM + VHI CEXT RING 5k IR0 VDOH VBATH IR R R/6 *1 (*2) DCP ACP PDRH Bias VBAT Switch VBI Mode Control VBATL Figure 6 R/30 + C1 C2 C3 Block Diagram Note: As in the dual channel version both channels "A" and "B" are identical, channel independent pin names (e.g. "TIP" instead of "TIPA / TIPB") are used throughout this document (with the exception of Table 2) Preliminary Data Sheet 14 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Functional Description 2 Functional Description A functional block diagram is shown in Figure 6. SLIC-E V2.1 supports AC and DC control loops based on feeding a voltage VTR to the line and sensing the transversal line current ITrans and the longitudinal current ILong. In receive direction, DC and AC voltages are handled separately with different gains. Both are applied differentially via the codec interface pins DCP / DCN and ACP / ACN, respectively, defining the transversal line voltage VTR through VTR = VTIP - VRING = Vab = = 30 * (VDCP - VDCN) + 6 * (VACP - VACN) for modes ACTH, ACTL = 60 * (VDCP - VDCN) + 6 * (VACP - VACN) for mode ACTR As the ring signal is processed in the DC path, the DC gain is doubled in the ring mode ACTR to enable the full output voltage swing. The common mode line voltage is always equal to the mean supply voltage, VCM = (VHI + VBI) / 2, leading to symmetrical line potentials with respect to the supplies. Depending on the operation mode, VHI is switched either to VHR or to BGND via the VH switch, whereas VBI is connected either to VBATH via the VBAT switch or to VBATL via an external diode. A reversed polarity of VTR is easily obtained by changing the polarity of (VDCP - VDCN). In transmit direction, the transversal and longitudinal line currents ITrans and ILong (Figure 7) are measured, and scaled images are provided at the IT and IL pins, respectively: IIT = (IT + IR) / 100 = ITrans / 50 ITrans = (IT + IR) / 2 IIL = (IT - IR) / 200 = ILong / 100 ILong = (IT - IR) / 2 For off-hook detection in PDRH mode, 5 k resistors are connected from TIP to BGND and from RING to VBATH, respectively. The currents through these resistors, IT0 and IR0, are sensed, scaled and provided at IT: IIT0 = (IT0 + IR0) / 10 = ITRANS0 / 5 IT VTIP TIP Z L/2 ITrans VTR ZL/2 VRING Figure 7 IR ILong VLong RING Transversal and Longitudinal Line Currents Preliminary Data Sheet 15 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Functional Description 2.1 Operating Modes SLIC-E V2.1 operates in the following modes controlled by ternary logic signals at C1, C2 and a binary signal at C3 (PEF 4265 only) Table 3 SLIC-E Mode Table C2 C1 L 1) L M H PDH PDRHL PDRH C33) H4) HIRT M L or N.C.2) ACTL ACTH ACTR L or N.C.2) H4) H HIRT HIT HIR H4) ACTH-R 1) 2) 3) 4) L or N.C.2) No `Overtemp' signaling possible via pin C1 if C1 is low. Register setting (VINETIC(R)): SEL-SLIC = (0001)hex Not connected in dual-channel version PEF 4365 Register setting (VINETIC(R)): SEL-SLIC = (0100)hex Table 4 SLIC-E Modes and Supplies Mode Mode Description Internal Supply Voltages VBI, VHI PDH Power Down High Impedance VBATH, VH switch open PDRH Power Down Resistive High VBATH, VH switch open PDRHL Power Down Resistive High Load VBATH, VH switch open ACTL Active Low VBATL, BGND ACTH Active High VBATH, BGND ACTH-R Active High Resistive VBATH, BGND ACTR Active Ring VBATH, VHR HIRT High Impedance on RING and TIP VBATH, VHR HIT High Impedance on TIP VBATH, VHR HIR High Impedance on RING VBATH, VHR Power Down High Impedance (PDH) PDH offers high impedance at TIP and RING; it can be used for testing purposes or when an error condition occurs. In PDH mode all functions are switched off. Off-hook detection is not available. Power Down Resistive High (PDRH) Power consumption is reduced to a minimum by switching completely off all voice transmission functions. To allow off-hook detection, PDRH provides a connection of 5 k each from TIP to BGND and RING to VBATH, respectively, while the output buffers show high impedance (see Figure 6). The current through these resistors is sensed, scaled by 1/5 and transferred to the IT pin for off-hook supervision. Power Down Resistive High Load (PDRHL) PDRHL is used as a transition state from Power Down to Active modes (automatically initiated during a mode change). It causes fast preloading of CEXT in order to suppress line voltage transients. Preliminary Data Sheet 16 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Functional Description Active Low (ACTL), Active High (ACTH) These are the regular transmission modes for voiceband. The line-driving section is operated between BGND and VBATL (ACTL) or VBATH (ACTH). Active High Resistive (ACTH-R) The SLIC is operated in Active High state together with the 5 k resistors from TIP to BGND and from RING to VBATH. This mode is intended to be used for line testing. Active Ring (ACTR) Utilizing an additional positive battery voltage VHR, this mode allows balanced ringing of up to 85 Vrms or feeding of very long telephone lines. In ACTR mode the DC voltage gain is doubled to 60. High Impedance (HIR, HIT, HIRT) In these modes each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while HIR switches off the RING buffer. The current through the active buffer is still sensed. In the HIRT mode both buffers show high impedance. The current sensor remains active thus allowing sensor offset calibration (for test purposes). 2.2 Current Limitation / Overtemperature Protection In any operating mode the total current delivered by the output drivers is limited to typically 85 mA. If, however, the junction temperature exceeds 165 C, the current limit is further reduced to keep the junction temperature constant. Simultaneously, pin C1 sinks a signalling current Itherm. Preliminary Data Sheet 17 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Typical Application Circuit for DuSLIC(R) and VINETIC(R) Typical Application Circuit for DuSLIC(R) and VINETIC(R) 3 Figure 8 to Figure 9 show one channel of application circuits including SLIC-E / TSLIC-E V2.1 and SLICOFI(R)-2/2S or VINETIC(R) codec (please refer to the latest DuSLIC(R) or VINETIC(R) Data Sheet). In Table 5 the recommended external components for a dual channel DuSLIC(R) or VINETIC(R) system and their typical values are listed. Table 5 External Components DuSLIC(R) / VINETIC(R) for 2 Channels No. Symbol Value Unit Relat. Tol. Rating DuSLIC(R) Systems VINETIC(R) Systems 2 RIT1 RIT1 RIT2 RIL RSTAB CSTAB 470 1% - x - 510 1% - - x 680 1% - x x 1.6 k 1% - x x - x x CDC CDC CITAC CITAC CPRE CVCMIT CREF CEXT C1 C1 C2 C3 D1 , D2 D33) 2 2 2 4 4 2 2 2 2 1 2 1 2 6 13 6 1 4 2 4) 1) 30 1% 15 (POTS) 22 (IVD) nF nF 10 % 10 % 100 V 100 V x x x x 120 nF 10 % 10 V x - 220 nF 10 % 10 V - x2) 680 nF 10 % 10 V x - 1 F 10 % 10 V - x 18 nF 5% 10 V - x 680 nF 10 % 10 V x - 68 nF 20 % 10 V x x 100 nF 20 % 50 V x x 100 nF 10 % 10 V x - 100 nF 10 % 10 V - x 100 nF 10 % 100 V x x 4.7 F 20 % 10 V, Tantal x - BAS 21 - - - x x BAS 21 - - - x x 2 OVP Overvoltage Protection - (e.g. thyristor) - - x x 4 OCP4) Overcurrent Protection (e.g. LFR, fuse, PTC) - - x x - 1) Matching tolerance depends on longitudinal balance requirements (for details see [2]). 2) With VINETIC(R)-2CPE this capacitance is substituted by 100 nF between DCN and DCP. 3) Due to the changed battery switch concept (see Figure 6), the VBATL series diode must not be shared between different channels; one diode per channel is mandatory (also for applications with TSLIC). 4) See [1] The C3 pin of SLIC-E V2.1 can be either * * Not connected (or connected to AGND) to be compatible with previous SLIC-E/-E2 versions or Connected to IO0x (IO2x) of VINETIC(R) (SLICOFI(R)-2/-2S) to offer an additional test mode ACTH-R. Preliminary Data Sheet 18 Revision 2.0, 2006-10-10 Figure 8 Preliminary Data Sheet OCP OCP OVPOVP Overvoltage protection 19 RSTAB C STAB BGND C STAB R STAB V B ATH SLIC-E VDD AGND D3 CEXT C EXT IL IT R IL A R IT2 A R IT1 A C REF CVCMITA C ITACA C DC GNDA GNDAB CREFAB VCMS VCM ILA VCMITA ITA ITACA CDCPA CDCNA DCNA C1A C2A DCN C1 C2 N.C. or IO2x ACPA ACNA DCPA C3 C1 V D DA ACP ACN DCP C2 VB ATL V B ATL D2 C2 V B A TH PEF 4265 V2.1 BGND RING TIP V HR C1 C2 D1 V DD V HR C1 VDD D GND C3 VD DPL L C1 GNDP IO0A ... IO4A GPIO0 ... GPIO7 SLICOFI-2 Channel A VD DR C1 V D D3 3 5 8 IOM-2 Interface PCM / C Interface SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Typical Application Circuit for DuSLIC(R) and VINETIC(R) Application Circuit DuSLIC(R) Revision 2.0, 2006-10-10 Figure 9 Preliminary Data Sheet OCP OCP OVPOVP Overvoltage protection 20 RSTAB CSTAB BGND CSTAB RSTAB V BATH SLIC-E VDD AGND D3 CEXT IL IT ACP ACN DCP DCN C1 C2 C3 C2 V BATL V BATL D2 C2 VBATH PEF 4265 V2.1 BGND RING TIP V HR C1 C2 D1 VDD V HR RILA RIT2A RIT1A CREF CPRE CITACA CDC N.C. or IO0x GNDA GNDAB CREFAB GNDP IO0A ... IO4A VREFAB C1 GPIO0 ... GPIO7 GND VINETIC-x VDD33x ...... C1 VDD33 VCMAB ILA VCMITA ITA ITACA CDCPA C1 Channel A VDD18x ...... CDCNA ACPA ACNA DCPA DCNA C1A C2A C1 VDD18 5 8 Parallel Interface PCM / C Interface SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Typical Application Circuit for DuSLIC(R) and VINETIC(R) Application Circuit VINETIC(R) Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Table 6 Absolute Maximum Ratings Parameter Symbol Battery voltage low Battery voltage high Battery voltage difference Auxiliary supply voltage Values Unit Note / Test Condition Min. Typ. Max. VBATL VBATH VBATL - VBATH VHR VHR - VBATH -85 - 0.4 V Referred to BGND -90 - 0.4 V Referred to BGND -0.4 - - V - -0.4 - 90 V Referred to BGND -0.4 - 160 V - -0.4 - 7 V Referred to AGND -0.4 - 0.4 V - -0.4 - VDD + 0.4 V Referred to AGND Junction temperature VDD VBGND - VAGND VDCP, VDCN, VACP, VACN, VC1, VC2, VC3 Tj - - 150 C - ESD voltage, all pins - - - 1 kV SDM (Socketed Device Model)1) - - - 1 kV HBM (Human Body Model)1) Total battery supply voltage, continuous VDD supply voltage Ground voltage difference Input voltages 1) EOS/ESD Assn. Standard DS5.3-1993. Attention: Stresses exceeding the max. values listed above may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 Foreign Line Voltages External voltages applied at the line outputs may cause large currents in the SLIC. The resulting on-chip power dissipation has to be limited to avoid thermal destruction, if the overtemperature protection cannot react sufficiently fast due to high local power density. The safe power dissipation values are strongly dependent on duration. They can be expressed in terms of voltage and current limits directly at the TIP and RING pins (see Table 7 and Table 8). Table 7 Voltage Limits on Output Pins Voltage Duration Pins Min. Voltage [V] Max. Voltage [V] Continuous TIP, RING < 10 ms TIP, RING < 100 s TIP, RING < 1 s TIP, RING VBATH - 0.4 VBATH - 5 VBATH - 10 VBATH - 15 VHR + 5 VHR + 10 VHR + 20 VHR + 40 Preliminary Data Sheet 21 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics Table 8 Current Limits on Output Pins Current Duration Pins Min. current [A] Max. current [A] Continuous TIP, RING - 0.1 0.1 < 10 ms TIP, RING - 0.5 0.5 < 100 s TIP, RING - 1.0 1.0 < 1 s TIP, RING - 1.5 1.5 The above limitations have to be regarded as typical. They are valid simultaneously. Together with external circuitry they determine protection requirements (see [1]). 4.3 Operating Range Table 9 Operating Range Parameter Symbol 1) VBATL VBATH VHR VHR - VBATH VDD VBGND - VAGND VIT, VIL Battery voltage L Battery voltage H Values 1) Auxiliary supply voltage Total battery supply voltage VDD supply voltage Ground voltage difference Voltage at pins IT, IL Input range VDCP, VDCN, VACP, VACN Tamb TJ Ambient temperature Junction temperature Unit Note / Test Condition Min. Typ. Max. -80 - -15 V Referred to BGND -85 - -20 V Referred to BGND VDD - 85 V Referred to BGND - - 150 V - 3.15 - 5.5 V Referred to AGND -0.4 - 0.4 V - -0.4 - VDD - 0.6 V Referred to AGND 0 - 3.3 V Referred to AGND -40 - 85 C - - - 1252) C - 1) If the battery switch is not used, VBATL has to be connected with VBATH 2) Operation up to TJ = 150 C possible. However, a permanent junction temperature exceeding 125 C could degrade device reliability. 4.4 Thermal Resistances Table 10 Thermal Resistances Parameter Symbol Rth, jC Junction to ambient Rth, jA Junction to case Junction to ambient Rth, jA Preliminary Data Sheet Values Unit Note / Test Condition Min. Typ. Max. - 2 - K/W All packages - 50 - K/W PG-DSO-20-24 without heatsink - 20 - K/W PG-DSO-20-24 with heatsink PG-DSO-36-15, 4-layer JEDEC PCB with vias, die pad soldered to PCB (footprint see Chapter 6.3.1) - 25 - K/W PG-VQFN-48-15, 4-layer JEDEC PCB with vias, die pad soldered to PCB (footprint see Chapter 6.2.1) 22 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics 4.5 Electrical Parameters Unless otherwise stated, minimum and maximum values are valid within the full operating range. Testing is performed according to the specific test figures at VBATH = -48 V, VBATL = -24 V, VHR = +32 V and VDD = +3.3 V. Functionality and performance is guaranteed for TA = 0 to 70 C by production testing. Extended temperature range operation at -40 C < TA < 85 C is guaranteed by design, characterization and periodically sampling and testing production devices at the temperature extremes. 4.5.1 Supply Currents and Power Dissipation Table 11 Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel) Parameter Symbol Values Min. Typ. Unit Note / Test Condition No. Max. Power Down High Impedance, Power Down Resistive High VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR - 250 350 A - 1 - 40 80 A - 2 - 0 10 A - 3 - 0 10 A - 4 IDD IBATH IBATL IHR - 2.2 2.8 mA - 5 - 40 80 A - 6 - 3.3 4 mA - 7 - 0 10 A - 8 IDD IBATH IBATL IHR - 2.6 3.2 mA - 9 - 3.8 4.5 mA - 10 - 0 10 A - 11 - 0 10 A - 12 IDD IBATH IBATL IHR - 1.5 2 mA - 13 - 3.5 4.3 mA - 14 - 0 10 A - 15 - 1.8 2.3 mA - 16 - 1.5 2 mA - 17 - 2.9 3.6 mA - 18 - 0 10 A - 19 - 1.3 1.7 mA - 20 1.4 1.8 mA - 21 2.2 2.8 mA - 22 Active Low VDD current VBATH current VBATL current1) VHR current Active High VDD current VBATH current2) VBATL current VHR current Active Ring VDD current VBATH current3) VBATL current VHR current4) High Impedance on TIP or RING (HIR, HIT) VDD current VBATH current VBATL current VHR current IDD IBATH IBATL IHR High Impedance on TIP and RING (HIRT) VDD current VBATH current Preliminary Data Sheet IDD IBATH - 23 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics Table 11 Supply Currents, Power Dissipation (IR = IT = 0; VTR = 0; one channel) (cont'd) Parameter Symbol VBATL current VHR current 1) 2) 3) 4) IBATL IHR Values Unit Note / Test Condition No. Min. Typ. Max. - 0 10 A - 23 - 0.8 1.1 mA - 24 Current depending on supply voltage: IBATL (VBATL) = BATL (-24V) + (-VBATL - 24) / 40k Current depending on supply voltage: IBATH (VBATH) = IBATH (-48V) + (-VBATH - 48) / 40k Current depending on line voltage: IBATH (VTR) = IBATH (0) + |VTR| / 40k Current depending on line voltage: IHR (VTR) = IHR (0) + |VTR| / 60k The total power dissipated in the SLIC consists of the quiescent power PQ due to the supply currents and the output stage power PO caused by any line current ITrans (see Table 12). Ptot = PQ + PO with PQ = VDD * IDD + IVBATHI * IBATH + IVBATLI * IBATL + VHR * IHR Table 12 Output Stage Power Dissipation Operating Mode Equation for PO Calculation ACTL ACTH ACTR Comment PO = (1.05 * |VBATL| - VTR) * ITrans PO = (1.05 * |VBATH| - VTR) * ITrans PO = (1.02 * VHR + 1.05 * |VBATH| - VTR) * ITrans PO = [4 * (VH + |VBATH|) - * VP * cos ] * VP / (2 * * ZL) - - Ohmic load complex load Z = ZLei, VP ... peak ring voltage For the dual channel version, the power values of each channel have to be added to yield the total power dissipation. Preliminary Data Sheet 24 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics 4.5.2 DC Characteristics Table 13 DC Characteristics (VACP = VACN = 1.5 V) Parameter Symbol Values Unit Note / Test Condition No. Min. Typ. Max. -0.4 0 0.4 V VDCP = VDCN = 1.5 V 23.5 24 24.5 V VDCP - VDCN = 0.8 V Line Termination TIP, RING Differential DC line voltage VTR, DC 25 Modes: ACTx 26 Mode: ACTH -24.5 -24 -23.5 V VDCP - VDCN = -0.8 V 27 Mode: ACTH Common mode DC line voltage DC line voltage drop (see Figure 10) Output current limit (see Figure 15) VTIP, DC = = VRING, DC - VBATH - -13 -12 -11 V Mode: ACTL 28 -25 -24 -23 V Mode: ACTH 29 -10 -9 -8 V Mode: ACTR 30 - 2.5 3 V ITrans,DC = 20 mA VDCP - VDCN = 2.5 V 31 VT,VR = 0 (sinking) VT,VR = VBATx 32 VTR, max |IR, max|, |IT, max| Temp = 25C1) Mode: ACTH 70 85 100 mA 80 100 120 mA (sourcing) Temp = 25C2) 33 Open loop resistance TIP to VBGND (see Figure 16) RTG 4.2 5 5.8 k Temp = 25C3) Mode: PDRH 34 Open loop resistance RING to VBATH (see Figure 16) RRB 4.2 5 5.8 k Temp = 25C3) Mode: PDRH 35 44 47 V Mode: PDRH 36 -10 - 10 A VBATH < VT/R < 0 37 -10 - 10 A Mode: PDH 38 -10 - 10 A VBATH < VR < VHR 39 42 Power down open loop line VTR,PD = = - VBATH - VDOH voltage Power down output leakage current High impedance output leakage current ILeak,R ILeak,T ILeak,R Mode: HIR, HIRT ILeak,T -10 - 10 A VBATH < VT < VHR 40 Mode: HIT, HIRT Inputs DCP, DCN, ACP, ACN, Output CEXT Input current DCP, DCN Differential AC input resistance ACP, ACN IDC RAC Output resistance on CEXT - - 0.1 - A - 41 - 20 - k - 42 - 100 - k - 43 -15 0 15 A 44 380 400 420 A IR = IT = 0 mA IR = IT = 20 mA Current Outputs IT, IL IT output current IT output current normal polarity Preliminary Data Sheet IIT IIT 25 45 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics Table 13 DC Characteristics (VACP = VACN = 1.5 V) (cont'd) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition No. IT output current reverse polarity4) IIT -420 -400 -380 A IR = IT = -20 mA 46 Transversal current ratio (see Figure 18)5) 1/GIT,DC 49.5 50 50.5 - IR = IT = 20 mA, IR = IT = -20 mA 47 800 950 1100 A TIP/RING shorted, Temp = 25 C6) Mode: PDRH 48 -20 0 20 A 30 50 70 A -160 -125 -90 A IR = IT = 20 mA 49 IR = 15 mA, IT = 25 mA 50 IR = 50 mA, IT = 25 mA 51 2.7 - VDD + V - 52 Off-hook output current on - IT IL output current (see Figure 18) IIL Control Inputs C1, C2, C3 H-input voltage VIH 0.3 M-input voltage L-input voltage Input pull down current Thermal overload current C1 Thermal overload threshold temperature VIM VIL Iin Itherm 1.2 - 2.1 V C1, C2 only 53 -0.3 - 0.6 V - 54 0 2 10 A C1, C2, C3 55 120 150 250 A VC1 = 1.20 V 56 TjLIM - 165 - C Mode: ACTx, HIx 57 1) 2) 3) 4) The systematic temperature dependence is appr. + 7 mV / C The systematic temperature dependence is appr. -0.3 % / C The systematic temperature dependence is appr. +0.1 %/ C With VDD = 3.3 V, the IT output current in reverse polarity is limited to typically 700 A; thus, the DC current regulation loop operates correctly only up to the corresponding line current value of 35 mA. In all other cases, IT is linear within the full line current range 5) The offset (IR = IT = 0 mA) has to be taken into account. 6) The systematic temperature dependence is appr. -0.1 %/ C Preliminary Data Sheet 26 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics 9 8 7 ACTR V drop [V] 6 5 ACTH, ACTL 4 3 2 1 0 0 10 20 30 40 50 60 Itrans [mA] Figure 10 Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR 4.5.3 AC Characteristics If not otherwise stated, AC characteristics are tested at a DC line current of 25 mA and -25 mA, respectively; they are valid in all active modes. Table 14 AC Characteristics Parameter Symbol Values Unit Min. Typ. Max. Receive gain (see Figure 18) Gr 5.925 6.0 6.075 - Total harmonic distortion VTR THD (see Figure 18) - 0.01 - % - 0.1 - % - 0.2 - % Note / Test Condition No. VACP - VACN = 640 mVrms, f = 1015 Hz VACP - VACN = 640 mVrms, f = 1015 Hz VTR,AC = 5 Vrms, f = 16 kHz, RL = 200 VTR,AC = 5 Vrms, f = 16 kHz, RL = 200 , ITrans,DC = 0 mA 58 Line Termination TIP, RING Teletax distortion THDTTX Psophometric noise (see Figure 18 ) NpVTR - -82 -78 dBmp - Longitudinal to transversal rejection ratio Vlong/VTR (see Figure 19) LTRR - 80 - dB 54 58 - dB 52 56 - dB LTRRloop Longitudinal to transversal rejection ratio Vlong/VTR (loop) PEF 4265, PEF 4365 (see Figure 19) Preliminary Data Sheet 27 59 60 61 62 Vlong = 3 Vrms, 300 Hz < f < 3.4 kHz Vlong = 3 Vrms 300 Hz < f < 1kHz f = 3.4 kHz 63 64 65 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics Table 14 AC Characteristics (cont'd) Parameter Symbol Values Min. LTRR-2loop Longitudinal to transversal 61 rejection ratio Vlong/VTR (loop) PEF 4265-2 56 (see Figure 19) Transversal to longitudinal rejection ratio VTR/Vlong(see Figure 21) TLRR Power supply rejection ratio (see Figure 11, Figure 12, Figure 14, Figure 14) PSRR VBATL/VTR VBATH/VTR VHR/VTR VDD/VTR Interchannel crosstalk 48 Unit Note / Test Condition No. Vlong = 3 Vrms 300 Hz < f < 1kHz f = 3.4 kHz 66 Typ. Max. 65 - dB 60 - dB 60 - dB 67 VACP - VACN = 1920 mVrms, 68 300 Hz < f < 3.4 kHz VSupplyAC = 100 mVp, 300 Hz < f < 3.4 kHz 40 60 - dB 69 40 60 - dB 70 33 50 - dB 71 33 50 - dB 72 -80 - dB 300 Hz < f < 3.4 kHz both channels active 73 -80 - dB One channel active, one channel power down 74 1) Ringing amplitude TIP/RING VRNG0 - 85 - Vrms VDCP - VDCN = 0.15 V (DC) 75 Ringing distortion (see Figure 22) RD - 0.1 - % + 1.42 Vrms (sine wave, 20Hz) RR = 450 , CR = 3.4 F, Mode: ACTR 76 Transversal Current IT2) Transversal current ratio (see Figure 18) 1/Git 49.5 50 50.5 49 50 51 VACP - VACN = 640 mVrms, f = 1015 Hz ITrans,DC = 25 mA ITrans,DC = -25 mA VACP - VACN = 640 mVrms, f = 1015 Hz Total harmonic distortion VIT THDIT - 0.02 0.3 Psophometric noise (see Figure 18) NpVIT - -110 -105 dBmp - Longitudinal to transversal current output rejection ratio Vlong/VIT (see Figure 19) LITRR - 85 - Power supply rejection ratio PSRR VBATL/VIT VBATH/VIT VHR/VIT VDD/VIT % dB 77 78 79 80 Vlong = 3 Vrms, 300 Hz < f < 3.4 kHz VSupplyAC = 100 mVp, 300 Hz < f < 3.4 kHz 81 50 70 - dB 50 70 - dB 83 50 70 - dB 84 50 70 - dB 85 82 1) Dual channel version PEF 4365 only 2) Unless otherwise specified, characteristics are valid for both DC line current directions (normal and reverse polarity) Preliminary Data Sheet 28 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics 4.5.3.1 Frequency Dependence of PSRR PSRR VBATL / VTR 0 VBATL / VTR [dB] 10 20 30 40 50 60 70 0.1 1 10 100 1000 100 1000 Frequency [kHz] Figure 11 Typical Frequency Dependence of PSRR VBATL/VTR PSRR VBATH / VTR 0 V BATH / VTR [dB] 10 20 30 40 50 60 70 Figure 12 0.1 1 10 Frequency [kHz] Typical Frequency Dependence of PSRR VBATH/VTR Preliminary Data Sheet 29 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Electrical Characteristics PSRR VHR / VTR 0 V HR / VTR [dB] 10 20 30 40 50 60 70 Figure 13 0.1 1 10 Frequency [kHz] 100 1000 100 1000 Typical Frequency Dependence of PSRR VHR/VTR PSRR VDD / VTR 0 10 VDD / V TR [dB] 20 30 ACTR 40 50 ACTL, ACTH 60 70 0.1 1 10 Frequency [kHz] Figure 14 Typical Frequency Dependence of PSRR VDD/VTR Preliminary Data Sheet 30 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Test Figures 5 Test Figures VT or VR connected to: BGND, VBATH (ACTH) BGND, VBATL (ACTL) VHR, VBATH (ACTR) IT IL 1 k 1.6 k IT,max VT ACN 30 TIP ~ VAC = 0 PEF 4265 V2.1 ACP 15 nF CEXT 30 100 nF RING IR,max VR = 1.5 V DCP 15 nF = VDC = 0 DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 15 VHR BGND +32 V Output Current Limit RTG = VT / 2 mA RRB = VR / 2 mA IT IL 1 k 1.6 k 30 TIP 2 mA ACN 15 nF ~ VAC = 0 PEF 4265 V2.1 VBATH ACP CEXT 100 nF 30 RING 2 mA = VDC = 0 VBATH DCN VBATL VBATH VDD AGND C1 C2 C3 VHR BGND +32 V -24 V -48 V +5 V Figure 16 = 1.5 V DCP 15 nF Output Resistance PDRH, PDRHL Preliminary Data Sheet 31 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Test Figures IT IIT = -VIT / 1 k 1 k IL I IL = -VIL / 2 k V IT 1.6 k V IL 30 IT TIP ACN 15 nF ~ V AC = 0 PEF 4265 V2.1 ACP CEXT 100 nF 30 RING = VDC = 0 15 nF DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 17 = 1.5 V DCP IR VHR BGND +32 V Current Outputs IT, IL G r = VTR,AC / VAC G IT = - (VIT,AC / 1000) / (VTR,AC / 660) IT IL 1 k V IT 1.6 k 30 TIP ACN 15 nF R L= 600 ~ V AC = 0 PEF 4265 V2.1 VTR , AC ACP CEXT 100 nF 30 RING = 1.5 V DCP 15 nF = DCN VBATL VBATH VDD AGND -24 V -48 V +5 V Figure 18 C1 C2 C3 VHR BGND VDC = ITR * 660 / 30 +32 V Transmission Characteristics Preliminary Data Sheet 32 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Test Figures LTRR = Vlong / VTR,AC LITRR = Vlong / VIT IT IL 1 k V IT 1.6 k 30 300 V long TIP 15 nF ~ ACN ~ V AC = 0 PEF 4265 V2.1 V TR, AC ACP CEXT 300 100 nF 30 RING = 1.5 V DCP 15 nF = DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 19 VHR BGND V DC = I TR * 660 / 30 +32 V Longitudinal to Transversal Rejection LTRRloop = Vlong / VTR,AC VACP - ACN = G loop * VIT,AC IT Gloop = 4.5 IL 1 k 1.6 k 30 TIP 300 V long ACN 15 nF ~ PEF 4265 V2.1 V TR, AC Gloop ACP CEXT 300 100 nF 30 RING = 1.5 V DCP 15 nF = DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 20 VHR BGND VDC = I TR * 660 / 30 +32 V Longitudinal to Transversal Rejection Loop Preliminary Data Sheet 33 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Test Figures TLRR = VTR / Vlong IT IL 1 k 1.6 k 30 TIP Vlong ACN 300 15 nF ~ PEF 4265 V2.1 VTR ACP VAC = 1.92 Vrms CEXT 300 100 nF RING 30 = 1.5 V DCP 15 nF = DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 21 VHR VDC = ITR * 660 / 30 BGND +32 V Transversal to Longitudinal Rejection IT IL 1 k 1.6 k 30 TIP V RNG 450 15 nF ACN ~ VAC = 0 PEF 4265 V2.1 ACP CEXT 3.4 F 100 nF 30 RING = 1.5 V DCP 15 nF = DCN VBATL VBATH VDD AGND C1 C2 C3 -24 V -48 V +5 V Figure 22 VHR BGND V DC = 0.15 V + 1.42 Vrms +32 V Ring Amplitude Preliminary Data Sheet 34 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Package Outlines 110.15 1) 1.2 -0.3 -0.02 5 3 B 6.3 (Mold) 0.25 +0.07 PG-DSO-20-24 Package 1.3 6.1 3.55 MAX. Package Outlines 0.3 0.05 3.25 0.1 6 2.8 0.1 1.27 0.4 +0.13 0.95 0.15 14.2 0.3 0.25 M 10 20 11 13.7 -0.2 (Metal) 15.9 0.15 1) 3.2 0.1 (Metal) 5.9 0.1 (Metal) 1 x 45 1 0.25 B A 20x Heatslug Bottom View 10 1 11 20 A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side GPS05755 Figure 23 Package Outline for PG-DSO-20-24 (Plastic Green Dual Small Outline) Notes 1. Heatsink on top - pin counting clockwise (top view) 2. Dimensions in mm Attention: The heatsink is connected to VBATH via the chip substrate. Due to the high voltage of up to 150 V between VHR and VBATH, touching of the heatsink or any attached conducting part can be hazardous. Preliminary Data Sheet 35 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Package Outlines 6.2 PG-VQFN-48-15 Package Figure 24 Package Outline for PG-VQFN-48-15 (Plastic Green Very thin Profile Quad Flatpack No-lead) Note: Dimensions in mm Attention: The exposed die pad and the die pad edges are connected to VBATH via the chip substrate. Due to the high voltage of up to 150 V between VHR and VBATH, touching of the die pad or any attached conducting part can be hazardous. 6.2.1 Recommended PCB Foot Print Pattern for PG-VQFN-48-15 Package For detailed information on PCB related thermal and soldering issues of the PG-VQFN-48-15 package see [3], chapter 3 and 4. Preliminary Data Sheet 36 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Package Outlines 0.65 0.25 +0.13 +0.07 -0.02 B 6.3 0.1 C (Mold) 5 3 0.25 2.8 1.3 15.74 0.1 (Heatslug) 36x 0.25 11 0.15 1) 3.5 MAX. 1.1 0.1 3.25 0.1 PG-DSO-36-15 Package 0 +0.1 6.3 Heatslug 0.95 0.15 M A B C 14.2 0.3 0.25 B 19 19 1 18 10 36 5.9 0.1 (Metal) 36 3.2 0.1 (Metal) Bottom View Index Marking 1 x 45 15.9 0.1 1) (Mold) 1) Figure 25 A 13.7 -0.2 (Metal) 1 Heatslug Does not include plastic or metal protrusion of 0.15 max. per side Package Outline for PG-DSO-36-15 (Plastic Green Dual Small Outline) Notes 1. Heatslug down version - pin counting counterclockwise (top view) 2. Dimensions in mm Attention: The heatslug is connected to VBATH via the chip substrate. Due to the high voltage of up to 150 V between VHR and VBATH, touching of the heatsink or any attached conducting part can be hazardous. Preliminary Data Sheet 37 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 Package Outlines 6.3.1 Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package The heatslug is soldered to the PCB according to Figure 25. For improved thermal behaviour the utilization of another PCB metal layer as an additional cooling area is recommended. These copper areas should be both electrically separated from each other and floating, i. e. they must not be connected with any other metallic part on the PCB. 1 .8 3 9 .5 5 .9 3 .2 H e a tslu g o u tlin e 0.65 13.7 15.9 0.33 P a cka g e o u tlin e 1 3 .4 8 C u laye r w ith solde r resist coa tin g F lash A u re co m m end ed, free o f solder re sist V ia hole Figure 26 Footprint for PG-DSO-36-15 Preliminary Data Sheet 38 Revision 2.0, 2006-10-10 SLIC-E / TSLIC-E PEF 4265 / PEF 4365 References References [1] SLIC-E/-E2 / TSLIC-E (PEB 4265/-2 / PEB 4365) Application Note "Protection for SLIC-E / -E2 against Overvoltages and Overcurrents according to ITU-T K. 20/K.21/K.45" Rev. 1.0, 2004-06-29 [2] VINETIC(R) Version 1.4 Prel. Application Note External Components Rev. 2.0, 2005-09-06 [3] Recommendations for Printed Circuit Board Assembly of Infineon P(G)-VQFN Packages, Application Support, DS3, 2006-03-03 Preliminary Data Sheet 39 Revision 2.0, 2006-10-10 www.infineon.com Published by Infineon Technologies AG