Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. 8-Bit Buffers/Line Drivers SCCS029 - May 1994 - Revised March 2000 Features CY54/74FCT540T CY54/74FCT541T Functional Description * Function, pinout, and drive compatible with FCT and F logic * FCT-C speed at 4.1 ns max. (Com'l) FCT-A speed at 4.8 ns max. (Com'l) * Reduced VOH (typically = 3.3V) versions of equivalent FCT functions * Edge-rate control circuitry for significantly improved noise characteristics * Power-off disable feature * ESD > 2000V * Matched rise and fall times * Fully compatible with TTL input and output logic levels * Sink current 64 mA (Com'l), 48 mA (Mil) Source current 32 mA (Com'l), 12 mA (Mil) * Extended commercial range of -40C to +85C Logic Block Diagram--FCT540T OEA OEB The FCT540T inverting buffer/line driver and the FCT541T non-inverting buffer/line driver are designed to be employed as memory address drivers, clock drivers, and bus-oriented transmitters/receivers. The devices provide speed and drive capabilities equivalent to their fastest bipolar logic counterparts while reducing power dissipation. The input and output voltage levels allow direct interface with TTL, NMOS, and CMOS devices without external components. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Pin Configurations CERDIP/SOIC/QSOP Top View OEA 1 20 D0 O0 D0 2 19 OEB D1 O1 D1 3 18 O0 D2 4 17 O1 D3 5 16 O2 D4 6 15 O3 D5 7 14 O4 D6 8 13 O5 D7 9 12 O6 GND 10 11 O7 D2 D3 O2 O3 D4 O4 D5 O5 D6 O6 D7 O7 FCT540T VCC Logic Block Diagram--FCT541T OEA OEB CERDIP/DIP/SOIC/QSOP Top View OEA 1 20 D0 O0 D0 2 19 OEB D1 O1 D1 3 18 O0 D2 4 17 O1 D3 5 16 O2 D4 6 15 O3 D5 7 14 O4 D6 8 13 O5 D7 9 12 O6 GND 10 11 O7 D2 D3 O2 O3 D4 O4 D5 O5 D6 O6 D7 O7 FCT541T VCC Copyright (c) 2000, Texas Instruments Incorporated CY54/74FCT540T CY54/74FCT541T Storage Temperature ................................. -65C to +150C Function Table FCT540T[1] Ambient Temperature with Power Applied............................................. -65C to +135C Inputs OEA OEB D Output Supply Voltage to Ground Potential ............... -0.5V to +7.0V L L H L L H L H X H L Z DC Input Voltage ........................................... -0.5V to +7.0V DC Output Voltage......................................... -0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ...... 120 mA Function Table FCT541T[1] Power Dissipation .......................................................... 0.5W Inputs OEA OEB D Output L L H L L H L H X L H Z Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Operating Range Maximum Ratings[2, 3] (Above which the useful life may be impaired. For user guidelines, not tested.) Ambient Temperature Range Range VCC Commercial T, AT, CT -40C to +85C 5V 5% Military[4] All -55C to +125C 5V 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions Min. Typ.[5] Max. Unit VCC = Min., IOH = -32 mA Com'l 2.0 V VCC = Min., IOH = -15 mA Com'l 2.4 3.3 V VCC = Min., IOH = -12 mA Mil 2.4 3.3 V VCC = Min., IOL = 64 mA Com'l 0.3 0.55 V VCC = Min., IOL = 48 mA Mil 0.3 0.55 V VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage VH Hysteresis[6] All inputs 0.2 VIK Input Clamp Diode Voltage VCC = Min., IIN = -18 mA -0.7 II Input HIGH Current IIH Input HIGH Current IIL Input LOW Current IOZH Off State HIGH-Level Output Current IOZL 0.8 V V -1.2 V VCC = Max., VIN = VCC 5 A VCC = Max., VIN = 2.7V 1 A VCC = Max., VIN = 0.5V 1 A VCC = Max., VOUT = 2.7V 10 A Off State LOW-Level Output Current VCC = Max., VOUT = 0.5V -10 A IOS Output Short Circuit Current[7] VCC = Max,. VOUT = 0.0V -225 mA IOFF Power-Off Disable VCC = 0V, VOUT = 4.5V 1 A -60 -120 Notes: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance 2. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. TA is the "instant on" case temperature. 5. Typical values are at VCC=5.0V, TA=+25C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parametric tests, IOS tests should be performed last. 2 CY54/74FCT540T CY54/74FCT541T Capacitance[6] Parameter Description Test Conditions Typ. [5] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Power Supply Characteristics Parameter Description Test Conditions Typ.[5] Max. Unit ICC Quiescent Power Supply Current VCC=Max., VIN 0.2V, VIN VCC-0.2V 0.1 0.2 mA ICC Quiescent Power Supply Current (TTL inputs) VCC = Max., VIN = 3.4V, f1 = 0, Outputs Open[8] 0.5 2.0 mA ICCD Dynamic Power Supply Current[9] VCC = Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1 = 10 MHz, OEA=OEB=GND, or OEA=GND, OEB=VCC, VIN 0.2V or VIN VCC-0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[10] VCC=Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OEA=OEB=GND, or OEA=GND, OEB=VCC, VIN0.2V or VINVCC-0.2V 0.7 1.4 mA VCC = Max., 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=10 MHz, OEA=OEB=GND, or OEA=GND, OEB=VCC, VIN = 3.4V or VIN = GND 1.0 2.4 mA VCC = Max., 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1= 2.5 MHz, OEA=OEB=GND, or OEA=GND, OEB=VCC, VIN 0.2V or VIN VCC -0.2V 1.3 2.6[11] mA VCC = Max., 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=2.5 MHz, OEA=OEB=GND, or OEA=GND, OEB=VCC, VIN = 3.4V or VIN = GND 3.3 10.6[11] mA Notes: 8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 10. IC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 3 CY54/74FCT540T CY54/74FCT541T Switching Characteristics Over the Operating Range[12] FCT540T/FCT541T FCT540AT/FCT541AT Commercial Parameter Description Commercial Min. Max. Min. Max. Unit Fig. No.[13] tPLH tPHL Propagation Delay Data to Output (FCT540) 1.5 8.5 1.5 4.8 ns 1, 2 tPLH tPHL Propagation Delay Data to Output (FCT541) 1.5 8.0 1.5 4.8 ns 1, 3 tPZH tPZL Output Enable Time 1.5 10.0 1.5 6.2 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 9.5 1.5 5.6 ns 1, 7, 8 FCT540DT/ FCT541DT FCT540CT/FCT541CT Military Parameter Description Commercial Commercial Min. Max. Min. Max. Min. Max. Unit Fig. No.[13] tPLH tPHL Propagation Delay Data to Output (FCT540) 1.5 4.7 1.5 4.1 1.5 3.8 ns 1, 2 tPLH tPHL Propagation Delay Data to Output (FCT541) 1.5 4.6 1.5 4.1 1.5 3.8 ns 1, 3 tPZH tPZL Output Enable Time 1.5 6.5 1.5 5.8 1.5 5.2 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 5.7 1.5 5.2 1.5 5.0 ns 1, 7, 8 Shaded areas contain preliminary information. Notes: 12. Minimum limits are specified but not tested on Propagation Delays. 13. See "Parameter Measurement Information" in the General Information section. 4 CY54/74FCT540T CY54/74FCT541T Ordering Information--FCT540T Speed (ns) Ordering Code Package Name Package Type Operating Range 4.1 CY74FCT540CTQCT Q5 20-Lead (150-Mil) QSOP Commercial 4.7 CY54FCT540CTDMB D6 20-Lead (300-Mil) CerDIP Military Ordering Information--FCT541T Speed (ns) 4.1 Ordering Code Package Name Package Type Operating Range CY74FCT541CTQCT Q5 20-Lead (150-Mil) QSOP CY74FCT541CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC 4.6 CY54FCT541CTDMB D6 20-Lead (300-Mil) CerDIP Military 4.8 CY74FCT541ATPC P5 20-Lead (300-Mil) Molded DIP Commercial CY74FCT541ATQCT Q5 20-Lead (150-Mil) QSOP CY74FCT541ATSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC CY74FCT541TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC 8.0 Document #: 38-00260-B Package Diagrams 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config.A 5 Commercial Commercial CY54/74FCT540T CY54/74FCT541T Package Diagrams (continued) 20-Lead (300-Mil) Molded DIP P5 20-Lead Quarter Size Outline Q5 6 CY54/74FCT540T CY54/74FCT541T Package Diagrams (continued) 20-Lead (300-Mil) Molded SOIC S5 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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