Vishay Siliconix
Si4160DY
New Product
Document Number: 69069
S-83092-Rev. A, 29-Dec-08
www.vishay.com
1
N-Channel 30-V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• 100 % UIS Tested
APPLICATIONS
• Notebook
- Vcore low side
- DC/DC
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)ID (A)aQg (Typ.)
30
0.0049 at VGS = 10 V 25.4
16.9 nC
0.0063 at VGS = 4.5 V 22.4
SO-8
SD
SD
SD
GD
5
6
7
8
Top View
2
3
4
1
Ordering Information: Si4160DY-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET
G
D
S
Notes:
a. Based on TC = 25 °C.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under Steady State conditions is 85 °C/W.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS 30 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
25.4
A
TC = 70 °C 20.2
TA = 25 °C 16.8b, c
TA = 70 °C 13.4b, c
Pulsed Drain Current IDM 70
Continuous Source-Drain Diode Current TC = 25 °C
IS
5.1
TA = 25 °C 2.2b, c
Single Pulse Avalanche Current L = 0.1 mH IAS 30
Avalanche Energy EAS 45 mJ
Maximum Power Dissipation
TC = 25 °C
PD
5.7
W
TC = 70 °C 3.6
TA = 25 °C 2.5b, c
TA = 70 °C 1.6b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, d t ≤ 10 s RthJA 39 50 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 18 22
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Document Number: 69069
S-83092-Rev. A, 29-Dec-08
Vishay Siliconix
Si4160DY
New Product
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 30 V
VDS Temperature Coefficient ΔVDS/TJID = 250 µA 29 mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ- 5.5
Gate-Source Threshold Voltage VGS(th) VDS = VGS , ID = 250 µA 1.0 2.4 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 30 V, VGS = 0 V 1µA
VDS = 30 V, VGS = 0 V, TJ = 55 °C 10
On-State Drain CurrentaID(on) V
DS ≥ 5 V, VGS = 10 V 30 A
Drain-Source On-State ResistanceaRDS(on)
VGS = 10 V, ID = 15 A 0.004 0.0049 Ω
VGS = 4.5 V, ID = 10 A 0.0051 0.0063
Forward Transconductanceagfs VDS = 15 V, ID = 15 A 60 S
Dynamicb
Input Capacitance Ciss
VDS = 15 V, VGS = 0 V, f = 1 MHz
2071
pFOutput Capacitance Coss 406
Reverse Transfer Capacitance Crss 168
Total Gate Charge Qg VDS = 15 V, VGS = 10 V, ID = 10 A 36 54
nC
VDS = 15 V, VGS = 4.5 V, ID = 10 A
16.8 25.5
Gate-Source Charge Qgs 5.1
Gate-Drain Charge Qgd 5.2
Gate Resistance Rgf = 1 MHz 0.2 0.85 1.7 Ω
Tur n - O n D e l ay Time td(on)
VDD = 15 V, RL = 1.5 Ω
ID ≅ 10 A, VGEN = 4.5 V, Rg = 1 Ω
25 45
ns
Rise Time tr 16 30
Turn-Off Delay Time td(off) 28 50
Fall Time tf12 24
Tur n - O n D e l ay Time td(on)
VDD = 15 V, RL = 1.5 Ω
ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω
10 20
Rise Time tr 918
Turn-Off Delay Time td(off) 25 45
Fall Time tf918
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C 5.1 A
Pulse Diode Forward CurrentaISM 70
Body Diode Voltage VSD IS = 3 A 0.73 1.1 V
Body Diode Reverse Recovery Time trr
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C
19 38 ns
Body Diode Reverse Recovery Charge Qrr 10 20 nC
Reverse Recovery Fall Time ta10 ns
Reverse Recovery Rise Time tb9
Document Number: 69069
S-83092-Rev. A, 29-Dec-08
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3
Vishay Siliconix
Si4160DY
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
14
28
42
56
70
0.0 0.5 1.0 1.5 2.0 2.5
VGS =10thru4V
VGS =3V
VDS - Drain-to-Source Voltage (V)
- Drain Current (A)I D
0.0035
0.0040
0.0045
0.0050
0.0055
0.0060
0142842 56 70
VGS =4.5V
VGS =10V
- On-Resistance (Ω)RDS(on)
ID- Drain Current (A)
0
2
4
6
8
10
0816 24 32 40
ID=10A
VDS =10V
VDS =20V
VDS =15V
- Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
VGS
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
2
4
6
8
10
012345
TC= 25 °C
TC= 125 °C TC= - 55 °C
VGS - Gate-to-Source Voltage (V)
- Drain Current (A)I D
Crss
0
560
1120
1680
2240
2800
0 6 12 1824 30
Ciss
Coss
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
- 50 - 25 0 25 50 75 100 125 150
VGS =10V
VGS =4.5V
ID=15A
TJ-Junction Temperature (°C)
(Normalized)
- On-ResistanceRDS(on)
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Document Number: 69069
S-83092-Rev. A, 29-Dec-08
Vishay Siliconix
Si4160DY
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
0.0 0.2 0.4 0.6 0.81.0 1.2
1
0.01
0.001
0.1
10
100
TJ= 25 °C
TJ= 150 °C
VSD -Source-to-Drain Voltage (V)
- Source Current (A)I S
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
- 50 - 25 0 25 50 75 100 125 150
ID= 250 µA
ID=5mA
Variance (V)VGS(th)
TJ- Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
0.000
0.005
0.010
0.015
0.020
012345678910
TJ= 25 °C
TJ= 125 °C
ID=15A
VGS -Gate-to-Source Voltage (V)
- On-Resistance (Ω)RDS(on)
0
34
68
102
136
170
011100.0 0.01 0.1
Time (s)
Power (W)
Safe Operating Area, Junction-to-Ambient
0.01
100
1
100
0.01
0.1
1ms
10 ms
1s
0.1 1 10
10
TA= 25 °C
Single Pulse
Limited byR
DS(on)*
DC
10 s
BVDSS Limited
100 ms
VDS - Drain-to-Source Voltage (V)
*VGS > minimumVGS at which RDS(on) is specified
- Drain Current (A)
ID
Document Number: 69069
S-83092-Rev. A, 29-Dec-08
www.vishay.com
5
Vishay Siliconix
Si4160DY
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
0
6
12
18
24
30
0 255075100125150
TC- Case Temperature (°C)
ID- Drain Current (A)
Power, Junction-to-Foot
0.0
1.4
2.8
4.2
5.6
7.0
0 25 50 75 100 125 150
TC- Case Temperature (°C)
Power (W)
Power, Junction-to-Ambient
0.00
0.36
0.72
1.08
1.44
1.80
0 25 50 75 100 125 150
TA-Ambient Temperature (°C)
Power (W)
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Document Number: 69069
S-83092-Rev. A, 29-Dec-08
Vishay Siliconix
Si4160DY
New Product
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69069.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 110 100010-1
10-4 100
0.2
0.1
Square WavePulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
t1
t2
Notes:
PDM
1. Duty Cycle, D =
2. Per Unit Base = RthJA =85 °C/W
3. TJM -T
A=P
DMZthJA(t)
t1
t2
4. Surface Mounted
Duty Cycle = 0.5
Single Pulse
0.02
0.05
Normalized Thermal Transient Impedance, Junction-to-Foot
10-3 10-2 01110-1
10-4
0.2
0.1
Duty Cycle = 0.5
Square WavePulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
0.05
0.02
Single Pulse
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
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Revision: 12-Mar-12 1Document Number: 91000
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