October 1987
Revised January 1999
CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary
Counter
© 1999 Fairchild Semicond uctor Corpor ation DS005988.prf www.fairchild semi .com
CD40192BC • CD40193BC
Synchronous 4-Bit Up/Down Decade Counter •
Synchronous 4-Bit Up/Down Binary Counter
General Descript ion
The CD40192BC and CD40193BC up/down counters are
monolithic complementary MOS (CMOS) integrated cir-
cuits. The CD40192BC is a BCD counter, while the
CD40193BC is a binary counter.
Counting up and countin g down i s perfor med by two cou nt
inputs, one being held HIGH while the other is clock ed. The
outputs change on the positive-going transition of this
clock.
These counters feature preset inputs that are enabled
when load is a l ogical “0” an d a clear which forces all ou t-
puts to “ 0” w hen it is a t logica l “1 ”. Th e coun ters a lso have
carry and borrow outputs so that they can be cascaded
using no external circuitry.
All inputs are protected against damage due to static dis-
charge by clamps to VDD and VSS.
Features
■Wide supply voltage range: 3V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL co mpatibility: Fan out of 2 dr iving 74L
or 1 driving 74LS
■Carry and bor row ou tpu ts for ea sy expansio n to N - bit by
cascading
■Asynchronous clear
■Equivalent to: MM74C192 and MM74C193
Ordering Code:
Devices also available in Tape an d R eel. Spe c if y by appendin g s uf f ix let t er “X” to the or dering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Cascading Packa ges
Order Number Package Number Package Description
CD40192BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD40193BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD40193BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
www.fairchildsemi.com 2
CD40192BC • CD40193BC
Block Diagrams
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Binary Counter
3 www.fairchildsemi.com
CD40192BC • CD40193BC
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions (No te 2)
Note 1: “Ab solute Ma ximum Rating s” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The “Recommended
Operati ng Condition s” and Ele ctrical C haracteristic s t ables provide c ondi-
tions for actu al devi c e operatio n.
Note 2: VSS = 0V unl es s ot herwise s pecified .
DC Electrical Characteristics (Note 3)
Note 3: AC Paramete rs are guarant eed by DC cor related te sting.
Note 4: IOH and IOL are tes t ed one ou tp ut at a ti m e.
DC Supply Voltage (VDD)−0.5 to +18 VDC
Input Voltage (VIN)−0.5toV
DD +0.5 VDC
Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P D)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering , 10 seconds) 260 °C
DC Supply Voltage (V DD) 3 to 15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)
CD40192BC, CD40193BC −40°C to +85°C
Symbol Paramet er Conditions −40°C +25°C+85°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V, VIN = VDDor VSS 20 20 150 µA
Current VDD = 10V, VIN = VDD or VSS 40 40 300 µA
VDD = 15V, VIN = VDD or V SS 80 80 600 µA
VOL LOW Level VDD = 5V 0.05 0.05 0.05 V
Output Voltage VDD = 10V 0.05 0.05 0.05 V
VDD = 15V 0.05 0.05 0.05 V
VOH HIGH Level VDD = 5V 4.95 4.95 4.95 V
Output Voltage VDD = 10V 9.95 9.95 9.95 V
VDD = 15V 14.95 14.95 14.95 V
VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V
VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA
VDD = 15V, V IN = 15V 0.3 10−5 0.3 1.0 µA
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CD40192BC • CD40193BC
AC Electrical Charac teristics (Note 3)
TA = 25°C, CL = 50 pF, RL = 200 kΩ, input tr = tf = 20 ns, unless otherwise specified.
Note 5: CPD det ermine s the no load AC power c onsumptio n of any CMOS devi ce. For c omplete explan ation, see Family Ch aracteristic s applicat ion note,
AN-90.
Symbol Parameter Conditions Min Typ Max Units
tPHL or tPLH Propagation Delay Time VDD = 5V 250 400 ns
from Count Up or VDD = 10V 100 160 ns
Count Down to Q VDD = 15V 80 130 ns
tPHL or tPLH Propagation Delay Time VDD = 5V 120 200 ns
from Count Up to Carry VDD = 10V 50 80 ns
VDD = 15V 40 65 ns
tPHL or tPLH Propagation Delay Time VDD = 5V 120 200 ns
from Count Down VDD = 10V 50 80 ns
to Borrow VDD = 15V 40 65 ns
tSU Time Prior to Load VDD = 5V 100 160 ns
That Data Must VDD = 10V 30 50 ns
Be Present VDD = 15V 25 40 ns
tPHL Propagation Delay Time VDD = 5V 130 220 ns
from Clear to Q VDD = 10V 60 100 ns
VDD = 15V 50 80 ns
tPLH or tPHL Propagation Delay Time VDD = 5V 300 480 ns
from Load to Q VDD = 10V 120 190 ns
VDD = 15V 95 150 ns
tTLH or tTHL Output Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
fCL Maximum Count Frequency VDD = 5V 2.5 4 MHz
VDD = 10V 6 10 MHz
VDD = 15V 7.5 12.5 MHz
trCL or t fCL Maximum Count Rise VDD = 5V 15 µs
or Fall Time VDD = 10V 5 µs
VDD = 15V 1 µs
tWH, tWL Minimum Count Pulse VDD = 5V 120 200 ns
Width VDD = 10V 35 80 ns
VDD = 15V 28 65 ns
tWH Minimum Clear V DD = 5V 300 480 ns
Pulse Width VDD = 10V 120 190 ns
VDD = 15V 95 150 ns
tWL Minimum Load VDD = 5V 100 160 ns
Pulse Width VDD = 10V 40 65 ns
VDD = 15V 32 55 ns
CIN Average Input Capacitance Load and Data 5 7.5 pF
Inputs (A,B,C,D)
Count Up, Count 10 15 pF
Down and Clear
CPD Power Dissipation Capacity (Note 5) 100 pF
5 www.fairchildsemi.com
CD40192BC • CD40193BC
Timing Diagrams
CD40192BC
Sequence:
1. Clear out puts to zero.
2. Load (p res et) to BC D s even.
3. Count up t o eight, nine, carr y, zero, one an d t wo.
4. Count dow n t o one, zero, borrow, nine, eight an d s even.
CD40193BC
Sequence:
1. Clear out puts to zero.
2. Load (p res et) to binar y thirte en.
3. Count up to fourteen, fifteen, carr y, zero, one and two.
4. Count dow n t o one, zero, borrow, fi fteen, four t een and thirteen.
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CD40192BC • CD40193BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are im plied and Fairchild reserves the right at any time w ithout notice to change said circuitry and specifications.
CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Dow n Binary
Counter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support d evices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A cr itical c ompon ent in any com ponent of a li fe support
device or system whose failure to perform can be rea-
sonably expected to cause th e failure of the li fe suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
