1
FEATURES
0.25µm, five-layer metal, ViaLinkTM epitaxial CMOS
process for smallest die sizes
One-time programmable, ViaLink technology for
personalization
150 MHz 16-bit counters, 150 MHz datapaths, 60+ MHz
FIFOs
2.5V core supply voltage, 3.3V I/O supply voltag e
Up to 320,000 usable system gates (non-volatile)
I/Os
- Interfaces with 3.3 volt
- PCI compliant with 3.3 volt
- Full JTAG 11 49.1 com pliant
- Registered I/O cells with individually controlled enables
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Test Method 1019
- Total-dose: 300 krad(Si)
- SEL Immune: >120MeV-cm2/mg
- LETTH (0.25) MeV-cm2/mg:
>42 logic cell flip flops
>64 for embedded SRAM
- Saturated Cross Section (cm 2) p er bit
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Up to 24 dual-port RadHard SRAM modules, organized in
user-configurable 2,304 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and initialized RAM
functions
100% routable with 100% utilization and 100% user fixed
I/O
Variable-grain logic cells provide high performance an d
100% utilization
Comprehensi ve design tools include high quality Verilog/
VHDL synthesis and simulation
QuickLogic IP available for microcontrollers, DRAM
controllers, USART and PCI
Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, and
484 CLGA,208 PQFP, 280 PBGA, 484 PBGA
Standard Microcircuit Drawing 5962-04229
- QML qualified
INTRODUCTION
The RadHard Eclipse Field Programmable Gate Array Family
(FPGA) offers up to 320,000 usable system gates including
Dual-Port RadHard SRAM modules. It is fabricated on 0.25µm
five-layer metal ViaLink CMOS process and contains a
maximum of 1,536 logic cells and 24 dual-port RadHard SRAM
modules (see Figure 1 Block Diagram). Each RAM module has
2,304 RAM bits, for a maximum total of 55,300 bits. Please
reference product family comparison chart on page 2.
RAM modules are Dual Port (one asynchronous/synchronous
read port, one write port) and can be configured into one of four
modes (see Figure 2). Designers can cascade multiple RAM
modules to increase the depth or width allowed in single
modules by connecting corresponding address lines together and
dividing the words between modules (see Figure 3). This
approach allows a variety of address dept hs and word widths t o
be tailored to a specific application.
The RadHard Eclipse FPGA is available in a 208-pin Cerquad
Flatpack, allowing access to 99 bidirectional signal I/O, 1
dedicated clock, 8 programmable clocks and 16 high drive
inputs. Other package options include a 288 CQFP, 484 CCGA
and a 484 CLGA.
Aeroflex uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology. QuickLogic is a
pioneer in the FPGA semiconductor and software tools field.
Standard Products
RadHard Eclipse FPGA Family (6250 and 6325)
Data Sheet
August 22, 2006
www.aeroflex.com/RadHardFPGA
2
Product Family Comparison
The RadHard Eclipse Field Programmable Gate Array Family consists of the UT6250 and UT6325. The similarities and differences
are summarized in the chart below
.
Features
Device System
Gates Logic
Cells Maximum
Flip Flops Logic
Cell Flip
Flops
RAM
Modules RAM
Bits I/O Standards Clocks High
Drive
Inputs
UT6325 320,640 1,536 3,692 3072 24 55,300 LVTTL,
LVCMOS3, PCI 916
UT6250 248,160 960 2,670 1920 20 46,100 LVTTL,
LVCMOS3, PCI 916
Radiation
Device RadHard
Total Dose LETTH (0.25) MeV-cm2/mg Saturated Cross Section Latch-up
Immune
UT6325 3E5 >42 logic cell flip flops
>64 embedded SRAM 5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
>120
UT6250 3E5 >42 logic cell flip flops
>64 embedded SRAM 5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
>120
Packages
Device 208 PQFP 208 CQFP 280PBGA 288 CQFP 484 PBGA 484 CLGA 484 CCGA
UT6235 99 99 163 163 310 310 310
UT6250 99 99 163 163 250 250 250
3
CONTACT FACTORY
Figure 1. RadHard Eclipse FPGA Block Diagram
Bidirectional I//O and
High-Drive Inputs
Maximum
of
1,536
High
Speed
Variable
Grain
Logic
Cells
IP
Maximum
of
24
RadHard
SRAM
Blocks
Fabric
Embedded RAM Blocks
Embedded RAM Blocks
4
Software support for the product is available from QuickLogic.
The turnkey QuickWorksTM package provides the most com-
plete software solution from design entry to logic synthesis,
place and route, simulation, static timing, and power analysis.
The QuickToolsTM for Workstations package provides a solu-
tion for designers who use Cadence, Exemplar, Mentor, Synop-
sys, Synplicity, Viewlogic, Veribest or other third-party tools
for design entry, synthesis, simulation. Please visit Quick Log-
ic’s website at www.quicklogic.com for more information.
The variable gr ai n lo gi c cell features up to 17 simultaneous in-
puts and 6 outputs within a cell that can be fragmented into 6
independent sections. Each cell has a fan-in of 30 including
register and control lines (see Figure 5).
PRODUCT DESCRIPTION
I/O Pins
• Up to 310 bi-directional input/output pins, PCI-compliant for
3.3V buses (see Table 4)
• Each bidirectional I/O contains RadHard flip-flops for inpu t,
output, and output enable lines
Distributed Networks
• One, dedicated clock network, hardwired to each logic cell
flip-flop clock pin to minimize skew
• Eight programmable clock networks, accessible from clock
pins or internal logic
• 20 pre-defined Quad-clock networds, five per quadrant. Ac-
cessed by the 8 programmable global clock networks
• Sixteen high drive inputs. Two inputs located in each of the
eight I/O banks. Used as clock or enable signals for the I/O
RadHard flip-flops, or as high drive inputs for internal logi c
Performance
• Input + logic cell + output total delay s un der 12 ns
• Data path speeds over 200 MHz
• Counter speeds over 150 MHz
• FIFO speeds over 60+ MHz
WA
WD
WE
WCLK
RE
RCLK
RA
RD
ASYNCRD
Figure 2. RadHard Eclipse FPGA RAM
RDATA
WDATA RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
WDATA
WADDR
RDATA
Figur e 3. RadHard Ecli pse FPGA Module Bit s
WADDR RADDR
(9:0)
(17:0)
(9:0)
(17:0)
MODE
(1:0)
5
CONTACT FACTORY
QED
R
Figure 4. RadHard Eclipse FPGA I/O Cell
INPUT
REGISTER
D
Q
R
D
EQ
R
OUTPUT
REGISTER
OUTPUT
ENABLE
REGISTER
PAD
-
+
6
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
PS
DCLK
AZ
OZ
QZ
FZ
NZ
Figure 5. RadHard Eclipse FPGA Logic Cell
Q2Z
PP
QC
CLKSEL
QR
GRST
DQ
DQ
R
S
R
S
7
Table 1: 208-pin Ceramic Quad Flatpack Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function
1GND 36 IO(B) 71 IO(C) 106 GND 141 IO(F) 176 IO(G)
2GND 37 IO(B) 72 V
CCIO
(C) 107 IO(E) 142 IO(F) 177 V
CCIO
(G)
3GND 38 IO(B) 73 IO(C) 108 GND 143 IO(F) 178 GND
4GND 39 IOCTRL(B) 74 IO(C) 109 IO(E) 144 IOCTRL(F) 179 IO(G)
5IO(A) 40 INREF(B) 75 GND 110 IO(E) 145 INREF(F) 180 IO(G)
6IO(A) 41 IOCTRL(B) 76 V
CC
111 V
CCIO
(E) 146 V
CC
181 IO(G)
7IO(A) 42 IO(B) 77 IO(C) 112 IO(E) 147 IOCTRL(F) 182 V
CC
8V
CCIO
(A) 43 IO(B) 78 TRSTB 113 V
CC
148 IO(F) 183 TCK
9IO(A) 44 V
CCIO
(B) 79 VCC 114 IO(E) 149 IO(F) 184 V
CC
10 IO(A) 45 IO(B) 80 IO(D) 115 IO(E) 150 V
CCIO
(F) 185 IO(H)
11 IOCTRL(A) 46 V
CC
81 IO(D) 116 IO(E) 151 IO(F) 186 IO(H)
12 V
CC
47 IO(B) 82 IO(D) 117 IOCTRL(E) 152 IO(F) 187 IO(H)
13 INREF(A) 48 IO(B) 83 GND 118 INREF(E) 153 GND 188 GND
14 IOCTRL(A) 49 GND 84 V
CCIO
(D) 119 IOCTRL(E) 154 IO(F) 189 V
CCIO
(H)
15 IO(A) 50 TDO 85 IO(D) 120 IO(E) 155 NU 190 IO(H)
16 IO(A) 51 NU 86 V
CC
121 IO(E) 156 GND 191 IO(H)
17 IO(A) 52 GND 87 IO(D) 122 V
CCIO
(E) 157 GND 192 IOCTRL(H)
18 IO(A) 53 GND 88 IO(D) 123 GND 158 GND 193 IO(H)
19 V
CCIO
(A) 54 GND 89 V
CC
124 IO(E) 159 GND 194 INREF(H)
20 IO(A) 55 GND 90 IO(D) 125 IO(E) 160 GND 195 V
CC
21 GND 56 V
CC
91 IO(D) 126 IO(E) 161 IO(G) 196 IOCTRL(H)
22 IO(A) 57 IO(C) 92 IOCTRL(D) 127 CLK(5) 162 V
CCIO
(G) 197 IO(H)
23 TDI 58 GND 93 INREF(D) 128 CLK(6) 163 IO(G) 198 IO(H)
24 CLK(0) 59 IO(C) 94 IOCTRL(D) 129 V
CC
164 IO(G) 199 IO(H)
25 CLK(1) 60 V
CCIO
(C) 95 IO(D) 130 CLK(7) 165 V
CC
200 IO(H)
26 V
CC
61 IO(C) 96 IO(D) 131 V
CC
166 IO(G) 201 IO(H)
27 CLK(2) 62 IO(C) 97 IO(D) 132 CLK(8) 167 IO(G) 202 IO(H)
28 CLK(3) 63 IO(C) 98 V
CCIO
(D) 133 TMS 168 IO(G) 203 V
CCIO
(H)
29 V
CC
64 IO(C) 99 IO(D) 134 IO(F) 169 IOCTRL(G) 204 GND
30 CLK(4),
DEDCLK 65 IO(C) 100 IO(D) 135 IO(F) 170 INREF(G) 205 IO(H)
31 IO(B) 66 IO(C) 101 GND 136 IO(F) 171 IOCTRL(G) 206 NU
32 IO(B) 67 IOCTRL(C) 102 NU 137 GND 172 IO(G) 207 GND
33 GND 68 INREF(C) 103 GND 138 V
CCIO
(F) 173 IO(G) 208
GND
34 V
CCIO
(B) 69 IOCTRL(C) 104 GND 139 IO(F) 174 IO(G)
35 IO(B) 70 IO(C) 105 GND 140 IO(F) 175 V
CC
8
Table 2: 288-pin Ceramic Quad Flatpack Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function
1GND 36 CLK(7) 71 V
CC
106 IO(G) 141 GND 176 IO(A)
2V
CC
37 CLK(8) 72 GND 107 TCK 142 GND 177 TDI
3GND 38 TMS 73 GND 108 V
CC
143 V
CC
178 CLK(0)
4GND 39 IO(F) 74 V
CC
109 IO(H) 144 GND 179 CLK(1)
5IO(E) 40 IO(F) 75 GND 110 IO(H) 145 GND 180 CLK(2)
6IO(E) 41 IO(F) 76 GND 111 IO(H) 146 V
CC
181 CLK(3)
7IO(E) 42 IO(F) 77 IO(F) 112 IO(H) 147 GND 182 CLK(4),
DEDClK
8IO(E) 43 V
CC
78 IO(F) 113 IO(H) 148 IO(A) 183 IO(B)
9IO(E) 44 GND 79 IO(F) 114 IO(H) 149 IO(A) 184 IO(B)
10 IO(E) 45 V
CCIO
(F) 80 IO(G) 115 V
CC
150 IO(A) 185 IO(B)
11 IO(E) 46 IO(F) 81 IO(G) 116 GND 151 IO(A) 186 IO(B)
12 IO(E) 47 IO(F) 82 IO(G) 117 V
CCIO
(H) 152 IO(A) 187 V
CC
13 IO(E) 48 IO(F) 83 IO(G) 118 IO(H) 153 IO(A) 188 GND
14 V
CC
49 IO(F) 84 IO(G) 119 IO(H) 154 IO(A) 189 V
CCIO
(B)
15 GND 50 IO(F) 85 IO(G) 120 IO(H) 155 IO(A) 190 IO(B)
16 V
CCIO
(E) 51 IO(F) 86 V
CC
121 IOCTRL(H) 156 IOCTRL(A) 191 IO(B)
17 IOCTRL(E) 52 INREF(F) 87 GND 122 IO(H) 157 INREF(A) 192 IO(B)
18 INREF(E) 53 IOCTRL(F) 88 V
CCIO
(G) 123 INREF(H) 158 V
CC
193 IO(B)
19 IOCTRL(E) 54 IOCTRL(F) 89 IO(G) 124 IOCTRL(H) 159 GND 194 IO(B)
20 IO(E) 55 IO(F) 90 IOCTRL(G) 125 IO(H) 160 V
CCIO
(A) 195 IOCTRL(B)
21 IO(E) 56 IO(F) 91 INREF(G) 126 IO(H) 161 IOCTRL(A) 196 INREF(B)
22 IO(E) 57 V
CCIO
(F) 92 IOCTRL(G) 127 IO(H) 162 IO(A) 197 IOCTRL(B)
23 IO(E) 58 GND 93 IO(G) 128 IO(H) 163 IO(A) 198 IO(B)
24 IO(E) 59 V
CC
94 IO(G) 129 V
CCIO
(H) 164 IO(A) 199 IO(B)
25 IO(E) 60 IO(F) 95 IO(G) 130 GND 165 IO(A) 200 IO(B)
26 IO(E) 61 IO(F) 96 IO(G) 131 V
CC
166 IO(A) 201 V
CCIO
(B)
27 IO(E) 62 IO(F) 97 IO(G) 132 IO(H) 167 IO(A) 202 GND
28 V
CCIO
(E) 63 IO(F) 98 IO(G) 133 IO(H) 168 IO(A) 203 V
CC
29 GND 64 IO(F) 99 IO(G) 134 IO(H) 169 IO(A) 204 IO(B)
30 V
CC
65 IO(F) 100 V
CCIO
(G) 135 IO(A) 170 IO(A) 205 IO(B)
31 IO(E) 66 IO(F) 101 GND 136 IO(A) 171 IO(A) 206 IO(B)
32 IO(E) 67 IO(F) 102 V
CC
137 IO(A) 172 V
CCIO
(A) 207 IO(B)
33 IO(E) 68 NU 103 IO(G) 138 NU 173 GND 208 IO(B)
34 CLK(5) 69 GND 104 IO(G) 139 GND 174 V
CC
209 IO(B)
35 CLK(6) 70 GND 105 IO(G) 140 GND 175 IO(A) 210 IO(B)
9
Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function
211 TDO 224 IO(B) 237 IOCTRL(C) 250 IO(C) 263 IO(D) 276 IO(D)
212 NU 225 IO(C) 238 INREF(C) 251 IO(C) 264 IO(D) 277 IO(D)
213 GND 226 IO(C) 239 IOCTRL(C) 252 TRSTB 265 IO(D) 278 IO(D)
214 IO(B) 227 IO(C) 240 IO(C) 253 V
CC
266 IO(D) 279 IO(D)
215 V
CC
228 IO(C) 241 IO(C) 254 IO(D) 267 IO(D) 280 IO(D)
216 GND 229 IO(C) 242 IO(C) 255 IO(D) 268 IO(D) 281 IO(E)
217 GND 230 V
CC
243 IO(C) 256 IO(D) 269 IO(D) 282 IO(E)
218 V
CC
231 GND 244 V
CCIO
(C) 257 IO(D) 270 IOCTRL(D) 283 IO(E)
219 GND 232 V
CCIO
(C) 245 GND 258 IO(D) 271 INREF(D) 284 NU
220 GND 233 IO(C) 246 V
CC
259 V
CC
272 IOCTRL(D) 285 GND
221 GND 234 IO(C) 247 IO(C) 260 GND 273 V
CCIO
(D) 286 GND
222 IO(B) 235 IO(C) 248 IO(C) 261 V
CCIO
(D) 274 GND 287 V
CC
223 IO(B) 236 IO(C) 249 IO(C) 262 IO(D) 275 V
CC
288 GND
10
Table 3: 484-pin Ceramic Land Grid Array and Plastic Ball Grid Array Pinout Table
Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function
A1 IO(A) AA14 IO(D) B5 IO(A) C18 IO(G) E9 IO(H) F22 IOCTRL(F)
A2 GND AA15 IO(D) B6 IO(H) C19 IO(F) E10 IO(H) G1 IO(A)
A3 IO(A) AA16 IO(D) B7 IO(H) C20 GND E11 V
CC
G2 IO(A)
A4 IO(A) AA17 IO(D) B8 INREF(H) C21 IO(F) E12 IO(G) G3 IO(A)
A5 IO(A) AA18 IO(D) B9 IO(H) C22 IO(F) E13 IO(G) G4 IO(A)
A6 IO(H) AA19 IO(E) B10 IO(H) D1 IO(A) E14 IO(G) G5 IO(A)
A7 IO(H) AA20 GND B11 IO(H) D2 IO(A) E15 IOCTRL(G) G6 IO(A)
A8 IOCTRL(H) AA21 IO(E) B12 NC D3 IO(A) E16 IO(G) G7 GND
A9 IO(H) AA22 IO(E) B13 NC D4 IO(A) E17 INREF(G) G8 IO(H)
A10 NC AB1 IO(B) B14 NC D5 IO(A) E18 IO(G) G9 IO(H)
A11 NC AB2 GND B15 IO(G) D6 IO(H) E19 IO(F) G10 IO(H)
A12 TCK AB3 GND B16 IO(G) D7 IO(H) E20 IO(F) G11 IO(G)
A13 IO(G) AB4 IO(B) B17 IO(G) D8 IO(H) E21 IO(F) G12 GND
A14 IO(G) AB5 IO(B) B18 IO(G) D9 IO(H) E22 IO(F) G13 IO(G)
A15 IO(G) AB6 IO(C) B19 GND D10 IO(H) F1 IO(A) G14 IO(G)
A16 IO(G) AB7 IO(C) B20 IO(F) D11 IO(H) F2 INREF(A) G15 IO(G)
A17 IO(G) AB8 IOCTRL(C) B21 IO(F) D12 IO(G) F3 IO(A) G16 GND
A18 IO(G) AB9 IO(C) B22 IO(F) D13 IO(G) F4 IO(A) G17 V
CCIO
(F)
A19 IO(F) AB10 IO(C) C1 IO(A) D14 IO(G) F5 IO(A) G18 IO(F)
A20 GND AB11 IO(C) C2 IO(A) D15 IOCTRL(G) F6 V
CCIO
(A) G19 IO(F)
A21 NU AB12 IO(D) C3 GND D16 IO(G) F7 V
CCIO
(H) G20 IO(F)
A22 IO(F) AB13 IO(D) C4 NU D17 IO(G) F8 IO(H) G21 INREF(F)
AA1 TDO AB14 IO(D) C5 IO(A) D18 IO(F) F9 V
CCIO
(H) G22 IO(F)
AA2 NU AB15 IO(D) C6 IO(H) D19 GND F10 IO(H) H1 IO(A)
AA3 GND AB16 IOCTRL(D) C7 IO(H) D20 IO(F) F11 V
CCIO
(H) H2 IO(A)
AA4 IO(B) AB17 IO(D) C8 IO(H) D21 IO(F) F12 V
CCIO
(G) H3 IO(A)
AA5 IO(C) AB18 IO(D) C9 IOCTRL(H) D22 IO(F) F13 IO(G) H4 IO(A)
AA6 IO(C) AB19 IO(E) C10 IO(H) E1 IOCTRL(A) F14 V
CCIO
(G) H5 IOCTRL(A)
AA7 IO(C) AB20 GND C11 IO(H) E2 IO(A) F15 NC H6 V
CCIO
(A)
AA8 INREF(C) AB21 GND C12 IO(H) E3 IO(A) F16 V
CCIO
(G) H7 IO(H)
AA9 IO(C) AB22 IO(E) C13 IO(G) E4 IO(A) F17 NC H8 GND
AA10 IO(C) B1 IO(A) C14 IO(G) E5 IO(A) F18 IO(F) H9 V
CC
AA11 IO(C) B2 GND C15 IO(G) E6 IO(H) F19 IO(F) H10 V
CC
AA12 IO(D) B3 GND C16 IO(G) E7 N/C F20 IOCTRL(F) H11 V
CC
AA13 IO(D) B4 GND C17 IO(G) E8 IO(H) F21 IO(F) H12 GND
11
PinFunctionPinFunctionPinFunction Pin Function Pin Function Pin Function
H13 V
CC
K4 IO(A) L17 V
CCIO
(F) N8 V
CC
P21 IO(E) T12 NC
H14 V
CC
K5 IO(A) L18 IO(F) N9 V
CC
P22 IO(E) T13 IO(D)
H15 GND K6 V
CCIO
(A) L19 CLK(8) N10 GND R1 IO(B) T14 NC
H16 IO(F) K7 IO(A) L20 IO(F) N11 GND R2 INREF(B) T15 IO(D)
H17 IO(F) K8 V
CC
L21 IO(F) N12 GND R3 IO(B) T16 GND
H18 IO(F) K9 V
CC
L22 IO(F) N13 GND R4 IO(B) T17 IO(E)
H19 IO(F) K10 GND M1 IO(B) N14 V
CC
R5 IO(B) T18 IO(E)
H20 IO(F) K11 GND M2 IO(B) N15 V
CC
R6 IO(B) T19 IO(E)
H21 IO(F) K12 GND M3 IO(B) N16 IO(E) R7 IO(B) T20 IO(E)
H22 IO(F) K13 GND M4 CLK(3) N17 V
CCIO
(E) R8 GND T21 IOCTRL(E)
J1 IO(A) K14 V
CC
M5 IO(B) N18 IO(E) R9 V
CC
T22 IO(E)
J2 IO(A) K15 V
CC
M6 V
CCIO
(B) N19 IO(E) R10 V
CC
U1 IOCTRL(B)
J3 IO(A) K16 IO(F) M7 CLK(1) N20 IO(E) R11 GND U2 IO(B)
J4 IO(A) K17 IO(F) M8 V
CC
N21 IO(E) R12 V
CC
U3 IOCTRL(B)
J5 IO(A) K18 IO(F) M9 V
CC
N22 IO(E) R13 V
CC
U4 IO(B)
J6 IO(A) K19 IO(F) M10 GND P1 IO(B) R14 V
CC
U5 IO(B)
J7 IO(A) K20 IO(F) M11 GND P2 IO(B) R15 GND U6 IO(C)
J8 V
CC
K21 IO(F) M12 GND P3 IO(B) R16 IO(D) U7 V
CCIO
(C)
J9 GND K22 IO(F) M13 GND P4 IO(B) R17 V
CCIO
(E) U8 NC
J10 V
CC
L1 CLK(4),
DEDCLK M14 GND P5 IO(B) R18 IO(E) U9 V
CCIO
(C)
J11 V
CC
L2 CLK(0) M15 GND P6 V
CCIO
(B) R19 IO(E) U10 IO(C)
J12 GND L3 CLK(2) M16 GND P7 IO(B) R20 IO(E) U11 V
CCIO
(C)
J13 V
CC
L4 IO(A) M17 IO(E) P8 V
CC
R21 IO(E) U12 V
CCIO
(D)
J14 GND L5 IO(A) M18 IO(E) P9 GND R22 IO(E) U13 IO(D)
J15 V
CC
L6 IO(A) M19 IO(E) P10 V
CC
T1 IO(B) U14 V
CCIO
(D)
J16 IO(F) L7 GND M20 CLK(7) P11 GND T2 IO(B) U15 NC
J17 V
CCIO
(F) L8 GND M21 CLK(5) P12 V
CC
T3 IO(B) U16 V
CCIO
(D)
J18 IO(F) L9 GND M22 TMS P13 V
CC
T4 IO(B) U17 V
CCIO
(E)
J19 IO(F) L10 GND N1 IO(B) P14 GND T5 IO(B) U18 IO(E)
J20 IO(F) L11 GND N2 IO(B) P15 V
CC
T6 V
CCIO
(B) U19 IO(E)
J21 IO(F) L12 GND N3 IO(B) P16 IO(E) T7 GND U20 IOCTRL(E)
J22 IO(F) L13 GND N4 IO(B) P17 IO(E) T8 IO(C) U21 IO(E)
K1 TDI L14 V
CC
N5 IO(B) P18 IO(E) T9 N/C U22 INREF(E)
K2 IO(A) L15 V
CC
N6 IO(B) P19 IO(E) T10 TRSTB V1 IO(B)
K3 IO(A) L16 CLK(6) N7 IO(B) P20 IO(E) T11 GND V2 IO(B)
12
Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function
V3 IO(B) V14 IO(D) W3 IO(B) W14 IO(D) Y3 GND Y14 IO(D)
V4 IO(B) V15 IO(D) W4 IO(B) W15 IO(D) Y4 IO(C) Y15 IOCTRL(D)
V5 IO(B) V16 INREF(D) W5 IO(B) W16 NC Y5 IO(C) Y16 IO(D)
V6 IO(C) V17 IO(D) W6 IO(C) W17 IO(D) Y6 IO(C) Y17 IO(D)
V7 IO(C) V18 IO(E) W7 NC W18 IO(E) Y7 IO(C) Y18 IO(E)
V8 IO(C) V19 IO(E) W8 IO(C) W19 IO(E) Y8 IOCTRL(C) Y19 NU
V9 NC V20 IO(E) W9 IO(C) W20 IO(E) Y9 IO(C) Y20 GND
V10 IO(C) V21 IO(E) W10 IO(C) W21 IO(E) Y10 IO(C) Y21 IO(E)
V11 IO(C) V22 IO(E) W11 IO(C) W22 IO(E) Y11 IO(D) Y22 IO(E)
V12 V
CC
W1 IO(B) W12 IO(D) Y1 IO(B) Y12 IO(D)
V13 NC W2 IO(B) W13 IO(D) Y2 IO(B) Y13 IO(D)
13
Table 4: RadHard Eclipse Pin Description
PIN FUNCTION DESCRIPTION
TDI/RSI Test data in for JTAG/RAM
initialization Serial Data In Hold HIGH during normal operation.
Connects to serial PROM data in for RAM
initialization. Connect to VCC if unused.
TRSTB/RRO Active low reset for JTAG/
RAM initialization reset out Hold LOW during normal operation.
Connects to serial PROM reset for RAM
initialization. Connect to GND if unused.
TMS Test mode select for JTAG Hold HIGH during normal operation.
Connect to VCC if not used for JTAG.
TCK Test clock for JTAG Hold HIGH or LOW during normal
operation. Connect to VCC or ground if not
used for JTAG.
TDO/RCO Test data out for JTAG/RAM
initialization clock out Connect to serial PROM clock for RAM
initialization. Must be left unconnected if not
used for JTAG or RAM initialization.
STM Special Test Mode Must be grounded during normal operation.
I/ACLK High-drive input and/or array
network driver Can be configured as either or both.
I/GCLK High-drive input and/or global
network driver Can be configured as either or both
I High-drive input Use for input signals with high fan out
I/O Input/Output pin Can be configured as an input and/or output
VCC Power supply pin Connect to 2.5V supply
VCCIO Input voltage tolerance pin Connect to 3.3V supply
GND Ground pin Connect to ground
14
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Test per MIL-STD-883; Method 1012.
RECOMMENDED OPERATING CONDITIONS
Notes:
1. T o conclude best and worst case delays, multiply the RadHard K factor from the operating conditions with the delay values defined in the following AC delay tables.
SYMBOL PARAMETER LIMITS
VCC Core supply voltage -0.5 to 3.6V
VCCIO I/O supply voltage -0.5 to 4.6V
INREF I/O reference voltage 2.7V
VIO Voltage on any pin -0.5V to VCCIO +0.5V
ILU Electrical Latchup Immunity +/-100mA
PDPower Dissipation .5 - 2.5W
ΘJC Thermal resistance, junction-to-case25oC/W
TJMaximum junction temperature2+150°C
ESDS ESD pad protection +/-2000V
II DC input current
±
20 mA
TLS Lead Temperature 300°C
SYMBOL PARAMETER LIMITS
VCC Core supply voltage 2.3 to 2.7V
VCCIO I/O Input Tolerance Voltage 3.0 to 3.6V
TA Ambient Temperature -55°C to +12 5°C
K1Delay factor for RadHard FPGA 0.42 to 2.3
15
DC ELECTRICAL CHARACTERISTICS (Pre/Post-
Radiation)* (-55°C to +125°C) (VCC = 2.5V + 10%)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Capacitance is sample tested for initial qualification or design changes only. Clock pins are 12pF maximum.
2. Input only or I/O. Duration should not exceed 30 seconds.
Notes:
1. The data provided in Table 5 are JEDEC and PCI specifications. See preceding AC Delay Data for information specific to RadHard Eclipse FPGA I/Os.
Notes:
1. Excludes input only signals such as DEDCLK. PROGCLK and IOCTRL.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
IIN Input or I/O leakage current VIN = VCCIO or Gnd -10 10 µA
IOZ Three-state output leakage current VIN= VCCIO or Gnd -10 10 µA
CI1Input capacitance -- - 8 pF
CI/O1Bi-directional capacitance -- - 12 pF
IOS2Short-circuit output current VO = GND
VO = VCCIO
-15
40 -180
210 mA
mA
ICC Quiescent current VIN, VO = VCCIO or GND .50 5 mA
IREF DC supply current on INREF -10 10 µA
IPD Pad Pull-down (programmable) V CCIO = 3.6V - 150 µA
Table 5: DC Input and Output Levels
INREF
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V
MIN
V
MAX
V
MIN
V
MAX
V
MIN
V
MAX
V
MAX
V
MIN
mA mA
LVTTL n/a n/a -0.3 0.8 2.0 VCCIO + 0.3 0.4 2.4 2.0 -2.0
LVCMOS3 n/a n/a -0.3 0.7 1.7 VCCIO + 0.3 0.7 1.7 2.0 -2.0
PCI n/a n/a -0.3 0.3 x VCCIO 0.5 x VCCIO VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5
Table 6: Max Bidirectional I/O per Device/Package Combination
Device 208 CQFP 288 CQFP 484 CCGA
RadHard Eclipse FPGA 6250 99 163 250
RadHard Eclipse FPGA 6325 99 163 310
16
AC CHARACTERISTICS LOGIC CELLS (Pre/Post-Radiation)*
(VCC = 2.5V, TA = 25oC, K=1.00)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Stated timing for typical case propagation delay over process variation at V
CC
=2.5V and TA=25
o
C. Multiply by the appropriate delay factor, K, for voltage and
temperature settings as specified in operating range.
2. These limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. W orst case delay values for specific
paths should be determined from timing analysis of your particular design.
SYMBOL PARAMETER Value (ns)
Min Max
TPD Combinatorial Delay of the longest path: time taken by the
combinatorial circui t to output 0.205 1.01
TSU Setup Time: time the synchronous input of the flip flop must be
stable before the active clock edge 0.231 --
THL Hold Time: time the synchronous input of the flip flop must be stable
after the active clock edge 0--
TCO Clock to Out Delay: the amo unt of tim e taken by the flip flop to
output after the active clock edge -0.43
TCWHI Clock High Time: required minimum time the clock stays high 0.46 --
TCWLO Clock Low Time: required minimum that the clock stays low 0.46 --
TSET Set Delay: time between when the flip flop is "set" (high) and when
the output is consequently "set" (high) -- 0.59
TRESET Reset Delay: time betw een when the flip flop is "reset" (low) and
when the output is consequently "reset" (low) -- 0.66
TSW Set Width: time that the SET signal remains high/low 0.3 --
TRW Reset Width: time that the RESET signal remains high/low 0.3
17
SET
D
CLK
Q
Figure 6: Logic Cell Flip Flop
RESET
CLK
SET
RESET
t
CWHI
(MIN) t
CWLO
(MIN)
tRW
tRESET
tSW
tSET
Figure 7: Logic Cell Flip Flop Timi ngs - First Waveform
CLK
D
D
tSU tHL
tCO
Figure 8: Logic Cell Flip Flop Timings - Second Waveform
Q
18
GLOBAL CLOCK TREE DELAY
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL PARAMETER Value (ns)
Min Max
tPGCK Global clock pin delay to quad net 0.990 1.386
tBGCK Global clock buffer delay (quad net to flip flop) 0.534 1.865
Figure 9: Globa l Clock Structure
Quad Net
Programmable Clock
External Clock
Clock
Select
tBGCK
tPGCK
Global Clock Buffer
Figure 10: Global Clock Structure Schematic
Global Clock
19
RAM CELL SYNCHRONOUS and ASYNCHRONOUS READ TIMING
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL PARAMETER Value (ns)
RAM Cell Synchronous Read Timing Min Max
tSRA RA setup time to RCLK: time the READ ADDRESS must be stable
before the active edge of the READ CLOCK 0.686 --
tHRA RA hold time to RCLK: time the READ ADDRESS must be stable
after the active edge of the READ CLOCK 0--
tSRE RE setup time to RCLK: time the READ ENABLE must be stable
before the active edge of the READ CLOCK 0.243 --
tHRE RE hold time to RCLK: time the READ ENABLE must be stable
after the active edge of the READ CLOCK 0--
tRCRD RCLK to RD: time betw een th e active READ CLOCK edge and
the time when the data is delivered to RD -- 2.3
RAM Cell Asynchronous Read Timing
tPDRD RA to RD: time between when the READ ADDRESS is input and
when the DATA is output -- 2.4
RCLK
RA
tSRA tHRA
RE
tSRE tHRE
RD
tRCRD
tPDRD
Figure 11: RAM Cell Synchronous and Asynchronous Read Timing
RCLK
new dataold data
20
RAM CELL SYNCHRONOUS WRITE TIMING
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL PARAMETER Value (ns)
Min Max
tSWA WA setup time to WCLK: time the WRITE ADDRESS must be
stable before the active edge of the WRITE CLOCK 0.675 --
tHWA WA hold time to WCLK: time the WRITE ADDRESS must be
stable after the active edge of the WRITE CLOCK 0--
tSWD WD setup time to WCLK: time the WRITE DATA must be stable
before the active edge of the WRITE CLOCK 0.654 --
tHWD WD hold time to WCLK: time the WRITE DATA must be stabl e
after the active edge of the WRITE CLOCK 0--
tSWE WE setup time to WCLK: time the WRITE ENABLE must be stable
before the active edge of the WRITE CLOCK 0.276
tHWE WE hold time to WCLK: time the WRITE ENABLE must be stable
after the active edge of the WRITE CLOCK 0
tWCRD WCLK to RD (W A = RA): time between the active WRITE CLOCK
edge and the time when the data is available at RD -- 2.8
WCLK
WA
WD
WE
RD
tHWA
tSWA
tSWD tHWD
tSWE tHWE
tWCRD
new dataold data
Figure 12: RAM Cell Synchronous Write Timing
21
QED
R
Figur e 13 . Input Register Cell
PAD
tICLK
tISU
tSID
tIN - tINI
-
+
22
INPUT REGISTER CELL
(VCC = 2.5V, TA = 25oC, K=1.00)
STANDARD INPUT DELAYS
(VCC = 2.5V, TA = 25oC, K=1.00)
SYMBOL PARAMETER Value (ns)
Min Max
tISU Input register setup time: time the synchronous input of the pin must
be stable before the active clock edge 3.308 3.526
tIHL Input register hold time: time the synchronous input of the flip-flop
must be stable after the active clock edge 0--
tICO Input register clock to out: time taken by the flip-flop to output after
the active clock edge -- 0.494
tIRST Input register reset delay: time between when the flip-flop is "reset"
(low) and when the output is consequently "reset" (low) -- 0.464
tIESU Input register clock enable setup time: time "enable" must be stable
before the active clock edge 0.830 -
tIEH Input register clock enable hold time: time "enable" must be stable
after the active clock edge 0--
SYMBOL PARAMETER Value (ns)
Min Max
tSID (LVTTL) LVTTL input delay: Low voltage TTL for 3.3V applications - 0.34
tSID (LVCMOS3) LVCMOS2 input delay: Low voltage CMOS for 3.3V applications - 0.42
R
CLK
D
Q
E
tISU tIHL
tICO
tIRST
tIESU tIEH Figur e 14. Input Register Timing
23
Figure 15. Output Register Cell
PAD
Q
D
24
OUTPUT REGISTER CELL
(VCC = 2.5V, TA = 25oC, K=1.00)
OUTPUT SLEW RATES
(VCC = 2.5V, TA = 25oC, K=1.00, VCCIO = 3.3V)
SYMBOL PARAMETER Value (ns)
Min Max
tOUTLH Output Delay low to high (90% of H) - 2.59
tOUTHL Output Delay high to low (10% of L) - 2.16
tPZH Output Delay tri-state to high (9 0% of H) - 3.06
tPZL Output Delay tri-state to low (10% of L) -- 2.71
tPHZ Output Delay high to tri-state -- 3.44
tPLZ Output Delay low to tr i- state -- 3.32
tCOP Clock to out delay (does not include clock tree delays) -- 2.67 (fast skew)
9.0 (slow skew)
Fast Slew Slow Slew
Rising Edge 2.8V/ ns 1.0V/ns
Falling Edge 2.86V/ns 1.0V/ns
tPHZ
tPZL
tOUTHL
tOUTHL
tPZH
tPLZ
H
L
H
Z
L
H
Z
L
H
L
H
Z
L
H
Z
L
Figure 16. Output Register Cell Timing
25
Power vs Operating Frequency
The basic power equation which best models power consum ption is shown below.
PTOTAL = 0.350 + f(0.0031 NLC + 0.0948 NCKBF +0.01 NCLBF + 0.0263 NCKLD + 0.543 N RAM + 0.0035 NINP + 0.0257 NOUTP)
(mW)
Where
• NLC is the total number of logic cells in the design
• NCKBF = # of clock buffers
• NCLBF = # of column clock buffers
• NCKLD = # of loads connected to the column clock buffers
• NRAM = # of RAM blocks
• NINP is the number of input pins
• NOUTP is the number of output pins
Figure 17 exhibits the power consumption in the device. The chip was filled with (300) 8-bit counters, approximately 76% logic cell
utilization.
2.5
2
1.5
1
.5
0
0 20 40 60 80 100 120 140
Power vs Frequency (Counter_300)
Frequency (Mhz)
Figure 17: Power Consumption
Power (W)
26
Power-Up Sequencing
Notes:
1. VCC and VCCIO should either be ramped simultaneously to their final values (as shown) or with the core voltage VCC leading the
I/O voltage VCCIO.
2. Rise time for the voltage supplies (tRVCC) must be within the range of 1µs < tRVCC <200ms.
3. Voltage power up/power down ramps for the supplies must be mon otonically increasing/decreasing.
4. The starting point for power up (VCCOFFSET) m ust be less than or equal to 300mV.
5. Users must allow time for the asynch ron ous power on reset to complete initializatio n of the dev ice (tPOR). For fast rise times,
(tRVCC <10msec) a minimum tPOR =10 msec must be allowed. For slower rise times, 10ms <tRUCE <200ms, a minimum
tPOR=tRVCC must be allowed.
VCCIO
VCC
tRVCC
Figure 18. Power-Up Requirements/Recommendations
Voltage
VCCOFFSET
tPOR
Time
27
Joint Test Access Group (JTAG)
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not in the least of which con-
cerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE
standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture.
The JTAG boundary scan test methodology allows com plete observation and control of the boundary pins of a JTAG-compatible
device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow
users to run three required tests along with several user-defined tests.
JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verifi cation
of higher level system elements.
The 1149.1 standard requires the followin g three tests:
• Extest Instruction: The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary
test mode, selecting the boundary scan register to be connected between the TAP’s Test Data In (TDI) and Test Data Out (TDO)
pins. Boundary scan cells are preloaded with test patters (via the Sample/Preload Instruction), and input boundary cells capture the
input data for analysis.
• Sample/Pr eload Instruction: This instruction allows a device to remain in its functional mode, while selecting the boundary scan
register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan
operation, allowing users to sample the functional data entering and leaving the device.
TAp Controller
State Machine
(16 States) Instruction Decode
&
Control Logic
TCK
TMS
TRSTB
Mux TDO
Instruction Register
Boundary-Scan
Register (Data Register)
Bypass
Register
Mux
RDI
I/O Registers
Internal
Register
User Defined Data Register
Figure 19. JTAG Block Diagram
28
• Bypass Instruction: The Bypass in struction allows data to skip a device’s boundary scan entirely, so the data passes through the
bypass register. The By pass instruction allow s users to test a device w ith out passing through other d evices. The bypass register i s
connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation
of the device.
Recommended Unused Pin Terminations for the RadHard Eclipse FPGA Devices
All unused, general purpose I/O p ins can be tied to VCC, GN D, or H IZ (high i mpedance) inte rnally using th e Confi guration edi tor.
This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint ->Fix
Placement in the Option pull-down menu of SpDE. The rest of the pins should be term inated at the bo ard level in the manner pre-
sented in Table 8.
Note: X---> number, Y ---> alphabetical character
Table 7: JTAG Pin Descriptions
Pin Function Description
TDI/RSI Test Data In for JTAG/RAM init. Serial Data In Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VCC if
unused.
TRSTB/RRO Active low Reset for JTAG/RAM init. reset out Hold LOW during normal oper atio n. Connects to serial
PROM data in for RAM initialization. Connect to GND
if unused.
TMS Test Mode Select for JTAG Hold HIGH during normal operation. Connect to VCC if
not used for JTAG.
TCK Test Clock for JTAG Hold HIGH or LOW during normal operation. Connect
to VCC or GND if not used for JTAG.
TDO/RCO Test data out for JTAG/RAM init. clock out Conn ect to serial PROM clock for RAM initialization.
Must be left unconnected if not used for JTAG or RAM
initialization.
Table 8: Recommended Unused Pin Terminations
Signal Name Recommended Termination
IOCTRL <y> Any unused pins of this type must be connected to either VCC or GND.
CLK <x> Any unused clock pins should be connected to eith er VCC or GND.
INREF <y> If an I/O bank does not require the use of INREF signal, the pin should be connected to GND.
29
Table 9: RadHard Eclipse Device Pins
Pin Direction Function Description
CLK I Global clock network driver Low skew global clock. This pin provides access to the dedicat-
ed, distributed network capable of driving the CLOCK, SET,
RESET, F1 and A2 inputs to the Logic Cell; READ and WRITE
CLOCKS, Read and Write Enables of the Embedded RAM
Blocks; and Output Enables of the I/O.
I/O(A) I/O Inp ut/Output Pin The I/O pin is a bi-directional pin, configurable to either an input
only, output-only, or bi-directional pin. Th e A inside the paren-
thesis means that the I/O is located in Bank A. If an I/O is not
used, SpDE (QuickWorks Tool) provides the option of tying that
pin to GND, VCC, or TriState during prog ramming.
VCC I Core power supply pin Connect to 2.5 V supply
VCCIO(A) I Input voltage tolerance pin
This pin connects to the 3.3V supply. The A inside the parenthesis
means that V
CCIO
is located in BANK A. Every I/O pin in Bank A will
be tolerant of V
CCIO
input signals and will output V
CCIO
level signals.
GND I Ground pin
Connect to ground.
DEDCLK I Dedicated clock pin Low skew global clock. This pin provides access to the dedicat-
ed, distributed clock network capable of driving the CLOCK in-
puts of all sequential elements of the device (e.g. RAM and flip-
flops).
INREF(A) I Differential reference voltage The A inside the parenthesis means that INREF is located in
BANK A. This pin should be tied to GND for LVCMOS3 and
LVTTL2 inputs.
IOCTRL(A) I High drive input
This pin provides fast RESET, SET, CLOCK, and ENABLE access to
the I/O cell flip-flops, providing fast clock -to-out and fast I/O response
times. This pi n ca n al so double as a high-drive pin to the intern al logic
cells. The A inside the
parenthesis means that IOCTRL is located
in BANK A. This pin should be tied to GND or VCC if it is not
used.
30
PACKAGING
Figure 20. 208-pin Ceramic FLATPACK
1. All exposed metalized areas are gold plated over nickel plating per
MIL-PRF-38535.
2. Lead finishes are in accordance with MIL-PRF-38535.
3. Letter designations are to cross-reference to MIL-STD-1835.
4. Packages may be shipp ed w ith repaired leads as shown.
31
1. All exposed metalized areas are gold plated over nickel plating per MIL-PRF-38535.
2. App note: Capacitor monitoring pads are dimensioned for a MIL-C-55581 CDR33 chip capacitor.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Letter designations are to cross-reference to MIL-STD- 1835.
5. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired area.
6. Seal ring is connected to V
SS
.
7. Drawing units are in millimeters.
Figure 21. 288-pin Ceramic Quad FLATPACK
32
1. Seal ring is connected to V
SS
.
2. Units are in millimeters (inches).
3. All top sides exposed metalized areas must be gold plated
100 to 225 micro-inches thick and all bottom side exposed
metalized areas must be gold plated to 60 micro-inches thick
nominal. Both sides shall be over electroplated nickel under-
coating 100 to 350 micro-inches per MIL-PRF-38535. The
bottom side plating is not subject to the salt atmosphere re-
quirements of 40-7150-xx.
4. Camber: 0.08MM max.
5. Geometry is vendor optio nal. Can not be alphan umeric and
must be isolated within the shaded area. M ust be electr ically
isolated. Plating is optional.
Figure 22. 484-pin Ceramic Column Grid Array
33
1. Seal ring is connected to V
SS
.
2. Units are in millimeters (inches).
3. All top sides exposed metalized areas must be gold plated
100 to 225 micro-inches thick and all bottom side exposed
metalized areas must be gold plated to 60 micro-inches thick
nominal. Both sides shall be over electroplated nickel under-
coating 100 to 350 micro-inches per MIL-PRF-38535. The
bottom side plating is not subject to the salt atmosphere re-
quirements of 40-7150-xx.
4. Camber: 0.08MM max.
5. Geometry is vendor optio nal. Cannot be alph anumeric and
must be isolated within the shaded area. Must be e lectrically
isolated. Plating is optional.
Figure 23. 484-pin Ceramic Land Grid Array
34
Figure 23. 484-pin Plastic Ceramic Land Grid Array
1. Units are in millimeters.
2. Dimension measured at the maximum solder ball diameter
parallel to primary datum C.
3. Primary datum C and the seating plane are defined by the
spherical crowns of the solder balls.
35
CONTACT FACTORY
ORDERING INFORMATION
UT6325 RadHard FPGA:
UT *****
Device Type:
(6325) = FPGA
Packaging: (NOTE 5)
(W) = 208-pin PQFP Plastic Quad Flatpack
(X) = 208-pin CQFP Ceramic Quad Flatpack
(P) = 280-pin PBGA Plastic Ball Grid Array
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(R) = 484-pin PBGA Plastic Ball Grid Array
(Z) = 484-pin CLGA Ceramic Land Grid Array (NOTE 6)
Screening: (NOTES 3 & 4)
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold, solder, or tinned)
***
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is F ACTORY OP TION "X" only. Radiation
neither tested nor guaranteed.
4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
5. Use the following table to determine which lead finishes to select for the corresponding package options.
6. Aeroflex offers COLUMN ATT ACHMENT as an additional service for the ceramic land grid array (Case Outline "Z"). If needed,
please ask for COLUMN ATTACHMENT when submitting your request for quotation.
Package Option Associated Lead Finish Option
(W) 208-PQFP (A) Hot Solder Dipped
(X) 208-CQFP (A) Hot Solder Dipped / (C) Gold
(P) 280-PBGA (A) Hot Solder Dipped
(Y) 288-CQFP (A) Hot Solder Dipped / (C) Gold
(R) 484-PBGA (A) Hot Solder Dipped
(Z) 484-CLGA (C) Gold
36
CONTACT FACTORY
UT6325 FPGA: SMD
5962 - 04229 Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gol d or solder)
Case Outline:
(X) = 208-pin CQFP Ceramic Quad Flatpack
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(Z) = 484-pin CLGA Ceramic Land Grid Array (NOTE 3)
Class Designator: (NOTE 4)
(Q) = QML Class Q
(V) = QML Class V
Device Type (NOTE 5)
01 = UT6325 Military Temperature Range
02 = No Longer Available. Contact Factory
03 = UT6 325 assembled to Aeroflex’s Q+ flow
Drawing Number: 04229
Total Dose: (NOTE 6)
(R) = 1E5 (100 krad)( Si))
(F) = 3E5 (300 krad)(Si))
Federal Stock Class Designator: No options
** ***
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Aeroflex offers COLUMN ATTACHMENT as an additional service for the ceramic land grid array (Case Outline "Z"). If needed, please ask for
COLUMN ATTACHMENT when submitting your request for quotation.
4. Product offered to an approved QML-V flow is not currently available through the SMD. If you require product that is assembled to Aeroflex’s standard
QML-V flow, you should order device type 03.
5. Aeroflex’s Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QM L-Q product through that SMD that is manufactured with Aeroflex’s
standard QML-V flow.
6. Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.
37
CONTACT FACTORY
ORDERING INFORMATION
UT6250 RadHard FPGA:
UT *****
Device Type: (NOTE 7)
(6250) = FPGA
Packaging: (NOTE 5)
(W) = 208-pin PQFP Plastic Quad Flatpack
(X) = 208-pin CQFP Ceramic Column Grid Array
(P) = 280-pin PBGA Plastic Ball Grid Array
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(R) = 484-pin PBGA Plastic Ball Grid Array
(Z) = 484-pin CLGA Ceramic Land Grid Array (NOTE 6)
Screening: (NOTES 3 & 4)
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold, solder, or tinned)
***
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. T ested at 25°C only. Lead finish is F ACTORY OP TION "X" only. Radiation
neither tested nor guaranteed.
4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
5. Use the following table to determine which lead finishes to select for the corresponding package options.
6. Aeroflex offers COLUMN A TT ACHMENT as an additional service for the ceramic land grid array (Case Outline "Z"). If needed,
please ask for COLUMN ATTACHMENT when submitting your request for quotation.
7. Device UT6250 is not currently available. Please contact factory to obtain status on availability time frame.
Package Option Associated Lead Finish Option
(W) 208-PQ FP (A) Hot Solder Dipped
(X) 208-CQFP (A) Hot Solder Dipped / (C) Gold
(P) 280-PBGA (A) Hot Solder Dipped
(Y) 288-CQFP (A) Hot Solder Dipped / (C) Gold
(R) 484-PBG A (A) Hot Solder Dipped
(Z) 484-CLGA (C) Gold
38
CONTACT FACTORY
UT6250 FPGA: SMD
5962 - 04229
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 208-pin CQFP CeramicQuad Flatpack
(Y) = 288-pin CQFP Ceramic Quad Flatpack
(Z) = 484-pin CLGA Ceramic Land Grid Array
Class Designator: (NOTE 3)
(Q) = QML Class Q
(V) = QML Class V
Device Type (NOTE 4)
TBD = UT6250 Military Temperature Range
Drawing Number: 04229
Total Dose:
(R) = 1E5 (100 krad)( Si))
(F) = 3E 5 (300 krad )( Si))
Federal Stock Class Designator: No options
** ***
Notes:
1.Lead finish (A,C, or X) must be specif ied.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiat ion must be specified when ordering. QML Q not available without radiation hardening.
4.The UT6250 is not currently available through the SMD. Please contact factory for availability time frame.
39
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com info-ams@aeroflex.com
Our passion for perform a nce is defined by three
attributes represented by the s e three icons:
solution-minde d, perform an c e-d riven and custom e r-focu sed
Aeroflex Colorado Springs, Inc. reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
