Marvell. Moving Forward Faster
Doc. No. MV-S104983-01, Rev. A
October 5, 2009
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Cover
88EM8040/88EM8041
Power Factor Correction Controller for
Flyback Topology
Datasheet
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88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 2 Document Classificatio n: Proprietary October 5, 2009, Prelimin ary
88EM8040/88EM8041
Power Factor Correction Controller for Flyback Topology
Datasheet
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 3
PRODUCT OVERVIEW
The Marvell® 88EM8040/88EM8041 device is a high
performance Power Factor Correction (PFC) Controller for
flyback applications. Both devices work at fixed frequencies,
88EM8040 at 60kHz while 88EM8041 at 120kHz. It can be used
in a wide variety of universal input PFC flyback converters with
an output power range of up to 150W without using any external
driver.
Marvell advanced mixed signal technology ensures the lowest
Total Harmonic Distortion (THD) in the industry . The IC operates
under average Continuous Conduction Mode (CCM).
The 88EM8040/88EM8041 PFC controller improves the steady
state and transient performance through Marvell's innovative
Digital Signal Processing (DSP) solution. The proprietary
adaptive over-current protection has the ability to ensure almost
constant power constraint and provides safety provisions
including open loop and over voltage protection protocols.
The internal voltage loop compensation and current loop control
guarantees system stability and thus reduces the external
component count and costs.
The 8-pin SOIC package further facilitates the application
design process, saving board space. The resultant simple
system design and minimum cost makes 88EM8040/88EM8041
the ideal choice for any flyback application with PFC .
General Features
Patented DSP control with adaptive loop coefficient
Continuous Conduction Mode (CCM) operation
Average current mode control
Adaptive control loop achieves high power factor for a
wide range of voltage and load conditions
Adaptive over current protection for universal voltage
Fixed frequency of operation
High power factor and low harmonic distortion for a wide
range of load conditions
Up to 2A driver capability
Minimal external components required
Under voltage lockout (UVLO)
Over voltage protection (OVP)
Thermal shutdown
Input line frequency range from 45Hz to 65Hz
Applications
Universal input PFC flyback converters
AC/DC adaptors and battery charger
Figure 1: PFC Flyback Circuit Diagram
FB
Drain
OCP
VDD
AC
IN
Opto-Coupler
Vout
N
p
N
S2
D
R2
C
O2
R
sen
VIN
R
a
R
b
R
c
ISNS
SW SGND
PFC
C
in
Bridge
Retifier
diode
C
cs
R
cs
D
sn
R
sn
C
sn
Q1
R
f1
R
S2
R
S3
R
S4
R
S5
Load
R
S1
C
S1
C
S2
R
gate
C
VDD
V
ref
PGND
88EM8040/
8041
V
DCin
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
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Table of Contents
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 5
Table of Contents
Table of Contents .......................................................................................................................................5
List of Figures.............................................................................................................................................7
List of Tables ..............................................................................................................................................9
1 Signal Description.......................................................................................................................11
1.1 Pin Configurations...........................................................................................................................................11
1.2 Pin Descriptions..............................................................................................................................................11
2 Electrical Specifications .............................................................................................................13
2.1 Absolute Maximum Ratings ........ ...................................................................................................................13
2.2 Recommended Operating Conditions.............................................................................................................14
2.3 Electrical Characteristics ................................................................................................................................15
3 Functional Description................................................................................................................19
3.1 Overview .........................................................................................................................................................19
3.2 Signal Process and Functions.........................................................................................................................20
4 Functional Characteristics .........................................................................................................21
4.1 VDD Characteristics ........................................................................................................................................21
4.2 VFB Characteristics for Over Voltage Protection.............................................................................................23
4.3 Switching Frequency Characteristics....................... .. ....................... ... ...................... ... ..................................24
4.4 Over Current Threshold Characteristics..........................................................................................................25
5 Design and Applications Information........................................................................................27
5.1 Input Voltage Resistor Divider on VIN Pin.......................................................................................................28
5.2 Isolated Voltage Loop and Ou tput Voltage Feedback on FB Pin....................................................................30
5.2.1 Resistor Divider Design for Output Voltage......................................................................................31
5.2.2 Compensation Network Design...................... ....................... ...................... ....................... ..............31
5.2.3 RS2 and Rf1 Design.........................................................................................................................33
5.3 Current Sensing and Over Current Protection ................................................................................................34
5.3.1 Current Sensing Through ISNS Pin..................................................................................................34
5.3.2 Average Current Signal and Over Power Limitation.........................................................................35
5.3.3 Cycle by Cycle Current Protection through OCP Pin........................................................................36
5.3.4 Peak Current and Average Current Relationship .............................................................................38
5.4 SW Pin to MOSFET Gate ...............................................................................................................................39
5.5 VDD, Signal Ground (SGND) and Power Ground (PGND)............ ... ... .. ....................... ... .. ... ....................... ...39
5.6 90W/20V Signal Stage PFC Adaptor Schematic and Bill of Materials (BOM).................................................41
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 6 Document Classificatio n: Proprietary October 5, 2009, Prelimin ary
6 Mechanical Drawings..................................................................................................................43
6.1 Mechanical Drawings......................................................................................................................................43
7 Part Order Numbering/Package Marking ..................................................................................45
7.1 Part Order Numbering ..................................................................................................................................45
7.2 Package Markings..................... ...................... .......................................... ......................................................46
A Revision History ..........................................................................................................................47
List of Figures
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 7
List of Figures
Figure 1: PFC Flyback Circuit Diagram ............................................................................................................3
1 Signal Description ........................................................................................................................... 11
Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11
2 Electrical Specifications ................................................................................................................. 13
3 Functional Description.................................................................................................................... 19
Figure 3: Top Level Block Diagram..................................................................................................................19
4 Functional Characteristics.............................................................................................................. 21
Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21
Figure 5a: IDD vs. VDD (VDD_ON)........................................................................................................................21
Figure 5b: IDD vs. VDD (VDD_ON)........................................................................................................................21
Figure 6a: IDD Operation (IDD_OP) vs. Temperature........................................................................................ 22
Figure 6b: IDD Operation (IDD_OP) vs. Temperature........................................................................................ 22
Figure 7: VDD On/Off vs. Temperature ...........................................................................................................22
Figure 8: IDD vs. VFB (OVP).............................................................................................................................23
Figure 9: VFB_OVP vs. Temperature..............................................................................................................23
Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23
Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23
Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature...........................................................24
Figure 13: Switching Frequency vs. Temperature .............................................................................................24
Figure 14: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................25
Figure 15: Over Current (VIOVER) vs. Temperature.........................................................................................25
Figure 16: VIOVER_CYC_ON/OFF vs. Temperature........................................................................................26
5 Design and Applications Information............................................................................................ 27
Figure 17: Internal Block for Zero-cross Detection, Brown-out Protection.........................................................28
Figure 18: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29
Figure 19: Input Voltage Resistor Divider Layout Guide lines ............................................................................30
Figure 20: Secondary Compensation Network with Opt-coupler.......................................................................30
Figure 21: Bode Plot of Compensation Network at Secondary Side .................................................................32
Figure 22: Bias Current for Offset Voltage on FB Pin........................................................................................33
Figure 23: Current Sensing Circuit.....................................................................................................................34
Figure 24: Current Sensing and Cycle by Cycle Over Current Protection Circuit..............................................36
Figure 25: Current Sensing and Cycle by Cycle Over Current Protection Waveforms......................................36
Figure 26: SW Pin Layout Guidelines................................................................................................................39
Figure 27: VDD Decoupling Capacitor and Ground Layout Guid elines.............................................................40
Figure 28: 90W/20V Single Stage PFC Adaptor Schematic..............................................................................41
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 8 Document Classificatio n: Proprietary October 5, 2009, Prelimin ary
6 Mechanical Drawings ...................................................................................................................... 43
Figure 29: 8-Lead SOIC Mechanical Drawing ...................................................................................................43
7 Part Order Numbering/Package Marking....................................................................................... 45
Figure 30: 88EM8040/88EM8041 Sample Ordering Part Number ....................................................................45
Figure 31: 88EM8040/88EM8041 Package Marking .........................................................................................46
A Revision History ...............................................................................................................................47
List of Tables
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 9
List of Tables
1 Signal Description ............................................................................................................................11
Table 1: Pin Descriptions................................................................................................................................11
Table 2: Pin Descriptions................................................................................................................................12
2 Electrical Specifications ..................................................................................................................13
Table 3: Absolute Maximum Ratings..............................................................................................................13
Table 4: Recommended Operating Conditions...............................................................................................14
Table 5: Electrical Characteristics ..................................................................................................................15
3 Functional Description.....................................................................................................................19
4 Functional Characteristics...............................................................................................................21
5 Design and Applications Information.............................................................................................27
Table 6: Comparison Between Average Current Mode and Critical Transition Mode Control........................27
Table 7: Current Sensing Circuit.....................................................................................................................35
Table 8: Current Sensing Resistor Selection Reference ................................................................................35
6 Mechanical Drawings .......................................................................................................................43
7 Part Order Numbering/Package Marking........................................................................................45
Table 9: 88EM8040/88EM8041 Part Order Options.......................................................................................45
A Revision History ...............................................................................................................................47
Table 10: Revision History................................................................................................................................47
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
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Signal Description
Pin Configurations
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 11
1Signal Description
1.1 Pin Configurations
1.2 Pin Descriptions
Table 1: Pin Descriptions
Figure 2: SOIC-8 Pin Diagram (Top View)
1
2
3
4
8
7
6
5
PGND
SGND
ISNS
OCP
SW
VDD
FBVIN
Pin # Pin Name Pin Type Pin Description
1 PGND Ground Power Ground
2 SGND Ground Signal Ground
3 ISNS Input Current Sense
4 VIN Input Voltage Input
5 FB Input Feedback
6 OCP Input Over Voltage Current Protection
7 VDD Supply IC Supply Voltage
8SWOutputSwitch
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 12 Document Classification: Proprietary October 5, 2009, Preliminary
Table 2: Pin Descriptions
Pin # Pin Name Pin Function
1PGNDPower Ground
Connected to the source of t he primary MOSFET. The PCB trace from the power ground to the
source of the primary MOSFET must be kept as short as possi ble.
To avoid any switching noise interruption on signal processing, PGND and SGND remain
seperate inside the I C.
2SGNDSignal Ground
Must be connected to the power ground wi th the Kelv in sensi ng conn ect ion , so that SGND has
dedicated trace and connections and provides noi seless environment for the signal processing.
3ISNSCurrent Sense
Sense resistor varies from 0.15Ω at 120W rated load to 0.44Ω for 40W rated load. Used for
current shaping and for over current protection.
4VINVoltage Input
• Connects to resistive divider at input AC line “phase” to GND. Voltage applied is a half
rectified sine wave scaled down by the input resistive divider.
• Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is
recommended to be designed from the input AC “phase” to GND in order to reduce the
standby power. Higher impedance is preferred with the right PCB design on this pin signal.
• Voltage is compared w it h a th re sh ol d refe re n ce (V VIN_BR) to detect the zero-cross location
of the input sine wave and synthesize (regenerate) the input si ne wave. This sine wave is
used to generate the current reference.
• Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1
ratio from the highsid e resistor to the lowside resistor is corresponding to the “brown-out
protection” input voltage as 50V (RMS). Increasing that raio will increase the “brown-out
voltage”. Please refer to footnote1 for further explaination.
5FBFeedback
It is connected to the emitter of the transistor on the secondary side of the opto coupler
(referred to within the Ap picati on Informat ion sectio n). The outpu t volt age i s scaled to 2 .5V with
100% rated value. Transition from soft start to normal regulation at 87.5% rated VFB. Over
voltage shutdown SW gate signal at 107% rated VFB and recover once below VFB_OVP.
There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB pin. When FB Volta ge reaches
VFB_OVP_LATCH, SW signal is shutdown and latched until another VDD power on reset.
6OCPOver Current Protection
Used to turn off the MOSFET when it is pulled as logic low
7VDDIC Supply Voltage
Nominal voltage is typical 12V and the Under Voltage Lock Out (UVLO) for VDD <VDD_UVLO
(Table 5). Start volta ge of IC is VDD_On (Table 5) and maximum voltage is 16V (Table 5). It
should be clamped by a zener for protection in the system design.
8SWSwitch
PWM gate signal for the switch. Connects to the gate of external MOSFET. It is the DSP core
output for ON/OFF time buffered through the internal adaptive driver.
1. Brown-out voltage is determined by Ra, Rb and Rc as shown in Figure 1. Please refer to page 29 for a further
understanding.
Electri ca l Specific at io ns
Absolute Maximum Ratings
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 13
2Electrical Specifications
2.1 Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings1
NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
1. Exceeding the absolute maximum rating may damage the device.
Symbol Parameter Min Max Units
VDD Power Supply (Voltage to PGND=SGND) -0.3 18 V
VIsns Voltage at ISNS pin -0.5 3 V
VOCP Voltage at OCP pin -0.3 5.5 V
VVIN Voltage at VIN pin -0.3 5.5 V
VFB Voltage at FB pin -0.3 5.5 V
ISW Driver Current (In stantaneous Peak) 2 A
θJA Thermal Resistance SOIC-8 156.5 °C/W
Thermal Resistance DIP-8 89.5 °C/W
TAOperating Ambient Temperature Range2
2. Specifications over the -40°C to 85°C operating temperature ranges are assured by design, characterization and
correlation with statistical process controls.
-40 85 °C
TJMaximum Junction Temperature 125 °C
TSTOR Storage Temperature Range -65 150 °C
VESD ESD Rating3
3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5kΩ in series with 100pF.
2kV
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 14 Document Classification: Proprietary October 5, 2009, Preliminary
2.2 Recommended Operating Conditions
Table 4: Recommended Operating Co nditions1
Symbol Parameter Min Typ Max Units
TAOperating Ambient Temperature2-40 85 °C
TJJunction Temp erature -20 125 °C
1. This device is not guaranteed to function outside the specified operating temperature range.
2. Over the –40°C to 80°C operating temperature ranges are assured by design, characterization, and correlation with
statistical process controls.
Electri ca l Specific at io ns
Electrical Characteristics
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 15
2.3 Electrical Characteristics
Table 5: Electrical Characteristics
NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25°C.
Symbol Parameter Conditions Min Typ Max Units
VDD Supply
VDD Supply Voltage 7.0 12 16 V
VDD_ON VDD Power On Threshold 11.9 V
VDD_UVLO VDD Power Off Threshold
(UVLO) After VDD is powered
up and running 7.0 V
VDD_UVLO_HYS VDD_UVLO Hysteresi s 4.8 5 V
IDD_QST VDD Quiescent Current1VDD = 12 V 95 µA
IDD_OP VDD Operating Current VDD = 12V;
CGate = 1nF
FSW = 118kHz
VIN=0
5.2 mA
Thermal Shutdown
TSD Thermal Shutdown 150 °C
TSD_HYS Hysteresis for Thermal
Shutdown 25 °C
Adaptive Output Gate Driver
VG_HI Minimum Gate High Voltage2VDD = 12V
CGate = 1nF
Sourcing 500mA
10.0 V
VG_LO Maximum Gate Low Voltage3VDD = 12 V
CGate = 1nF
Sinking 500mA
2.0 V
RDSON Gate Drive Resistance Sourcing 75mA
T=25C2.4 Ω
Gate Drive Resistance Sinking 20mA
T=25C2.0 Ω
ISW_PK Driver Peak Current CGate = 10 nF
VDD = 12 V 2.0 A
tRRise Time CGate = 1 nF 35 ns
CGate = 10 nF 125 ns
tFFall Time CGate = 1 nF 35 ns
CGate = 10 nF 145 ns
DMAX Maximum Duty Cycle 97 %
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 16 Document Classification: Proprietary October 5, 2009, Preliminary
DMIN Minimum Duty Cycle 3.0 %
Feedback/Overvoltage
VFB_REG Normal Regulation Reference IC powered on 2.55 V
VFB_OVP Over Voltage Protection
Threshold At 107% of VFB_REG.2.71V
VFB_OVP_HYS Over Voltage Protection
Hysteresis 0.108 V
VFB_OVP_LATCH Over Vo ltage Protection Latch 3.77 V
Current Sensing and Current Pr otection4
VIOVER_TH1 Over Current Threshold Zone
15Peak value of half-sine
voltage at VIN:
1.26<VIN<1.89Vpk6
397 mV
VIOVER_TH2 Over Current Threshold Zone
25Peak value of half-sine
voltage at VIN:
1.89<VIN<2.59Vpk7
329 mV
VIOVER_TH3 Over Current Threshold Zone
35Peak value of half-sine
voltage at VIN:
2.59< VIN<3.43Vpk8
269 mV
VIOVER_TH4 Over Current Threshold Zone
45Peak value of half-sine
voltage at VIN:
3.43<VIN<3.85Vpk9
202 mV
VIOVER_CYC_ON Cycle by cycle current
protection logic input (OCP
pin) threshold for SW on10
1.68 V
VIOVER_CYC_OFF Cycle by cycle current
protection logic input (OCP
pin) threshold for SW off11
1V
88EM8040 Switching Frequency Oscil lator
FSW Frequency
(Average Mode) kHz
88EM8041 Switching Frequency Oscil lator
FSW Frequency 118 kHz
1. Quiescent Current: VDD power supply current before VDD first time reaches VDD_On.
2. Considering the voltage drop on the internal driver MOSFET during current sourcing.
3. Considering the voltage drop on the internal driver MOSFET during current sinking.
Table 5: Electrical Characteristics (Continued)
NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25°C.
Symbol Parameter Conditions Min Typ Max Units
Electri ca l Specific at io ns
Electrical Characteristics
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 17
4. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four
zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current
values.
5. Threshold of negative voltage drop across Rsns due to instantaneous current
6. With input divider ratio of 1/100, these values are equivalent to 90 Vrms<Vline<135 Vrms.
7. With input divider ratio of 1/100, these values are equivalent to 135 Vrms<Vline<185 Vrms.
8. With input divider ratio of 1/100, these values are equivalent to 185 Vrms<Vline<245 Vrms.
9. With input divider ratio of 1/100, these values are equivalent to 245 Vrms<Vline<275 Vrms.
10.When OCP pin is above VIOVER_CYC_ON as 1.68V, then SW is controlled by the PWM block for on and off.
11.When OCP pin is below VIOVER_CYC_OFF as 1V, then SW is turned off and released at the next switching cycle if OCP
pin is above VIOVER_CYC_ON
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
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Functional Description
Overview
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
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3Functional Description
3.1 Overview
The 88EM8040/88EM8041 is a high performance, low-cost with minimum component count Power
Factor Correction (PFC) Controll er. The device is used for controlling Universal input flyback
converters in systems or standalone products. The high performance of 88EM8040/88EM8041 is
accompanied with its small size and simplicity of application. Figure 3 shows the top level block
diagram.
Figure 3: Top Level Block Diagram
DSP
Core
88EM8040/8041
Current
Amplifier MUX
Switcher
&
ADC
Current
Protection
Threshold
Selection
Zero Cross
Detect
Power
Distribution
and
Bandgaps
Startup Setting
or
Frequency
Setting
Over
Temperature
Gate
Driver
Current
Protection
Protection
Management
Clock
ISNS
FB
VIN
I
_over
I
_over
V
o_over
T
_over
V
o_over
SW
OCP
VDD
Oscillator
Fault
Driv er Disa ble
PGND SGND
Output
Volt age Level
Detect
Serial Data
Interface
Stat e Machine
Note
I_over, Vo_over, and T_over are the over current, over voltage, and over temperature
signals respectively.
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 20 Document Classification: Proprietary October 5, 2009, Preliminary
3.2 Signal Process and Functions
The 88EM8040/88EM8041 boost power board includes three inputs:
Resistive divider signal from AC line voltage
Feedback from the output DC bus
Voltage across the current sense resistor
The input phase voltage to ground (half rectified sine wave) scaled down by the input resistive
divider is applied to pin VIN. This signal used for estimation of the AC line voltage and re generation
of the AC sine wave. It is also used for voltage level detection that produces adaptive multiple
thresholds for the over current limit and guarantees a constant power limit from the AC source.
Signal from the DC bus voltage through the muxed 12-bit Analog-to-Digital Converter (ADC)
provides the feedback data for the voltage PI control loop.
HF switching current pulse signal is retrieved from the voltage drop across the current sense resistor
that is negative to GND. This signal after HF noise filter and fi xed gain amplification, is transferred
through the muxed 12-bit ADC to the digital current loop and the current error amplifier. The
reference current for the current control PI loop is provided by multiplying the voltage error amplifier
output and the regenerated sinusoidal line voltage information.
Functional Characteristics
VDD Characteristics
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 21
4Functional Characteristics
The following applies unless otherwise noted: VIN = 60Hz half-w ave sinusoidal from 0V to the peak
voltage (VPK) given in the test conditions of each grap h . TA = 25°C.
All measurement readings are typical.
4.1 VDD Characteristics
Figure 4: IDD Quiescent (IDD_QST) vs. VDD
Test Conditions:
VIN = 0V
FSW = 118kHz
VFB = 0V
CGate = 1nF
V_Isns = 0V
Figure 5a: IDD vs. VDD (VDD_ON)Figure 5b: IDD vs. VDD (VDD_ON)
Test Conditions:
VIN = 0V
FSW = 118kHz
VFB = 0V
CGate = 1nF
V_Isns = 0V
Test Conditions:
VIN = 0V
FSW = 118kHz
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
0
10
20
30
40
50
60
70
80
90
100
024681012
VDD (V)
IDD (μA)
0
1
2
3
4
5
6
0246810121416
VDD ( V)
IDD (mA)
VDD Fal ling
VDD Ris ing
0
1
2
3
4
5
6
7
0246810121416
VDD (V)
IDD (mA)
VDD Fal ling
VDD Ris ing
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 22 Document Classification: Proprietary October 5, 2009, Preliminary
Figure 6a: IDD Operation (IDD_OP) vs.
Temperature Figure 6b: IDD Operation (IDD_OP) vs.
Temperature
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
VFB = 0V
CGate = 1nF
V_Isns = 0V
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
Figure 7: VDD On/Off vs. Temperature
Test Conditions:
VIN = 0V
FSW = 118kHz
FFB = 2.4V
CGate = 1nF
V_Isns = 0V
0
1
2
3
4
5
6
7
-40-20020406080
Temperature (°C)
I DD ( mA)
0
1
2
3
4
5
6
7
-40-20 0 20406080
Temperature (°C)
I DD (m A)
0
2
4
6
8
10
12
14
-40-200 20406080
Temperature (°C)
VDD (V)
ON
OFF
Hysteresis
Functional Characteristics
VFB Characteristics for Over Voltage Protection
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 23
4.2 VFB Characteristics for Over Voltage Protection
Figure 8: IDD vs. VFB (OVP) Figure 9: VFB_OVP vs. Temperature
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
CGate = 1nF
V_Isns = 0V
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
CGate = 1nF
V_Isns = 0V
Figure 10: VFB_OVP Hysteresis vs. Temper at u re Figure 11: VFB_OVP_LATCH vs. Temperature
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
CGate = 1nF
V_Isns = 0V
Test Conditions:
VDD = 12V
VIN = 0V
FSW = 118kHz
CGate = 1nF
V_Isns = 0V
3.0
3.5
4.0
4.5
5.0
5.5
2.02.12.22.32.42.52.62.72.82.93.0
VFB (V)
IDD (mA)
VFB Falling
VFB Rising
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-40-200 20406080
Temperature (C)
VFB (V)
Recovery Threshold
O VP Thres ho ld
0.00
0.05
0.10
0.15
0.20
0.25
0.30
-40 -20 0 20 40 60 80
Temperature (C)
VFB (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-40 -20 0 20 40 60 80
Tem perature (°C)
VFB (V)
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 24 Document Classification: Proprietary October 5, 2009, Preliminary
4.3 Switching Frequency Characteristics
Figure 12: Normal Regulation Reference
(VFB_REG) vs. Temperature
Test Conditions:
VDD = 12V
VIN = 2V
FSW = 118kHz
CGate = 1nF
V_Isns = 0V
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
-40-200 20406080
Temperature (°C)
VFB (V)
Figure 13: Switching Frequency vs. Temperature
Test Conditions:
VDD = 12V
VIN = 0V
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
0
20
40
60
80
100
120
140
-40-20 0 20406080
Temperature (°C)
Freq uen cy (kHz)
FSW (8041 )
FSW (8040 )
Functional Characteristics
Over Current Threshold Characteristics
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 25
4.4 Over Current Threshold Characteristics
Figure 14: Over Current (VIOVER) vs. Input Volt age
VIN Peak Value)
Test Conditions:
VDD = 12V
FSW = 118kHz
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
01122334455
VIN (V)
VCS (V)
Figure 15: Over Current (VIOVER) vs. Temperature
Test Conditions:
VDD = 12V
FSW = 118kHz
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
0
50
100
150
200
250
300
350
400
450
-40-200 20406080
Temperature (C)
VCS (V)
V
IN
= 1.5V
V
IN
= 2.25V
V
IN
= 3V
V
IN
= 3.7V
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 26 Document Classification: Proprietary October 5, 2009, Preliminary
Figure 16: VIOVER_CYC_ON/OFF vs. Temperature
Test Conditions:
VDD = 12V
VIN = 0V
VFB = 2.4V
CGate = 1nF
V_Isns = 0V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40-20020406080
Te m pera ture (°C)
Vio ver (V)
V
IOVER_CYC_ON
V
IOVER_CYC_OFF
Design and Applications Information
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 27
5Design and Applications Information
The flyback (isolated buck/bo ost) topology is used to simplify the two stage front-end design to a
single isolated Power Factor Correction (PFC) conversion stage. Compared to the two stage PFC
structure, a single stage PFC is a more cost effective solution.
The 88EM8040/88EM8041 chip control algorithm uses Average Current Mode Control for power
factor correction applications with low harmonic distortion and good noise immunity. The IC senses
the output voltage and forces it to follow the reference voltage to produce a stable DC output voltage
matching the design requirements. It also senses the primary current and forces the average signal
of the primary current to follow the sinusoidal current reference, therefore achieving power factor
correction. Compared to other competitors parts operating under Critical Transition Mode Control,
the 88EM8040/88EM8041 has many advantages as shown in Table 6l
Marvell's innovative PFC control technology improves the performance of the isolated flyback
converter used in PFC applications. The flyback PFC solution based on the 88EM8040/88EM8041
provides customers with a simple structure, low cost without sacraficing performance compared with
the other industry solutions currently on the market.
The following sections provides guidelines for the application desi gn, component selection, and
board layout all in order to improv e flyback single stage PFC performance. There are three analog
input signals and one logic inp ut signal listed below are required from the power train to the
controller IC 88EM8040/88EM8041.
1. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through
the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC.
2. Output voltage signal at FB pin is the output voltage through the resistor divider plus the
compensation and opto-coupler to feedback on FB pin. This is for the vo ltage loop regulation.
3. Current sensing signal through the sensin g resistor to the ISNS pin. This is for the average
current mode control to achieve a good sinusoidal current waveform and high power factor.
4. The input over current protection (OCP) signal is a logic signal instead of an analog signal. It is
used to shut down the output at the SW pin when it is pulled low.
Table 6: Comparison Between Average Current Mode and Critical Transition
Mode Control
Critical Transmition Mode Control Average Current Mode Control
High peak current on switch Low peak current on switch
High diode peak current at secondary side Low diode peak current at secondary side
Variable switching frequency with lowest
switching frequency at peak input voltage Fixed switching frequency
Big transformer Small transformer
Low efficiency High efficiency
Low power factor / higher THD at high line low
load High power factor / lowerer THD at high line low
load due to adaptive loop control
Diffi c ult to achieve high power Easy to achieve high power
High cost Low cost
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 28 Document Classification: Proprietary October 5, 2009, Preliminary
The output signal from the 88EM8040/88EM80 41 is the PWM gate drive signal from the SW pin.
The switching frequency on the 88EM8040 device is fixed to 60kHz while the 88EM8041 is fixed to
120kHz. Both device tolerances are shown in the electrical char acteristics table.
5.1 Input Voltage Resistor Divider on VIN Pin
An accurate peak detection signal and zero-cross detection for regeneratin g the input sinusoidal
voltage is the most important issue for a proper curre nt shaping and total harmonic distortion (THD)
improvement. If the threshold reference is too high, near the peak area, the calculation may lose
accuracy because of the low slope. On the other hand, if the threshold reference is too low, there
could be an error on zero-cross detection due to the possible distortions near the zero-crossing. For
a universal input voltage range (85Vac~270Vac) the optimum accuracy would be achieved if the
threshold level is around 30 degree of the line cycle.
Figure 17: Internal Block for Zero-cross Detection, Brown-out Protection
To get a proper sinusoidal AC voltage, UVLO, and peak voltage detection, we need to choose the
right value for the sensing resistors: Ra, Rb, and Rc, as shown in Figure 17. If the value is too small
there will be higher power loss and if the value is too big the resistor will not properly work due to the
picking noise of the VIN signal. The recommended values are shown below:
Equation (1)
For the input voltage resistor divider, the appropriate combination based on the voltage / power
rating of the resistors should also be considered.
AC
IN
R
a
R
b
R
c
VIN
88EM8040
/8041
Peak
detecting
pulse
Phase ( )
Zero
Crossing
Power Limit
Threshold
Selection
pkline
V
_
φ
Brown-Out
Protection
Predictive
Sinusoidal
AC Voltage
V
DCin
RaRb
+
Rc
------------------ 100
1
---------1.8MΩ
18kΩ
-----------------
==
Design and Applications Information
Input Voltage Resistor Divider o n VIN Pin
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 29
Figure 18: Peak Detecting Signal for Predictive Sinusoidal AC Volta ge
As can be seen in Figure 17, the internal peak detecting circuit generates peak detecting pulse
through the inside comparator which has a threshold voltage of 0.72V (typical). Processing of this
pulse in DSP core calculates the mid-point (peak point) and the zero-crossing point of the sinusoidal
waveform. The phase angle of
φ
is calculated using the width of the high and low signal M&N.
Equation (2)
Equation (3)
Equation (4)
Peak value of the sinusoidal waveform is introduced by the relation:
Equation (5)
The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak line value
has to be higher than VVIN_BR of 0.72V (typical) for normal operation. Whenever the VVIN_BR is less
than 0.72V at the peak line value, it is considered as a Brown-out condition. The IC only generates
6% duty during the brown-out con dition. To adjust the brown-out protection point, the resistance
value of Ra, Rb and Rc can be changed. With the recommended resistor values in Equation (1) the
brown-out protection voltage is 72V peak value, which is around a 50V RMS value for the input line
voltage.
The layout of Ra, Rb and Rc should be kept as close as possible to the VIN pin, as shown in
Figure 19 in order to have a proper layout on the input voltage resistor divider and to avoid noise
picking. It is also recommended that a 0.1nF–10nF capacitor is connected between the VIN pin and
ground with the layout also close to this pin.
φ
sin)( ×
=VHalf line cycle
NMN
V
line_pk
Half line cycle
Peak detecting Pulse
V
VIN_BR
= 0.72V (Typ.)
V
line_pk
V
line_pk
φ
φφφφ
Nπ2
φ
–()=
Mπ2
φ
+()=
φ
MN–()4⁄=
Vline_pk V
φ
()
φ
()sin⁄=
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 30 Document Classification: Proprietary October 5, 2009, Preliminary
Figure 19: Input Voltage Resistor Divider Layout Guidelines
5.2 Isolated Volt age Loop and Output Volt age Feedback
on FB Pin
The88EM8040/88EM8 041 IC integrates the voltage loop into digital DSP core. This internal voltage
loop has the lower corner frequency for the PFC requirement. The FB pin is the internal voltage loop
feedback signal input. The voltage reference of the IC is 2.5V for the rated output voltage.
The Flyback PFC is an isolated power system, which needs the opto-coupler device transferring the
output voltage amplitude signal to the FB pin. Since the CTR (Current Transfer Ratio) parameter of
this opto-coupler has a big tolerance and shifts with the temperature, an additional voltage reference
and compensation is required at the secondary side. This secondary voltage loop circuit can use a
low voltage adjustable shunt regulator such as the TLV431 or a dual op-amp with a reference
voltage such as the TSM1014 to constitute the error amplifier with compensation network. Figure 20
shows the typical voltage feedback loop circuit.
Figure 20: Secondary Compensation Network with Opt-coupler
FB
OCP
VDD
VIN
ISNS
SW
PGND
SGND
Ra
Rb
RcCc
Keep layout of Rb, Rc and Cc as
close as possible to Vin pin to
keep high nois e immu nization
88EM8040/
8041
R
S3
R
S4
R
S5
C
S1
C
S2
V
ref
R
S2
V
Out
VFB
R
f1
VDD
1
2
V
err
Design and Applications Information
Isolated Voltage Loo p and Output Voltage Feedback on FB Pin
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 31
It is well known that a single stage PFC with flyback topology is not easy to maintain enough stability
while at the same time keeping a good sinusoidal current waveform and power factor under a wide
input voltage and load condition. In order to achieve enough stability as the first criteria, the
compensation network at the secondary should be designed properly, which will be described in the
following paragraph. In order to achieve a good sinusoid al current waveform and power factor, the
voltage loop regulation coefficient should also be designed properly correspon ding to the different
input voltages. The adaptive voltage loop coefficient is designed inside the IC to se lect different
voltage regulation parameters. This achieves a much better power factor and sinusoidal current
waveform compared to any of the single stage PFC power system on the market now. This is why
there is also another voltage loop regulation designed inside of the IC while an external voltage loop
compensation is designed at the secondary side of the flyback system.
5.2.1 Resistor Divider Design for Output Voltage
The design of RS3 and RS4 is based on the rated output voltage and the power loss of the resistor
divider. In order to keep low power consumption on the resistor divider and good signal to noise
immunity, a minimal total resistance of 20kΩ (Typical) is recommended for the pair of resistors RS3
and RS4.
The relation among the output voltage, referenc e voltage and resistor di vider is as;
Equation (6)
If the output voltage is designed as 20V, refere nce voltage is 2.5V and RS4 is selected as 15.4kΩ,
the value RS3 is calculated from equation (6) as 2.21 kΩ.
5.2.2 Compensation Network Design1
The compensation network should be designed by selecting the value of RS5, CS1 and CS2. A typical
compensation network is constructed in Figure 20. The transfer function is derived as;
Equation (7)
Equation (7) is simplifed as;
Equation (8)
Where:
; ; Equation (9)
The criteria to design the network in Figure 20 is to provide enough DC gain and attenuate the
double line frequency ripple by properly selecting the right zero and pole parameters. In order to
meet these criteria, zero ωz should be placed below the double line frequency (100/120Hz) and pole
Vout RS3
RS3RS4
+
-----------------------
×Vref
=
1. Please refer to the 88EM8041 90W application note for a detailed derivation of open-loop transfer function for t he overall flyback circuit.
Hs() Verr s()
VOUT s()
--------------------
=1
RS4CS1CS2
+()
--------------------------------------1sRS5CS1
+
s1sCs1Cs2
CS1CS2
+
------------------------RS5
+
⎝⎠
⎛⎞
-----------------------------------------------------
×=
Hs() Ksωz
+()
ss ωp
+()
----------------------
×=
K1
RS4CS2
------------------
=
ωz1
RS5CS1
------------------
=
ωp1
CS1CS2
CS1CS2
+
------------------------RS5
---------------------------------
=
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 32 Document Classification: Proprietary October 5, 2009, Preliminary
ωp should be placed above the double line frequency. The magnitude of the gain around the double
line frequency should below the unity gain, which is 0db axis in the bode plot, in order to atten uate
the double line frequency ripple.
The following is a design example of this network: RS4=15.4kΩ, RS5=2kΩ, CS1=4.7μF and
CS2=47nF. This produces a zero and pole as: ωz = 16.94Hz, ωp = 1.71kHz. The bode plot is shown in
Figure 21. The magnitude of the gain at 100Hz to 120Hz is about -18dB, therefore the double line
frequency ripple is attenuated. The parameters are designed to maintain the stability for the single
stage PFC system.
Figure 21: Bode Plot of Compensation Network at Secondary Side
In order to decrease the time for the transconductance error amplifier at the secondary to quit the
saturation process and reduce the output voltage overshoot at startup, a Zener diode is require d.
The zener diode is connected between the error amplifier output terminal to ground. This reduces
the overshoot and improves the startup performance, because the zene r provides a bias current
before the transconductance error amplifier sinks current. Because of the tolerance of the
opto-coupler CTR, the output vol tage of the error amplifi er unde r a steady state should not become
too low so as to keep the sufficient output regulation capability.
In the 20V/90W reference design, a 6.8V Zener is selected and output of the error amplifier is set as
about 5 to 6 volts under steady state. The output voltage of the transco nductance error amplifier is
around one third of the rated output voltage under steady state.
10
-4
10
-2
10
0
10
2
10
4
10
6
-50
0
50
100
Frequency (Hz)
magnitude (db)
10
-4
10
-2
10
0
10
2
10
4
10
6
-100
-80
-60
-40
-20
0
Frequency (Hz)
Phase (degree)
Design and Applications Information
Isolated Voltage Loo p and Output Voltage Feedback on FB Pin
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 33
5.2.3 RS2 and Rf1 Design
The RS2 and Rf1 design is mainly based on the opto-couplers current transfer ratio(CTR) Which
should be around 100% to 200%. RS2 is designed to produce around 1mA current at the LED side
of the opto-coupler. Rf1 is designed to produce 2.5V feedback voltage to close the loop under a
stead state. If Rf1 is designed at 1.24kΩ, the current at transistor side of the opto-coupler should be
designed at 2mA (typical). This should have enough signal to noise ratio in the practical design. The
feedback resistor (Rf1) should be kept close to the opto-coupler to avoid noise in the layout.
The output of PFC Flyback has double line frequency ripple voltage. At the steady state operation
condition, the FB pin voltage transferred from secondary side also has this double line frequency
ripple voltage. The ripple voltage amplitude on the FB pin is determined by the output voltage ripple
amplitude and the gain from the output voltage to the FB pin (referred in the previous sectio n
Section 5.2.2, Compensation Network Design, on page 31). It is noticed that there is an attenuated
ripple appearing at the outpu t of the amplifier with the minus phase shift from the output voltage
ripple. Therefore, the ratio of ripple voltage amplitude over the DC voltage value of FB pin is bigger
than the ratio of output ripple over DC output voltage. If the output ripple voltage is too big in certain
applications, the FB pin voltage peak value might trigge r the internal FB OVP threshold, which is
about 7% on the top of the reference value. This will heavily distort the input current waveform and
disturb the stability of the system. In order to solve this issue, it is recommended to use a constant
offset voltage circuit, as show in Figure 22. This circuit consists of a diode (ZD1), and two resistors
(Rf2 and Rf3). This will provide a bias current from the bias winding so as to produce a bias voltage
on the FB pin. Therefore, the ripple voltage amplitude of the FB pin is decreased below the FB OVP
threshold. In the 90W reference design, the winding bias voltage provides 1mA (typical) offset
current to the FB pin and the ripple voltage amplitude on the FB pin ca n decrease to be around half
of that with this bias circuit. Rf2 can be calculated by equation (10), in which VFB is 2.5V reference
voltage.
If the cathode voltage VZD1 is 9.1V, Rf2 is calculated as 6.8kΩ⋅
Equation (10)
Figure 22: Bias Current for Offset Voltage on FB Pin
VZD1VFB
–
Rf2
----------------------------1mA=
FB
OCP
88EM8040
/8041
VDD Opto- Coupler
VOut
VIN
ISNS
SW SGND
R
f1
R
S2
R
S3
R
S4
R
S5
C
S1
C
S2
C
VDD
V
ref
PGND
C
VCC
R
f3
R
f2
Z
D1
C
vout
V
ZD1
+
–
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 34 Document Classification: Proprietary October 5, 2009, Preliminary
5.3 Current Sensing and Over Current Protection
5.3.1 Current Sensing Through ISNS Pin
The voltage drop on the current sense resistor should be kept very small in order to reduce the
power consumption on the sense resistor. In flyback topology, the drain to source current flows
through the transformer , MOSFET and current sense resistor (Rsen). This is shown in Figure 23. The
average current mode control single stage solution requires two signals of flyback: the peak current
signal to avoid the transformer saturation including a short circuit condition, and the average current
sense signal to achieve the right PFC operation. The voltage drop (Vsen) across resistor (Rsen)
represents the flyback peak current signal. The voltage of (VCS), after RCS and CCS low pass filter,
represents the average current signal of the primary side of the flyback converter.
Figure 23: Current Sensing Circuit
The resistor (Rsen) should be designed such as the example in Table 7 where Rsen is designed for a
90W adaptor. The specification are : output power = 90W, input voltage range = 85-264V, output
voltage = 20V, output current= 4.5A, 30% margin of over current on top of the normal current.
FB
Drain
OCP
VDD
N
p
N
S2
D
R2
R
sen
VIN
ISNS SW SGND
C
cs
R
cs
D
sn
R
sn
C
sn
Q1
V
sen
V
cs
PGND
88EM8040
/8041
C
in
V
DCin
V
OUT
Design and Applications Information
Current Sensing an d Over Current Protecti on
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 35
Table 8 shows the reference value of the current sensing resistor. In the practical design, the current
sensing resistor value could be fine tuned around the value shown in the table based on the specification
and the primary inductance of the flyback transformer.
5.3.2 Average Current Signal and Over Power Limitation
To convert flyback peak current into an average current signal, an RC filter is required. Figure 24
shows how adding two more components will result in an average current signal. This average
current signal, VCS is fedback onto the ISNS pin and used to achieve a sinusoidal current waveform
by an internal current control loop. It is also used to achieve power limitation. The corner frequen cy
of the RC filter is recommended approximately 1/10~1/6 of the switchin g frequency. Rcs is
recommended as the value of 187Ω for the purpose of blocking negative and surge voltages. A
single stage PFC operates at 120kHz (typical), Ccs is designed as 47nF which results in a corner
frequency of 18kHz. The internal IC block is designed to perform the over power limitation as shown
in the electrical characteristics table. The corner frequency of the low pass filter is designed as;
Equation (11)
Table 7: Current Sensing Circuit
Input Power Pin 90W
Minimum input voltage Vinmin 85V
Maximum average input
current 1.49A
Over current threshold
Zone 1 VIOVERTH1 0.391V
Over current margin Imargin 30%
Current sensing resistor
calculation 0.2Ω
Current sensing resistor
selection Rsns 0.2Ω
Table 8: Current Sensing Resistor Selection Reference
Input Power (W) 36 72 90 120
Current Sensing Resistor (Ω) 0.40 - 0.45 0.20 - 0.27 0.15 - 0.20 0.12 - 0.15
Iinmax 2Pin
Vinmin
---------------
×=
Rsns VIOVERTH1
iinmax 1Iminarg
+()×
----------------------------------------------------
=
fcorner 1
2πRcsCcs
-----------------------
=
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 36 Document Classification: Proprietary October 5, 2009, Preliminary
5.3.3 Cycle by Cycle Current Protection through OCP Pin
In order to get the cycle by cycle current protection to avoid the transformer saturation, a circuit with
a low base to emitter parasitic capacit ance NPN transistor is recommended in the design, as shown
in Figure 24. The sensing voltage through Rsen should trigger and turn on the transistor of Q2 during
the over current condition. Q2 then pulls the OCP pin to low and turns off the gate signal to the
external MOSFET. In order to get proper protection, a -2mV/°C (typical) temperature coefficient of
(Vbe) should be considered. The lowest voltage (Vbe) will be set to the junction temperature of 80°C.
Figure 24: Current Sensing and Cycle by Cycle Over Current Protection Circuit
Figure 25: Current Sensing and Cycle by Cycle Over Current Protection Waveforms
FB
Drain
OCP
VDD
N
p
N
S2
D
R2
R
sen
VIN
C
sen
ISNS SW SGND
C
cs
R
cs
D
sn
R
sn
C
sn
Q1
V
sen
V
cs
R
1
R
2
Q2
88EM8040
/8041
V
OUT
C
in
V
DCin
sen
V
LEB
(Leading Edge
current)
avg
cs
V
avg
sen
V
GND
D
OCP
Power limit
OCP
cs
V
D
sen
V
avg
sen
V
avg
cs
V
cs
V
Design and Applications Information
Current Sensing an d Over Current Protecti on
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 37
Equation (12)
The highest Vbe voltage will be set to the junction temperature of -25°C.
Equation (13)
The voltage Vbe is supposed to have some tolerance margin to select the resistor of Rsen without
any unpredicted cycle by cycle over current protection. The recommended equation is:
Equation (14)
The minimum saturation current poi nt of Ilim for the transformer should satisfy:
Equation (15)
Ilim should have enough margins considering transformer saturation condition at lower ambie nt
temperature.
R1 and R2 should be selected properly in Figure 24, in order to make the cycle by cycle current
limiting work correctly. R1 and R2 act as voltage dividers to setup the right current limitation
threshold. Actually R2 also works as controlling base current of that transistor, the same time, R1
works to discharge the parasitic capacitance of that transistor . In the practical design, the R1 and R2
need to choose properly based on the power rating of the system. The value of R1 is recommended
as 500~2KΩ and R2 as 500~2kΩ.
Please note that a small value of the capacitor parallel with the Rsns resistor is very helpful to filter
the noise in order to guarantee this OCP circuit to function properly. When the MOSFET turns on,
external COSS of the MOSFET starts discharging. This causes switching loss increases and makes
the leading edge current. Figure 25 show s that this current creates unwanted over current making
the system not function properly. This phenomenon can be avoided by ad ding one capacitor Csen.
The leading edge current timi ng is less than 300nS (typical). Csen can be calculated as;
Equation (16)
Csen is recommended to have a value of 0.22μF/25V.
Vbe 0.65V2mV 80 25–()×–≅0.54V=
Vbe 0.65V2mV 25–25–()×–≅0.75V=
Rsen 0.50V
Idspeak
----------------
≤
Ilim 0.75V
Rsen
--------------
=
fsen 1
2πRsenCsen
---------------------------- 1MHz≈=
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 38 Document Classification: Proprietary October 5, 2009, Preliminary
5.3.4 Peak Current and Average Current Relationship
The relationship between the flyback peak and the average current signals are described in the
following equation. Figure 25 explains this in detail.
Current sensing signal across Rsen resistor is calculated as
Equation (17)
The average current sensing signal during MOSFET switching on is
Equation (18)
The switching frequency peak to peak ripp le is
Equation (19)
The average current sensing signal during the whole switching cycle is
Equation (20)
Vsen Rsen Ids
×=
Vsenavg Vsen Rsen
ΔIins
2
------------
–=
ΔIins Vline D⋅
Lmfs
⋅
--------------------
=
Vcsavg Vsenavg D×=
Design and Applications Information
SW Pin to MOSFET Gate
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 39
5.4 SW Pin to MOSFET Gate
The 88EM8040/88EM8041 provides a maximum 2A drive current, which is the strongest driver
capability in comparison with the other similar part on the market. A default resistor of 10Ω is
designed to go between the SW pin and the gate of the external MOSFET. The gate driver loop is
subject to fast rise and the layout trace should be kept as short as possible in order to minimize th e
parasitic inductance, as shown in Figure 26.
Figure 26: SW Pin Layout Guidelines
5.5 VDD, Signal Ground (SGND) and Power Ground
(PGND)
VDD is the IC power supply pin. It has a typical input voltage value of 12V and a maximum operating
voltage of 16V. A Zener clamp circuit of 16V is recommended in order to guarantee that the voltage
on VDD will not go any higher than 16V. The IC begins to function when VDD powers on at 12V.
Once the IC powers on, it keeps functioning as long as the VDD is higher than VDD_UVLO, which is
7V (typical). In a practical design, an electrolytic capacitor 220μF (typical) is recommended to
connect between VDD and gro und in order to retain the IC functionality during startup. That
capacitor will need to keep the VDD higher than 7V before the bias transformer winding takes over
and provides enough energy for the power IC.
A 0.01-0.1μF ceramic capacitor is strongly recommended to be placed between the VDD and IC
ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the
noise to VDD and clamping the VDD voltage during the switching of the internal driver circuit.
SGND is directly connected to the system ground by a Kelvin connection trace. The system ground
is the source of the MOSFET, as shown in Figure 27. PGND connects to the system ground
separately and can not share the same trace with SGND. This is due to pulse current on PGND
while driving the external MOSF ET on and off. This pulse current produces pulse voltage drops on
the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the
same trace.
FB
Drain
OCP
VDD
N
p
N
S2
D
R2
Rgate
VIN
ISNS SW SGND
D
sn
R
sn
C
sn
Q1
PGND
Keep this trace as short
as poss ible in lay out
88EM8040
/8041
V
DCin
V
OUT
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 40 Document Classification: Proprietary October 5, 2009, Preliminary
Figure 27: VDD Decoupling Capacitor and Ground Layout Guidelines
FB
Drain
OCP
VDD
NpNS2
DR2
Rgate
VIN
ISNS SW SGND
Dsn
Rsn
Csn
Q1
PGND K eep t hi s t race ri ght bes i de
I C and as short as possibl e
C
Us i ng Kel v in s ensi ng connect i on for
SGND with separate trac e from PGND
88EM8040
/8041
VDCin VOUT
Design and Applications Information
90W/20V Signal Stage PFC Adaptor Schema tic and Bill of Materials (BOM)
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 41
5.6 90W/20V Signal Stage PFC Adaptor Schematic and
Bill of Materials (BOM)
Figure 28: 90W/20V Single Stage PFC Adaptor Schematic
+
C208
0.1uF
Q107
BCX54
R220
IC200
TSM1014
Vref
1
Cc-
2
VCC
8
Cvout
5
GND
6
Ccout
7
Cv-
4
Cc+
3
VARA1
240V LF1
10MH
FS1
4A250V
ZD107
18V
+
D120
US1J
IC101
88EM8041
PGND
1
SGND
2
SW
8
FB
5
SDI/FSET
6
VDD
7
VIN
4
ISNS
3
U200B
LTV817B
4
3
T101A
250uH
9
25
6
D200
VF40120C
2
1
3
D201
VF40120C
21
3
ZD105
6.2V
U200A
LTV817B
D220
ES1002FL
-
+
BD1
GBL406
1
2
3
4
D103
US1D
Q101
IPB60R199
Q108
MMBT-
4403
ZD101
18V
+
J1
Socket
N
L
t
t
D202
1N4148
R221
T101B
D104
1N4148
C210
0.1uF
R200
15K
ZD106
15V
LF2
50MH
C101
0.68uF
STD1NK60
Q102
CY1
1nF
GTD1
501
1
1
2
2
Q103
2N7002
VO+
Q105
MMBT4401
CX1
0.47uF
Q106
MMBT4403
3
1
2
R301
9.1M
VO-
Q109
MMBT-
4401
+
D101
1N4148
ZD102
9.1V
2
1
C207
10nF
R201
1K
C209
0.1uF
R204
1.5K
R203
30K
R202
1K
RS200
0.01
C206
0.1uF
C204
2700uF
C203
2700uF
C202
2700uF
C201
2700uF
C220
1nF
R126
100K
R125
100K
C120
4.7nF R124
100K
R123
100K
R133
1M
R134
820K
R103
5.1
R105
5.1
R135
820K
R119
1.1K
NTC1
10K R118
360
R101
0.15
R104
187
R102
10K
C212
4.7uF
C211
0.1uF
R209
2K
ZD201
6.8V
R206
11K
R207
2K R208
2K
C106
0.22uF
C102
47nF
L101
50uH
R106B
620K
R106A
620K
R132
100K R106C
620K
R108
18K
C103
220pF
R109
300K
R122
12K
R128
12K
R127
12K R110
300
R111
1.21K R112
5.1K
ZD104
0.1uF
C104
0.1uF
C105
1uF
R116
2K
R107
802
NTC2
100k
R130B
2.5M
R130C
2.5M
R130
2.5M
R302
9.1M R303
9.1M R304
9.1M R305
9.1M
R120
20K C110
0.1uF
R129
1K
C107
0.1uF
C108
470uF
R117
1.1K R115
5.1K
C109
100uF
R114
5.1K
10
10
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 42 Document Classification: Proprietary October 5, 2009, Preliminary
THIS PAGE INTENTIONALLY LEFT BLANK
Mechanical Drawings
Mechanical Drawings
Copyright © 2009 Marvell Doc. No. MV-S104983-01 Rev. A
October 5, 2009, Preliminary Document Classification: Proprietary Page 43
6Mechanical Drawings
6.1 Mechanical Drawings
Figure 29: 8-Lead SOIC Mechanical Drawing
Notes:
All dimensions in mm.
See Section 7, Part Order Numbering/Package Marking, on page 45 for package marking and pin 1
location.
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 44 Document Classification: Proprietary October 5, 2009, Preliminary
THIS PAGE INTENTIONALLY LEFT BLANK
Part Order Numbering/Package Mark ing
Part Order Numbering
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 45
7Part Order Numbering/Package Marking
7.1 Part Order Numbering
Figure 30 shows the part order numbering scheme. For complete ordering information, contact your
Marvell FAE or sales representative.
The standard ordering part number for the respective solution is shown in Table 9.
Figure 30: 88EM8040/88EM8041 Sample Ordering Part Num ber
xx–SAG2C000–xxxx
Part number
Package code
Environmental code
2 = Green Halogen Free
Temperature code
C = Commercial
Custom code (optional)
88EM804X
Custom code
Custom code
Custom code
Table 9: 88EM8040/88EM8041 Part Order Options1
1. Please note that the 88EM8040 device is 60kHz and the 88EM8041 device is 120kHz.
Package Type Part Order Number
8-Pin SOIC 88EM8040xx-SAG2C000
8-Pin SOIC 88EM8040xx-SAG2C000-T (Tape and Reel)
8-Pin SOIC 88EM8041xx-SAG2C000
8-Pin SOIC 88EM8041xx-SAG2C000-T (Tape and Reel)
88EM8040/88EM8041
Datasheet
Doc. No. MV-S104983-01 Rev. A Copyright © 2009 Marvell
Page 46 Document Classification: Proprietary October 5, 2009, Preliminary
7.2 Package Markings
Figure 31 shows a typical package marking and pin 1 location.
Figure 31: 88EM8040/88EM8041 Packa ge Marking
MRVL
804X
YWWG
Marvell company abbreviation
Date code and assembly house code
Y = last digit of year
WW = work week
G = assembly house code
Abbreviated part nu mber
XXXX = 4 character abbreviated part number
Note: The above example is not drawn to scale. Location of markings are approximate.
Pin 1 location
Copyright © 2009 Marvell Doc. No. MV-S104983 -01 Rev. A
October 5, 2009, Prelimin ary Documen t Classification: Propriet ary Page 47
ARevision History
Table 10: Revisio n History
Document Type Document Revision
Release 8040/41 Rev. A
• Revised EC tabl e with new values.
• Reworked Application and Design Section
• Revised Mechanical Drawing
• Updated Part Ordering
Release 8041 Rev. –
First Release
