Semiconductor Components Industries, LLC, 2004
October, 2004 − Rev. 3 1Publication Order Number:
NTP60N06/D
NTP60N06, NTB60N06
Power MOSFET
60 V, 60 A, N−Channel
TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
•Pb−Free Packages are Available
Typical Applications
•Power Supplies
•Converters
•Power Motor Controls
•Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 60 Vdc
Drain−to−Gate Voltage (RGS = 10 M) VDGR 60 Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp10 ms) VGS
VGS 20
30
Vdc
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp10 s)
ID
ID
IDM
60
42.3
180
Adc
Apk
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
PD150
1.0
2.4
W
W/°C
W
Operating and Storage Temperature Range TJ, Tstg −55 to
+175 °C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, L = 0.3 mH
IL(pk) = 55 A, VDS = 60 Vdc)
EAS 454 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1) RJC
RJA 1.0
62.5
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds TL260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
60 VOLTS, 60 AMPERES
RDS(on) = 14 m
N−Channel
D
S
G
TO−220
CASE 221A
STYLE 5
123
4
NTx60N06 = Device Code
x = P or B
A = Assembly Location
Y = Year
WW = Work Week
NTx60N06
AYWW
1
Gate 3
Source
4
Drain
2
Drain
NTx60N06
AYWW
1
Gate 3
Source
4
Drain
2
Drain
D2PAK
CASE 418B
STYLE 2
2
3
4
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS 60
−72.3
69.8 −
−
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS −
−−
−1.0
10
Adc
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS − − ±100 nAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th) 2.0
−2.85
8.0 4.0
−
Vdc
mV/°C
Static Drain−to−Source On−Resistance (Note 2)
(VGS = 10 Vdc, ID = 30 Adc) RDS(on) − 11.5 14 m
Static Drain−to−Source On−Voltage (Note 2)
(VGS = 10 Vdc, ID = 60 Adc)
(VGS = 10 Vdc, ID = 30 Adc, TJ = 150°C)
VDS(on) −
−0.715
1.43 1.01
−
Vdc
Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc) gFS − 35 − mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V 25 Vd V 0Vd
Ciss − 2300 3220 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz
)
Coss − 660 925
Transfer Capacitance
f
=
1
.
0
MHz)
Crss − 144 300
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(on) − 25.5 50 ns
Rise Time (VDD = 30 Vdc, ID = 60 Adc, tr− 180.7 360
Turn−Off Delay Time
(VDD
30
Vdc
,
ID
60
Adc
,
VGS = 10 Vdc, RG = 9.1 ) (Note 2) td(off) − 94.5 200
Fall Time tf− 142.5 300
Gate Charge
(V 48 Vd I 60 Ad
QT− 62 81 nC
(VDS = 48 Vdc, ID = 60 Adc,
V
GS
= 10 Vdc
)
(
Note 2
)
Q1− 10.8 −
VGS
=
10
Vdc)
(Note
2)
Q2− 29.4 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (IS = 60 Adc, VGS = 0 Vdc) (Note 2)
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) VSD −
−0.99
0.87 1.05
−Vdc
Reverse Recovery Time
(I 60 Ad V 0Vd
trr − 64.9 − ns
(IS = 60 Adc, VGS = 0 Vdc,
dI
S
/dt = 100 A/
s
)
(
Note 2
)
ta− 44.1 −
dIS/dt
=
100
A/s)
(Note
2)
tb− 20.8 −
Reverse Recovery Stored Charge QRR − 0.146 − C
2. Pulse Test: Pulse Width ≤300 s, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
NTP60N06, NTB60N06
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0.026
0.022
0.018
0.01
40200
0.006 12060
0.014 TJ = 25°C
TJ = −55°C
TJ = 100°C
VGS = 15 V
80 100
ID, DRAIN CURRENT (AMPS)
VGS = 10 V
Figure 1. On−Region Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
120
60
40
20
53210
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 86543
120
60
40
20
0
0
Figure 3. On−Resistance versus Gate−to−Source
Voltage
ID, DRAIN CURRENT (AMPS)
0.026
0.022
0.018
0.01
40200
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
0
0.006
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
2.2
2
1.8
1.6
1.4
1.2
1
0.8
1751251007550250−25−50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
1000
100
10
0.6
10,000
Figure 6. Drain−to−Source Leakage Current
versus Voltage
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
12060
0.014
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
IDSS, LEAKAGE (nA)
20 60
4
30 40 50
4.5 V
5 V
5.5 V
7 V
6 V
9 V
8 V
TJ = 25°C
TJ = −55°C
TJ = 100°C
VDS ≥ 10 V
TJ = 25°C
TJ = −55°C
TJ = 100°C
VDS = 10 V
ID = 30 A
VGS = 10 V TJ = 150°C
VGS = 0 V
TJ = 100°C
80
100
80
100
7
80 100
150
TJ = 125°C
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−of f delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t d(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is a ffected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
0
C, CAPACITANCE (pF)
510
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
VGS VDS
VGS = 0 VVDS = 0 V TJ = 25°C
Crss
Ciss
Coss
Crss Ciss
0 5 10 15 2520
800
1600
2400
3200
4000
4800
5600
6400
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5
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
60
00.960.4
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE ()
1 10 100
1000
10
VDS = 30 V
ID = 60 A
VGS = 10 V
VGS = 0 V
TJ = 25°C
Figure 10. Diode Forward Voltage versus Current
0
10
6
2
0
QG, TOTAL GATE CHARGE (nC)
12
8
4
20 7040
100
10 5030 60
0.48 0.56 0.64 0.72 0.8 0.88
20
30
50
10
40
ID = 60 A
TJ = 25°C
VGS
Q2
Q1
QT
tr
td(off)
td(on)
tf
TJ = 150°C
TJ = 25°C
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry c ustom.
The energy rating must be derated for temperature as shown
in the accompanying g raph ( Figure 12). M aximum e ner gy a t
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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6
SAFE OPERATING AREA
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
t, TIME (s)
0.1
1.0
0.01
0.1
0.2
0.02
D = 0.5
0.05
0.01
SINGLE PULSE
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
1.0 100.10.010.0010.00010.00001
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1 1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1000
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
25 50 75 100 125
100
ID = 55 A
10
10 175
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
300
500
100
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
1 ms
100 s
10 ms dc
10 s
150
200
400
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ORDERING INFORMATION
Device Package Shipping†
NTP60N06 TO−220 50 Units/Rail
NTP60N06G TO−220
(Pb−Free) 50 Units/Rail
NTB60N06 D2PAK 50 Units/Rail
NTB60N06G D2PAK
(Pb−Free) 50 Units/Rail
NTB60N06T4 D2PAK 800 Tape & Reel
NTB60N06T4G D2PAK
(Pb−Free) 800 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
PACKAGE DIMENSIONS
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.570 0.620 14.48 15.75
B0.380 0.405 9.66 10.28
C0.160 0.190 4.07 4.82
D0.025 0.035 0.64 0.88
F0.142 0.147 3.61 3.73
G0.095 0.105 2.42 2.66
H0.110 0.155 2.80 3.93
J0.018 0.025 0.46 0.64
K0.500 0.562 12.70 14.27
L0.045 0.060 1.15 1.52
N0.190 0.210 4.83 5.33
Q0.100 0.120 2.54 3.04
R0.080 0.110 2.04 2.79
S0.045 0.055 1.15 1.39
T0.235 0.255 5.97 6.47
U0.000 0.050 0.00 1.27
V0.045 −−− 1.15 −−−
Z−−− 0.080 −−− 2.04
B
Q
H
Z
L
V
G
N
A
K
F
123
4
D
SEATING
PLANE
−T−
C
S
T
U
R
J
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9
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
17.02
0.67
10.66
0.42
3.05
0.12
5.08
0.20
mm
inches
SCALE 3:1
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SEATING
PLANE
S
G
D
−T−
M
0.13 (0.005) T
231
4
3 PL
K
J
H
V
E
C
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.340 0.380 8.64 9.65
B0.380 0.405 9.65 10.29
C0.160 0.190 4.06 4.83
D0.020 0.035 0.51 0.89
E0.045 0.055 1.14 1.40
G0.100 BSC 2.54 BSC
H0.080 0.110 2.03 2.79
J0.018 0.025 0.46 0.64
K0.090 0.110 2.29 2.79
S0.575 0.625 14.60 15.88
V0.045 0.055 1.14 1.40
−B−
M
B
W
W
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
F0.310 0.350 7.87 8.89
L0.052 0.072 1.32 1.83
M0.280 0.320 7.11 8.13
N0.197 REF 5.00 REF
P0.079 REF 2.00 REF
R0.039 REF 0.99 REF
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