LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input 1.0 General Description 3.0 Features The LMK00105 is a high performance, low noise LVCMOS fanout buffer which can distribute 5 ultra-low jitter clocks from a differential, single ended, or crystal input. The LMK00105 supports synchronous output enable for glitch free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming. 5 LVCMOS Outputs, DC to 200 MHz Universal Input 2.0 Target Applications LO Reference Distribution for RRU Applications SONET, Ethernet, Fibre Channel Line Cards Optical Transport Networks GPON OLT/ONU Server and Storage Area Networking Medical Imaging Portable Test and Measurement High-end A/V -- LVPECL -- LVDS -- HCSL -- SSTL -- LVCMOS / LVTTL Crystal Oscillator Interface -- Crystal Input Frequency: 10 to 40 MHz Output Skew: 6 ps Additive Phase Jitter -- 30 fs at 156.25 MHz (12 kHz to 20 MHz) Low Propagation Delay Operates with 3.3 or 2.5 V Core Supply Voltage Adjustable Output Power Supply -- 1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank 24 pin LLP package (4.0 x 4.0 x 0.8 mm) 4.0 Functional Block Diagram 30180701 TRI-STATE(R) is a registered trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 301807 SNAS579A Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 5.0 Connection Diagram 24-Pin LLP Package 30180702 6.0 Pin Descriptions Pin # Pin Name Type DAP DAP - Description The DAP should be grounded 2, 6 Vddo Power Power Supply for Bank A (CLKout0 and CLKout 1) CLKout pins. 3 CLKout0 Output LVCMOS Output 1,4,7,11,12, 16,19 GND GND 5 CLKout1 Output LVCMOS Output 8,23 Vdd Power Supply for operating core and input buffer 9 OSCin Input 10 OSCout Output Output for Crystal Ground Input for Crystal 13 CLKout2 Output LVCMOS Output 14,18 Vddo Power Power Supply for Bank B (CLKout2 to CLKout 4) CLKout pins 15 CLKout3 Output LVCMOS Output 17 CLKout4 Output LVCMOS Output 20 CLKin* Input Optional complimentary input pin 21 CLKin Input Input Pin 22 SEL Input Input Clock Selection. This pin has an internal pull-down resistor. (Note 1) 24 OE Input Output Enable. This pin has an internal pull-down resistor. (Note 1) Note 1: CMOS control input with internal pull-down resistor. 2 Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 7.0 Absolute Maximum Ratings (Note 2, Note 3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Parameter Core Supply Voltage Output Supply Voltage Input Voltage Symbol Vdd Vddo VIN Ratings -0.3 to 3.6 -0.3 to 3.6 Units V V -0.3 to Vdd + 0.3 V Storage Temperature Range TSTG -65 to 150 C Lead Temperature (solder 4 s) TL +260 C Junction Temperature TJ +125 C 8.0 Recommended Operating Conditions Symbol TA Min Typ Max Units Ambient Temperature Parameter -40 25 85 C Core Supply Voltage Output Supply Voltage (Note 4) Vdd Vddo 2.375 1.425 3.3 3.3 3.45 Vdd V V Note 2: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 3: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV. Note 4: Vddo should be less than or equal to Vdd, (Vddo Vdd) 9.0 Package Thermal Resistance 24-Lead LLP Package Symbols Ratings Units Thermal resistance from junction to ambient on 4-layer Jedec board (Note 5) JA 54 C/W Thermal resistance from junction to case (Note 6) JC (DAP) 20 C/W Note 5: Specification assumes 5 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias play a key role in improving the thermal performance of the LLP. For best thermal dissipation it is recommended that the maximum number of vias be used on the board layout. Note 6: Case is defined as the DAP (die attach pad). Copyright (c) 1999-2012, Texas Instruments Incorporated 3 LMK00105 10.0 Electrical Characteristics (2.375 V Vdd 3.45 V, 1.425 Vddo Vdd, -40 C TA 85 C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, TA = 25 C, at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 unless otherwise stated. Symbol Parameter Test Conditions Min Typ Max Units Total Device Characteristics Vdd Core Supply Voltage 2.375 2.5 or 3.3 3.465 V Vddo Output Supply Voltage 1.425 1.5,1.8, 2.5, or 3.3 Vdd V No CLKin 16 25 Vddo = 3.3 V, Ftest = 100 MHz 24 Vddo = 2.5 V, Ftest = 100 MHz 20 Vddo = 2.5 V, OE = High, Ftest = 100 MHz, CL = 10pF 5 IVdd Core Current IVddo[n] Current for Each Output Vddo= 3.3 V, OE = High, Ftest = 100 MHz, CL = 10pF 7 OE = Low 0.1 IVdd + IVddo Total Device Current with Loads on all outputs OE = High @ 100 MHz 59 OE = Low 16 mA mA mA Power Supply Ripple Rejection (PSRR) PSRR Ripple Induced Phase Spur Level 100 kHz, 100 mVpp Ripple Injected on Vdd, Vddo = 2.5 V -44 dBc Outputs (Note 7) Skew Output Skew tPD Propagation Delay CLKin to CLKout (Note 9) tPD, PP fCLKout tRise VCLKoutLow Part-to-part Skew (Note 8, Note 9) Measured between outputs, referenced to CLKout0 6 CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V 1 ns CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 1.4 ns 750 ps CL = 5 pF, RL = 50 Vdd = 2.5 V; Vddo = 1.5 V 1.1 ns 200 MHz DC Vdd = 3.3 V, Vddo = 1.8 V, CL = 10 pF 500 Vdd = 2.5 V, Vddo = 2.5 V, CL = 10 pF 300 Vdd = 3.3 V, Vddo = 3.3 V, CL = 10 pF 200 Output Low Voltage VCLKoutHigh Output High Voltage RCLKout Output Resistance ps CL = 5 pF, RL = 50 Vdd = 3.3 V; Vddo = 3.3 V Output Frequency (Note 10) Rise/Fall Time 25 ps 0.1 V Vddo0.1 50 ohm 30 fs fCLKout = 156.25 MHz, tj 4 RMS Additive Jitter CMOS input slew rate 2 V/ns CL = 5 pF, BW = 12 kHz to 20 MHz, Differential Input Mode Only Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 Symbol Parameter VLow Input Low Voltage Test Conditions Min Typ Max Units Digital Inputs (OE, SEL0, SEL1) Vdd = 2.5 V 0.4 Vdd = 2.5 V 1.3 Vdd = 3.3 V 1.6 VHigh Input High Voltage IIH High Level Input Current IIL Low Level Input Current IIH High Level Input Current VCLKin = Vdd IIL Low Level Input Current (Note 11) VCLKin = 0 V VIH Input High Voltage VIL Input Low Voltage V 50 -5 5 uA CLKin/CLKin* Input Clock Specifications, (Note 12, Note 13) VCM VID -20 uA uA Vdd GND V VID = 150 mV 0.5 Vdd1.2 VID = 350 mV 0.5 Vdd1.1 VID = 800 mV 0.5 Vdd0.9 CLKin driven differentially 0.15 1.5 V DC 200 MHz 10 40 MHz Differential Input Common Mode Input Voltage (Note 15) Differential Input Voltage Swing 20 V OSCin/OSCout Pins fOSCin Input Frequency (Note 10) Single-Ended Input, OSCout floating fXTAL Crystal Frequency Input Range ESR < 200 ( fXtal 30 MHz ) COSCin Shunt Capacitance VIH Input High Voltage Fundamental Mode Crystal ESR < 120 ( fXtal > 30 MHz ) (Note 14, Note 10) 1 Single-Ended Input, OSCout floating pF 2.5 V Note 7: AC Parameters for CMOS are dependent upon output capacitive loading Note 8: Part-to-part skew is calculated as the difference between the fastest and slowest tPD across multiple devices. Note 9: Guaranteed by design. Note 10: Guaranteed by characterization. Note 11: VIL should not go below -0.3 volts. Note 12: See Section 12.1 Differential Voltage Measurement Terminology for definition of VOD and VID. Note 13: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information. Note 14: The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal. Note 15: When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled. Copyright (c) 1999-2012, Texas Instruments Incorporated 5 LMK00105 11.0 Typical Performance Characteristics Unless otherwise specified: Vdd = Vddo = 3.3 V, TA = 20 C, CL = 5 pF, CLKin driven differentially, input slew rate 2 V/ns. RMS Jitter vs. CLKin Slew Rate @ 100 MHz -40 C 25 C 85 C CLKin Source 450 RMS JITTER (fs) 400 -140 Fclk-100 MHz Int. BW=1-20 MHz NOISE FLOOR (dBc/Hz) 500 Noise Floor vs. CLKin Slew Rate @ 100 MHz 350 300 250 200 150 100 50 0 -40 C 25 C 85 C CLKin Source -145 Fclk=100 MHz Foffset=20 MHz -150 -155 -160 -165 -170 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL INPUT SLEW RATE (V/ns) 30180741 LVCMOS Phase Noise @ 100 MHz 30180774 LVCMOS Output Swing vs. Frequency OUTPUT SWING (V) 3.5 3.0 Vddo=1.5 V Vddo=1.8 V Vddo=2.5 V Vddo=3.3 V 2.5 Rterm=50 2.0 1.5 1.0 0.5 0.0 0 30180742 Note 16: Test conditions: LVCMOS Input, slew rate 2 V/ns, CL = 5 pF in parallel with 50 , BW = 1 MHz to 20 MHz 200 400 600 800 FREQUENCY (MHz) 1000 30180775 Iddo per Output vs Frequency CURRENT (mA) 15 Vddo = 1.5 V Vddo = 1.8 V Vddo = 2.5 V Vddo = 3.3 V Cload = 10 pF 10 5 0 0 50 100 150 200 FREQUENCY (MHz) 250 30180776 6 Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 12.0 Measurement Definitions 12.1 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first section Figure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitions side-byside for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined in volts (V) and VSS is often defined as volts peak-to-peak (VPP). 30180712 FIGURE 1. Two Different Definitions for Differential Input Signals 30180713 FIGURE 2. Two Different Definitions for Differential Output Signals Copyright (c) 1999-2012, Texas Instruments Incorporated 7 LMK00105 13.0 Functional Description The LMK00105 is a 5 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz. It features a 2:1 input multiplexer with a crystal oscillator input, single supply or dual supply (lower power) operation, and pin-programmable device configuration. The device is offered in a 24-pin LLP package. 13.1 Vdd and Vddo Power Supplies (Note 17, Note 18) Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply (3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. Bank A (CLKout0 and CLKout1) and Bank B (CLKout2 to CLKout4) may also be operated at different Vddo voltages, provided neither Vddo voltage exceeds Vdd. Note 17: Care should be taken to ensure the Vddo voltage does not exceed the Vdd voltage to prevent turning-on the internal ESD protection circuitry. Note 18: DO NOT DISCONNECT OR GROUND ANY OF THE Vddo PINS as the Vddo pins are internally connected within an output bank. 13.2 CLOCK INPUT The LMK00105 has one differential input, CLKin/CLKin* and OSCin, that can be driven in different manners that are described in the following sections. 13.2.1 SELECTION OF CLOCK INPUT Clock input selection is controlled using the SEL pin as shown in Table 1. Refer to Section 14.1 Driving the Clock Inputs for clock input requirements. When CLKin is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator will start-up and its clock will be distributed to all outputs. TABLE 1. Input Selection SEL Input 0 CLKin, CLKin* 1 OSCin (Crystal Mode) 13.2.1.1 CLKin/CLKin* Pins The LMK00105 has a differential input (CKLin/CLKin*) which can be driven single-ended or differentially. It can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and single ended signals that meet the input requirements in Section 10.0 Electrical Characteristics and (Note 15). Refer to Section 14.1 Driving the Clock Inputs for more details on driving the LMK00105 inputs. In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them, Table 2 will be the state of the outputs. TABLE 2. CLKin Input vs. Output States CLKin Output State Open Logic Low Logic Low Logic Low Logic High Logic High 13.2.1.2 OSCin/OSCout Pins The LMK00105 has a crystal oscillator which will be powered up when OSCin is selected. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal. Refer to Section 14.2 Crystal Interface for more information. If Crystal mode is selected and the pins do not have an AC signal applied to them, Table 3 will be the state of the outputs. If Crystal mode is selected an open state is not allowed on OSCin, as the outputs may oscillate due to the crystal oscillator circuitry. TABLE 3. OSCin Input vs. Output States 8 OSCin Output State Open Not Allowed Logic Low Logic High Logic High Logic Low Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 13.3 CLOCK OUTPUTS The LMK00105 has 5 LVCMOS outputs. 13.3.1 Output Enable Pin When the output enable pin is held High, the outputs are enabled. When it is held Low, the outputs are held in a Low state as shown in Table 4. TABLE 4. Output Enable Pin States OE Outputs Low Disabled (Hi-Z) High Enabled The OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from Low to High, the outputs will initially have an impedance of about 400 to ground until the second falling edge of the input clock and starting with the second falling edge of the input clock, the outputs will buffer the input. If the OE pin is taken from Low to High when there is no input clock present, the outputs will either go high or low and stay a that state; they will not oscillate. When the OE pin is taken from High to Low the outputs will be Low after the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising edge. 13.3.2 Using Less than Five Outputs Although the LMK00105 has 5 outputs, not all applications will require all of these. In this case, the unused outputs should be left floating with a minimum copper length (Note 19) to minimize capacitance. In this way, this output will consume minimal output current because it has no load. Note 19: For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. Copyright (c) 1999-2012, Texas Instruments Incorporated 9 LMK00105 14.0 Application Information 14.1 Driving the Clock Inputs The LMK00105 has a differential input (CLKin/CLKin*) that can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, and other differential and single ended signals that meet the input requirements specified in Section 10.0 Electrical Characteristics. The device can accept a wide range of signals due to its wide input common mode voltage range (VCM) and input voltage swing (VID)/dynamic range. AC coupling may also be employed to shift the input signal to within the VCM range. To achieve the best possible phase noise and jitter performance, it is recommended that the input to have a high slew rate of 2 V/ ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this reason, a differential input signal is recommended over single-ended because it typically provides higher slew rate and common-mode noise rejection. While it is recommended to drive CLKin with a differential signal input, it is possible to drive them with a single ended clock. The single-ended input slew rate should be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4 V. The input can be AC coupled as shown in Figure 3 which is the preferred configuration, or Figure 4, or Figure 5 depending upon the application. In these cases, the output impedance of the CMOS driver plus RS should be matched as closely as possible to the 50 termination resistor for best performance. 30180738 FIGURE 3. Preferred Configuration: Single-Ended LVCMOS Input, AC Coupling 30180743 FIGURE 4. Single-Ended LVCMOS Input, AC Coupling Near End Termination 30180744 FIGURE 5. Single-Ended LVCMOS Input, AC Coupling, Far End Temination A single ended clock may also be DC coupled to CLKin as shown in Figure 6. If the DC coupled input swing has a common mode level near the devices internal bias of 1.4 V, then only a 0.1 F bypass cap is required on CLKin*. Otherwise, if the input swing is not optimally centered near the internal bias voltage, then CLKin* should be externally biased to the midpoint voltage of the input swing. This can be achieved using external biasing resistors, RB1 and RB2, or another low-noise voltage reference. The external bias voltage should be within the specified input common voltage (VCM) range. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest. 10 Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 30180739 FIGURE 6. Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 7. Configurations similar to Figure 4 or Figure 5 could also be used as long as the OSCout pin is left floating. In these cases, the output impedance of the CMOS driver plus RS should be matched as closely as possible to the 50 termination resistor for best performance. The input clock should be AC coupled to the OSCin pin, which has an internally generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, it is recommended to use either differential input (CLKin) since it offers higher operating frequency, better common mode, improved power supply noise rejection, and greater performance over supply voltage and temperature variations. 30180703 FIGURE 7. Driving OSCin with a Single-Ended 14.2 Crystal Interface The LMK00105 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 8. 30180704 FIGURE 8. Crystal Interface The load capacitance (CL) is specific to the crystal, but usually on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the device and PCB stray capacitance (CSTRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C1 and C2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows: CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY (1) Typically, C1 = C2 for optimum symmetry, so Equation 1 can be rewritten in terms of C1only: CL = C12 / (2 * C1) + CIN + CSTRAY (2) C1 = (CL - CIN - CSTRAY) * 2 (3) Finally, solve for C1: Section 10.0 Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed Copyright (c) 1999-2012, Texas Instruments Incorporated 11 LMK00105 the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation. The power dissipated in the crystal, PXTAL, can be computed by: PXTAL = IRMS2 * RESR * (1 + C0 / CL)2 (4) Where: * IRMS is the RMS current through the crystal. * RESR is the maximum equivalent series resistance specified for the crystal. * CL is the load capacitance specified for the crystal. * C0 is the mininimum shunt capacitance specified for the crystal. IRMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active. As shown in Figure 8, an external resistor, RLIM, can be used to limit the crystal drive level if necessary. If the power dissipated in the selected crystal is higher than the drive level specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive level with RLIM shorted, then a zero value for RLIM can be used. As a starting point, a suggested value for RLIM is 1.5 k. 14.3 Power Supply Ripple Rejection In practical system applications, power supply noise (ripple) can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance. When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00105, it can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the carrier (measured in dBc). For the LMK00105, power supply ripple rejection (PSRR), was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the Vddo supply. The PSRR test setup is shown in Figure 9. 30180740 FIGURE 9. PSRR Test Setup A signal generator was used to inject a sinusoidal signal onto the Vddo supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions: * Ripple amplitude: 100 mVpp on Vddo = 2.5 V * Ripple frequency: 100 kHz Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / ( * fclk)] * 1012 (5) 14.4 Power Supply Bypassing The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very close to each supply pin. Placing the bypass capacitors on the same layer as the LMK00105 improves input sensitivity and performance. All bypass and decoupling capacitors should have short connections to the supply and ground plane through a short trace or via to minimize series inductance. 14.5 Thermal Management For reliability and performance reasons the die temperature should be limited to a maximum of 125 C. That is, as an estimate, TA (ambient temperature) plus device power consumption times JA should not exceed 125 C. 12 Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 10. More information on soldering LLP packages and gerber footprints can be obtained: http://www.national.com/en/packaging/index.html. A recommended footprint including recommended solder mask and solder paste layers can be found at: http://www.national.com/ en/packagingl/gerber.html for the SQA24A package. To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 10 should connect these top and bottom copper layers and to the ground layer. These vias act as "heat pipes" to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 30180773 FIGURE 10. Recommended Land and Via Pattern Copyright (c) 1999-2012, Texas Instruments Incorporated 13 LMK00105 15.0 Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 24 Pin LLP Package 16.0 Ordering Information Order Number Package Marking LMK00105SQX LMK00105SQ LMK00105SQE 14 Packaging 4500 Unit Tape and Reel K00105 1000 Unit Tape and Reel 250 Unit Tape and Reel Copyright (c) 1999-2012, Texas Instruments Incorporated LMK00105 Notes Copyright (c) 1999-2012, Texas Instruments Incorporated 15 Notes Copyright (c) 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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