LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 LM555 Timer Check for Samples: LM555 FEATURES DESCRIPTION * * * The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits. 1 2 * * * * * * Direct Replacement for SE555/NE555 Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty Cycle Output Can Source or Sink 200 mA Output and Supply TTL Compatible Temperature Stability Better than 0.005% per C Normally On and Normally Off Output Available in 8-pin VSSOP Package APPLICATIONS * * * * * * * Precision Timing Pulse Generation Sequential Timing Time Delay Generation Pulse Width Modulation Pulse Position Modulation Linear Ramp Generator Schematic Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com Connection Diagram Top View Figure 1. PDIP, SOIC, and VSSOP Packages These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage Power Dissipation +18V (3) LM555CM, LM555CN (4) 1180 mW LM555CMM 613 mW Operating Temperature Ranges LM555C 0C to +70C -65C to +150C Storage Temperature Range Soldering Information PDIP Package Soldering (10 Seconds) 260C Small Outline Packages (SOIC and VSSOP) (1) (2) (3) (4) 2 Vapor Phase (60 Seconds) 215C Infrared (15 Seconds) 220C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. For operating at elevated temperatures the device must be derated above 25C based on a +150C maximum junction temperature and a thermal resistance of 106C/W (PDIP), 170C/W (S0IC-8), and 204C/W (VSSOP) junction to ambient. Refer to RETS555X drawing of military LM555H and LM555J versions for specifications. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 Electrical Characteristics (1) (2) (TA = 25C, VCC = +5V to +15V, unless otherwise specified) Limits Parameter Test Conditions LM555C Min Supply Voltage Typ 4.5 Units Max 16 V VCC = 5V, RL = 3 6 VCC = 15V, RL = (Low State) (3) 10 15 1 % RA = 1k to 100k, 50 ppm/C Accuracy over Temperature 1.5 % Drift with Supply 0.1 %/V 2.25 % 150 ppm/C 3.0 % Supply Current mA Timing Error, Monostable Initial Accuracy Drift with Temperature C = 0.1F, (4) Timing Error, Astable Initial Accuracy Drift with Temperature RA, RB = 1k to 100k, C = 0.1F, (4) Accuracy over Temperature Drift with Supply 0.30 %/V Threshold Voltage 0.667 x VCC VCC = 15V 5 V VCC = 5V 1.67 V Trigger Voltage Trigger Current Reset Voltage 0.4 Reset Current Threshold Current Control Voltage Level (5) Pin 7 Sat 0.9 0.5 1 V 0.1 0.4 mA A 0.1 0.25 VCC = 15V 9 10 11 VCC = 5V 2.6 3.33 4 1 100 Pin 7 Leakage Output High A 0.5 V nA (6) Output Low VCC = 15V, I7 = 15mA 180 Output Low VCC = 4.5V, I7 = 4.5mA 80 200 mV ISINK = 10mA 0.1 0.25 V ISINK = 50mA 0.4 0.75 V ISINK = 100mA 2 2.5 V ISINK = 200mA 2.5 Output Voltage Drop (Low) mV VCC = 15V V VCC = 5V ISINK = 8mA ISINK = 5mA (1) (2) (3) (4) (5) (6) V 0.25 0.35 V All voltages are measured with respect to the ground pin, unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Supply current when output high typically 1 mA less at VCC = 5V. Tested at VCC = 5V and VCC = 15V. This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20M. No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 3 LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (2) (continued) (TA = 25C, VCC = +5V to +15V, unless otherwise specified) Limits Parameter Test Conditions LM555C Min Output Voltage Drop (High) ISOURCE = 200mA, VCC = 15V ISOURCE = 100mA, VCC = 15V 12.75 VCC = 5V 2.75 Typ Units Max 12.5 V 13.3 V 3.3 V Rise Time of Output 100 ns Fall Time of Output 100 ns 4 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 Typical Performance Characteristics Minimum Pulse Width Required for Triggering Supply Current vs. Supply Voltage Figure 2. Figure 3. High Output Voltage vs. Output Source Current Low Output Voltage vs. Output Sink Current Figure 4. Figure 5. Low Output Voltage vs. Output Sink Current Low Output Voltage vs. Output Sink Current Figure 6. Figure 7. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 5 LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 6 Output Propagation Delay vs. Voltage Level of Trigger Pulse Output Propagation Delay vs. Voltage Level of Trigger Pulse Figure 8. Figure 9. Discharge Transistor (Pin 7) Voltage vs. Sink Current Discharge Transistor (Pin 7) Voltage vs. Sink Current Figure 10. Figure 11. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 APPLICATIONS INFORMATION MONOSTABLE OPERATION In this mode of operation, the timer functions as a one-shot (Figure 12). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. Figure 12. Monostable The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 13 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. VCC = 5V TIME = 0.1 ms/DIV. RA = 9.1k C = 0.01F Top Trace: Input 5V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div. Figure 13. Monostable Waveforms During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10s before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering. Figure 14 is a nomograph for easy determination of R, C values for various time delays. NOTE In monostable operation, the trigger should be driven high before the end of timing cycle. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 7 LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com Figure 14. Time Delay ASTABLE OPERATION If the circuit is connected as shown in Figure 15 (pins 2 and 6 connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors. Figure 15. Astable In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage. Figure 16 shows the waveforms generated in this mode of operation. VCC = 5V TIME = 20s/DIV. RA = 3.9k RB = 3k C = 0.01F Top Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div. Figure 16. Astable Waveforms 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 The charge time (output high) is given by: t1 = 0.693 (RA + RB) C (1) And the discharge time (output low) by: t2 = 0.693 (RB) C (2) Thus the total period is: T = t1 + t2 = 0.693 (RA +2RB) C (3) The frequency of oscillation is: (4) Figure 17 may be used for quick determination of these RC values. The duty cycle is: (5) Figure 17. Free Running Frequency FREQUENCY DIVIDER The monostable circuit of Figure 12 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 18 shows the waveforms generated in a divide by three circuit. VCC = 5V Top Trace: Input 4V/Div. TIME = 20s/DIV. Middle Trace: Output 2V/Div. RA = 9.1k Bottom Trace: Capacitor 2V/Div. C = 0.01F Figure 18. Frequency Divider PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. Figure 19 shows the circuit, and in Figure 20 are some waveform examples. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 9 LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com Figure 19. Pulse Width Modulator VCC = 5V Top Trace: Modulation 1V/Div. TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div. RA = 9.1k C = 0.01F Figure 20. Pulse Width Modulator PULSE POSITION MODULATOR This application uses the timer connected for astable operation, as in Figure 21, with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 22 shows the waveforms generated for a triangle wave modulation signal. Figure 21. Pulse Position Modulator 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com VCC = 5V TIME = 0.1 ms/DIV. RA = 3.9k RB = 3k C = 0.01F SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 Top Trace: Modulation Input 1V/Div. Bottom Trace: Output 2V/Div. Figure 22. Pulse Position Modulator LINEAR RAMP When the pullup resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 23 shows a circuit configuration that will perform this function. Figure 23. Figure 24 shows waveforms generated by the linear ramp. The time interval is given by: (6) (7) VBE 0.6V Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 11 LM555 SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 www.ti.com VCC = 5V Top Trace: Input 3V/Div. TIME = 20s/DIV. Middle Trace: Output 5V/Div. R1 = 47k Bottom Trace: Capacitor Voltage 1V/Div. R2 = 100k RE = 2.7 k C = 0.01 F Figure 24. Linear Ramp 50% DUTY CYCLE OSCILLATOR For a 50% duty cycle, the resistors RA and RB may be connected as in Figure 25. The time period for the output high is the same as previous, t1 = 0.693 RA C. For the output low it is t2 = (8) Thus the frequency of oscillation is: (9) Figure 25. 50% Duty Cycle Oscillator Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator. ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1F in parallel with 1F electrolytic. Lower comparator storage time can be as long as 10s when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10s minimum. Delay time reset to output is 0.47s typical. Minimum reset pulse width must be 0.3s, typical. Pin 7 current switches within 30ns of the output (pin 3) voltage. 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 LM555 www.ti.com SNAS548C - FEBRUARY 2000 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: LM555 13 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM 555CM LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM LM555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI 0 to 70 Z55 LM555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 Z55 LM555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 Z55 LM555CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LM 555CM LM555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM LM555CN NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LM 555CN MC1455P1 NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN NE555V NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM555CMM VSSOP DGK 8 1000 210.0 185.0 35.0 LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM555CMX SOIC D 8 2500 367.0 367.0 35.0 LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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