Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
3A 5V 2MHz Synchronous Buck Converter
Features
• High Efficiency up to 95%
- PFM/PWM Mode Operation
• Adjustable Output Voltage from 0.8V to VIN
• Integrated 110mΩ High/Low Side MOSFET
• Programmable Switching Frequency: 300kHz to
2MHz
• Low Dropout Operation: 100% Duty Cycle
• Stable with Low ESR Capacitors
• Power-On-Reset Detection on VDD and PVDD
• Integrate Soft-Start and Soft-Off
• Over-Temperature Protection
• Over-Voltage Protection
• Under-Voltage Protection
• High/Low Side Current-Limit
• Power Good Indicator (APW7153A/B)
• Enable/Shutdown Function
• Small TDFN3x3-10 and SOP-8P Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
• LCD Minitor/TV
• Set-Top Box
• DSL, Switch HUB
• Notebook Computer
• Portable Instrument
Simplified Application Circuit
Pin Configuration
S
APW7153/A/B is a 3A synchronous buck converter with
integrated 110mΩ power MOSFETs. The APW7153/A/B
is designed with a current-mode control scheme; it can
convert wide input voltage of 2.6V to 5.5V to the output
voltage adjustable from 0.8V to 5.5V to provide excellent
output voltage regulation.
The APW7153/A/B is equipped with an PFM/PWM mode
operation. At light load, the IC operates in the PFM mode
to reduce the switching losses. At heavy load, the IC works
in PWM. At PWM mode, the switching frequency is set by
the external resistor.
The APW7153/A/B is also equipped with Power-on-reset,
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
single package.
This device, available TDFN3x3-10 and SOP-8P provides
a very compact system solution external components and
PCB area.
The pin 2 and 5 must be connected to the pin 11 (Exposed Pad)11The pin 2 and 4 must be connected to the pin 9 (Exposed Pad)9
APW7153/A/B
VDD PVDD
VIN
VOUT
LX 3
8 COMP
SHDN/RT 1
GND 2 7 FB
5 PVDD
6 VDD
SOP-8P
(Top View)
PGND 4
APW7153
9
Expose
Pad LX 3
10 COMP SHDN/RT 1
GND 2
PGND 5
9 FB
7 PVDD
8 VDD
TDFN3X3-10
(Top View)
11
Expose
Pad
LX 4 6 PVDD
APW7153
LX 3
10 COMPEN/RT 1
GND 2
PGND 5
9 FB
7 VDD
8 POK
TDFN3X3-10
(Top View)
11
Expose
Pad
LX 4 6 PVDD
APW7153A
LX 3
10 COMPSHDN/RT 1
GND 2
PGND 5
9 FB
7 VDD
8 POK
TDFN3X3-10
(Top View)
11
Expose
Pad
LX 4 6 PVDD
APW7153B
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw2
Symbol Parameter Rating Unit
VVDD, VPVDD Input Supply Voltage -0.3 ~ 6 V
>20ns pulse width
-1 ~VPVDD+0.3 V
VLX LX to GND Voltage <20ns pulse width
-3 ~VPVDD+3 V
SHDN/RT, FB, COMP, POK to GND Voltage -0.3 ~ 6 V
PGND PGND to GND Voltage -0.3 ~ +0.3 V
PD Power Dissipation Internally Limited W
TJ Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2) TDFN3x3-10
SOP-8P
50
80
oC/W
θJC Junction-to-Case Resistance in Free Air (Note 3) TDFN3x3-10
SOP-8P
10
20
oC/W
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TDFN3x3-10 and SOP-8P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-10 and SOP-8P
packages.
Package Code
QB : TDFN3x3-10 KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7153/A/B QB: APW
7153
XXXXX XXXXX - Date Code
APW7153/A/B
Handling Code
Temperature Range
Package Code
Assembly Material
APW
7153A
XXXXX
APW7153 KA: APW7153
XXXXX XXXXX - Date Code
APW
7153B
XXXXX
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw3
Recommended Operating Conditions (Note 4)
Symbol
Parameter Range Unit
VVDD Control and Driver Supply Voltage 2.6~ 5.5 V
VPVDD
Input Supply Voltage 1. 5~5.5 V
VOUT Converter Output Voltage 0.8~5.5 V
IOUT Converter Output Current 0~3 A
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Electrical Characteristics
APW7153/A/B
Symbol
Parameter Test Conditions Min. Typ. Max. Unit
SUPPLY CURRENT
IVDD VDD Supply Current VFB=1V - 460 - µA
IVDD_SDH
VDD Shutdown Supply Current SHDN/RT=VDD - - 1 µA
IVDD_SDL
VDD Shutdown Supply Current SHDN/RT=GND - - 10 µA
POWER-ON-RESET (POR)
VDD POR Voltage Threshold VIN Rising 2.3 2.4 2.5 V
VDD Debounce Time - 100 - µs
VDD POR Hysteresis 0.1 0.2 0.3 V
PVDD POR Voltage Threshold 1.5 1.6 1.7 V
PVDD POR Debounce - 10 - µs
PVDD POR Hysteresis - 50 - mV
REFERENCE VOLTAGE
APW7153/B - 0.8 -
VREF Reference Voltage Regulated on FB
pin APW7153A - 0.5 - V
TJ=25°C, IOUT=10mA, VDD=5V -0.5 - +0.5 %
Output Voltage Accuracy IOUT=10mA~3A, VDD=2.6~5V -0.8 - +0.8 %
OSCILLATOR AND DUTY CYCLE
FOSC Oscillator Frequency 0.3 - 2 MHz
Oscillator Frequency RT=332kΩ 0.8 1 1.2 MHz
Maximum Converter’s Duty - 100 - %
Minimum on Time - 90 - ns
POWER MOSFET
High Side P-MOSFET Resistance ILX=0.5A, TA=25°C - 110 160 mΩ
Low Side N-MOSFET Resistance ILX=0.5A, TA=25°C - 110 160 mΩ
High/Low Side MOSFET Leakage
Current - - 10 µA
Note 4: Refer to the typical application circuit.
Unless otherwise specified, these specifications apply over VVDD=VPVDD=3.3V, TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APW7153/A/B
Symbol
Parameter Test Conditions Min. Typ. Max. Unit
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance - 550 - µA/V
Error Amplifier DC Gain COMP=NC - 80 - dB
Current Sense Transresistance - 500 - mΩ
TD Dead Time (Note 5) - 20 - ns
PROTECTIONS
ILIM High Side MOSFET Current-Limit Peak Current 4.0 4.5 5.0 A
TOTP Over-Temperature Trip Point (Note 5) - 160 - °C
Over-Temperature Hysteresis - 50 - °C
Over-Voltage Protection Threshold 119 125 131 %VOUT
Under-Voltage Protection Threshold 44 50 56 %
Low Side MOSFET Current-Limit From Drain to Source 0.7 - 1.6 A
SOFT-START, ENABLE AND INPUT CURRENTS
Soft-Start Time 1 1.5 2 ms
VSHDN SHDN Shutdown Threshold VSHDN > SHDN s
IC shutdown - VVDD-0.9
VVDD -0.4
V
POK in from Lower
(POK Goes High) 85 87.5 90 %VOUT
POK Low Hysteresis
(POK Goes High) - 5 - %VOUT
POK in from Higher
(POK Goes High) 110 112.5 115 %VOUT
POK Threshold
POK High Hysteresis
(POK Goes Low) - 5 - %VOUT
Power Good Pull Low Resistance - 100 - Ω
Power Good Debounce - 0.5 - ms
Unless otherwise specified, these specifications apply over VVDD=VPVDD=3.3V, TA= -40 ~ 85 oC. Typical values are at TA=25oC.
Note 5: Guarantee by design.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw5
Refer to the application circuit in the section “Typical Application Circuits”, VIN=5V, TA=25oC, unless otherwise specified.
Typical Operating Characteristics
Oscillator Frequency vs. RT Resistance Efficiency vs. Output Current
Reference Voltage vs. Supply Voltage
Supply Voltage, VVDD (V)
Reference Voltage, VREF (mV)
780
785
790
795
800
805
810
815
820
22.5 33.5 44.5 55.5
No Switch Quiescent Current
vs. Supply Voltage Peak Current-Limit vs. Supply Voltage
0
1
2
3
4
5
6
2.5 33.5 44.5 55.5
Supply Voltage, VVDD (V)
Peak Current Limit, ILIM (A)
Efficiency vs. Output Current
200
250
300
350
400
450
22.5 33.5 44.5 55.5
Supply Voltage, VVDD (V)
No Switch Quiescent Current, IVDD (µA)
0.01 0.1 1 10
Output Current, IOUT (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
100
VIN=5V
VOUT=3.3V
RT=330k
50
55
60
65
70
75
80
85
90
95
100
0.01 0.1 1 10
Output Current, IOUT (A)
Efficiency (%)
VIN=5V
VOUT=1.8V
RT=330k
Oscillator Frequency, FOSC (MHz)
RT Resistance, RRT (kΩ)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 200 400 600 800 1000 1200 1400
RT=330k for 1MHz
RT=1.3M for 300kHz
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw6
Operating Waveforms
Start-up with No Load
EN, 2V/div
IIN, 200mA/div
POK, 5V/div
VOUT, 1V/div, DC
0.5ms/div
Start-up with 3A Load
Load Transient Response
10mA
3A
Slew rate = 3A/20µs
100µs/div
VOUT, 100mV/div, AC
IOUT, 1A/div
VOUT =1.8V
Normal Operating
500ns/div
VOUT, 50mV/div, AC
VLX, 2V/div
IOUT, 1A/div
0.5ms/div
EN, 2V/div
IIN, 1A/div
POK, 5V/div
VOUT, 1V/div, DC
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw7
Pin Description
PIN
TDFN3x3-10 SOP-8P
APW7153
APW7153A
APW7153B
APW7153
NAME FUNCTION
1 - 1 1 SHDN/RT
Shutdown/Enable and Oscillator Input. Connecting a resistor to
GND sets the switching Frequency. Pull the pin to VDD to shut
down the device. Do leave the pin floating.
- 1 - - EN/RT
Shutdown/Enable and Oscillator Input. Connecting a resistor to
VDD sets the switching Frequency. Pull the pin to GND to shut
down the device. Do leave the pin floating.
2 2 2 2 GND Signal Ground. Ground of MOSFET Gate Drivers and Con
trol
Circuitry.
3, 4 3, 4 3, 4 3 LX Power Switching Output. LX is the Junction of the high-
side and
low-side Power MOSFETs to supply power to the output LC filter.
5 5 5 4 PGND Power Ground. The Source of the N-
channel power MOSFET.
Connect this pin to the system ground with lowest impedance.
6, 7 6 6 5 PVDD Power Input. PVDD supplies the step-
down converter switches.
Connecting a ceramic
bypass capacitor from PVDD to PGND to
eliminate switching noise and voltage ripple on the input to the IC.
8 7 7 6 VDD
Control circuitry supply Input. VDD supplies the control circuitry,
gate drivers. Connecting a ceramic
bypass capacitor from VDD to
GND to eliminate switching noise and voltage ripple on the input
to the IC.
- 8 8 - POK Power Good Output. This pin is open-
drain logic output that is
pulled to ground when the output voltage is not within ±
12.5% of
regulation point.
9 9 9 7 FB
Output Feedback Input. The APW7153/A senses the feedback
voltage via FB and regulates the voltage at 0.8V. Connecting FB
with a resistor-divider from the converter’
s output sets the output
voltage.
10 10 10 8 COMP
Output of the error amplifier. Connect a series RC network from
COMP to GND to
compensate the regulation control loop. In
some cases, an additional capacitor from COMP to
GND is
required.
11 11 11 9 Exposed
Pad
Connect the exposed pad to the system ground plan with large
copper area for dissipating heat into the ambient air.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw8
Block Diagram
APW7153
APW7153A
LX
Gate
Control
Fault
Logics
Error
Amplifier
FB
Inhibit
PGND
POR
Power-On-
Reset
Current Sense
Amplifier
COMP Oscillator
Slope
Compensation
Current
Compartor
Over-
Temperature
Protection Current
-Limit
Gat
e
Gm
1V OTP
Current Sense
Amplifier
LOC
LOC
VDD
SHDN/RT
0.4
Shutdown GND
Gate
Driver
UVP
VREF
OVP
Zero Crossing
Amplifier
0.8V
PVDD
Soft-Start
LX
Gate
Control
Fault
Logics
Error
Amplifier
FB
Inhibit
PGND
POR
Power-On-
Reset
Current Sense
Amplifier
COMP Oscillator
Slope
Compensation
Current
Compartor
Over-
Temperature
Protection Current
-Limit
Gat
e
Gm
PVDD
3
5
6
9
10
0.625V OTP
Current Sense
Amplifier
LOC
LOC
VDD
7
4LX
EN/RT
1
0.25V
8
Shutdown
POK
GND
Gate
Driver
UVP
VREF
OVP
2
0.5625V
0.4375V
0.5V
Zero Crossing
Comparator
Soft-Start
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw9
Block Diagram
APW7153B
LX
Gate
Control
Fault
Logics
Error
Amplifier
FB
Inhibit
PGND
POR
Power-On-
Reset
Current Sense
Amplifier
COMP Oscillator
Slope
Compensation
Current
Compartor
Over-
Temperature
Protection Current
-Limit
Gat
e
Gm
PVDD
3
5
6
9
10
1V OTP
Current Sense
Amplifier
LOC
LOC
VDD
7
4LX
SHDN/RT
1
0.4V
Soft-Start
8
Shutdown
POK
GND
Gate
Driver
UVP
VREF
OVP
2
0.9V
0.7V
0.8V
Zero Crossing
Comparator
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw10
Typical Application Circuit
APW7153
PVDD
VDD
PGND
LX
FB
VOUT
1.8V/3A
COUT
22µFx2
R1
25k
R2
20k
Cc
100pF
Rc
30k
COMP
CIN
22µF
RT
332k
C2
1µF
CFF
22pF
GND
R4
2R2
SHDN/RT
L1
2.2µH
R3
1M
VIN
5V
ON
OFF
APW7153A
PVDD
6
VDD
PGND
5
LX 3,4
FB 9
7
VOUT
1.8V/3A
COUT
22µFx2
R1
39k
R2
15k
Cc
100pF
Rc
30k
COMP 10
CIN
22µF
POK
C2
1µF
CFF
22pF
GND 2
R4
2R2
8
1EN/RT
L1
2.2µH
R3
1.8M
R5
100k
VIN
5V
OFF
ON
APW7153B
PVDD
6
VDD
PGND
5
LX 3,4
FB 9
7
VOUT
1.8V/3A
COUT
22µFx2
R1
25k
R2
20k
Cc
100pF
Rc
30k
COMP 10
CIN
22µF
POK
RT
332k
C2
1µF
CFF
22pF
GND 2
R4
2R2
8
1SHDN/RT
L1
2.2µH
R3
1M
R5
100k
VIN
5V
ON
OFF
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw11
Function Description
VDD and PVDD Power-On-Reset (POR)
The APW7153/A/B keeps monitoring the voltage on VDD
and PVDD pins to prevent wrong logic operations which
may occur when VDD or PVDD voltage is not high enough
for internal control circuitry to operate. The VDD POR ris-
ing threshold is 2.4V (typical) with 0.2V hysteresis and
PVDD POR rising threshold is 1.7V with 0.05V hysteresis.
During start-up, the VDD and PVDD voltage must exceed
the enable voltage threshold. Then, the IC starts a start-
up process and ramps up the output voltage to the volt-
age target.
Output Under-Voltage Protection (UVP)
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC shuts down con-
verter’s output.
The under-voltage threshold is 50% of the nominal out-
put voltage. The under-voltage comparator has a built-in
3µs noise filter to prevent the chips from wrong UVP shut-
down being caused by noise. APW7153/A/B will be latched
after under-voltage protection.
Over-Voltage Protection (OVP)
The over-voltage function monitors the output voltage by
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, the over-voltage protection compara-
tor will force the low-side MOSFET gate driver to be high.
This action actively pulls down the output voltage and
eventually attempts to blow the internal bonding wires.
As soon as the output voltage is within regulation, the
OVP comparator is disengaged. The chip will restore its
normal operation.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7153/A/B. When the junction temperature
exceeds TJ=+160oC, a thermal sensor turns off the both
Current-Limit Protection
The APW7153/A/B monitors the output current, flows
through the high-side and low-side power MOSFETs, and
limits the current peak at current-limit level to prevent the
IC from damaging during overload, short-circuit, and over-
voltage conditions. Typical high side power MOSFET cur-
rent-limit is 4.5A, and low side MOSFET current-limit is
1.6A maximum.
power MOSFETs, allowing the devices to cool. The ther-
mal sensor allows the converters to start a start-up pro-
cess and to regulate the output voltage again after the
junction temperature cools by 50oC. The OTP is designed
with a 50oC hysteresis to lower the average TJ during
continuous thermal overload conditions, increasing life-
time of the APW7153/A/B.
Soft-Start
The APW7153/A/B has a built-in soft-start to control the
rise rate of the output voltage and limit the input current
surge during start-up. During soft-start, an internal volt-
age ramp connected to one of the positive inputs of the
error amplifier, rises up from 0V to 0.95V to replace the
reference voltage, VREF until the voltage ramp reaches the
reference voltage. During soft-start without output over-
voltage, the APW7153/A/B converter’s sinking capability
is disabled until the output voltage reaches the voltage
target.
Soft-Off
At the moment of shutdown controlled by SHDN/RT
signal, under-voltage event or over-temperature
protection, the APW7153/A/B initiates a soft-stop process
to discharge the output voltage in the output capacitors.
Certainly, the load current also discharges the output
voltage. During soft-stop, the internal voltage ramp (VRAMP)
falls down rises from 0.95V to 0V to replace the reference
voltage. Therefore, the output voltage falls down slowly at
the light load. After the soft-stop interval elapses, the soft-
stop process ends and the IC turns on the low-side power
MOSFET.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw12
Function Description (Cont.)
Switching Frequency and Shutdown/Enable
The SHDN/RT pin is a multi-function pin that is used to
control the switching frequency and Shutdown/Enable
function of APW7153/A/B. The switching frequency is set
by the external resistor that is connected between SHDN/
RT and GND. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timing capacitor within the oscillator.
The SHDN/RT pin also provides Shutdown/Enable
function. Pulling the pin to VDD or GND, APW7153/A/B
initiates a soft-stop process and shutdown the IC.
Power Good Indicator (APW7153A/B)
POK is actively held low in shutdown and soft-start status.
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is released. In normal
operation, the POK window is from 87.5% to 112.5% of
the converter reference voltage. When the output voltage
has to stay within this window, POK signal will become
high after 0.5ms internal delay. When the output voltage
outruns 85% or 115% of the target voltage, POK signal
will be pulled low immediately. In order to prevent false
POK drop, capacitors need to parallel at the output to
confine the voltage deviation with severe load step
transient.
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw13
Application Information
Input Capacitor Selection
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
Also, the input capacitor must be sufficiently large to sta-
bilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capaci-
tor is sufficient. It can be increased without any limit for
better input voltage filtering. Ceramic capacitors show
better performance because of the low ESR value, and
they are less sensitive against voltage transients and
spikes compared to tantalum capacitors. Place the input
capacitor as close as possible to the input and GND pin
of the device for better performance.
Inductor Selection
For high efficiencies, the inductor should have a low dc
resistance to minimize conduction losses. Especially at
high-switching frequencies the core material has a higher
impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor
core losses. This needs to be considered when select-
ing the appropriate inductor. The inductor value deter-
mines the inductor ripple current. The larger the inductor
value, the smaller the inductor ripple current and the lower
the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response.
A reasonable starting point for setting ripple current, ∆IL,
is 40% of maximum output current. The recommended
inductor value can be calculated as below:
LSW
IN
OUT
OUT
IFV
V
1V
L∆⋅
−
≥
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
To avoid saturation of the inductor, the inductor should be
rated at least for the maximum output current of the con-
verter plus the inductor ripple current.
Output Voltage Setting
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is con-
nected to the output, allowing remote voltage sensing as
shown in “Typical Application Circuits”. A suggestion of
maximum value of R2 is 300kΩ to keep the minimum
current that provides enough noise rejection ability through
the resistor divider. The output voltage can be calculated
as below:
+⋅=2R1R
1VV REFOUT
R2 ≤ 300KΩ
APW7153FB
GND
VOUT
R1≤1MΩ
Output Capacitor Selection
The current-mode control scheme of the APW7153 al-
lows the use of tiny ceramic capacitors. The higher ca-
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. If required,
tantalum capacitors may be used as well. The output
ripple is the sum of the voltages across the ESR and the
ideal output capacitor.
⋅⋅
+⋅
⋅
−⋅
≅∆OUTSWSW
IN
OUT
OUT
OUT CF81
ESR
LFV
V
1V
V
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
VIN
VOUT
IL
N-FET
LX
IOUT
CIN
COUT
IIN
ESR
P-FET
IP-FET
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw14
Application Information (Cont.)
Output Capacitor Selection (Cont.)
ILIM
IL
IPEAK
IOUT
IP-FET
∆IL
Layout Considerations
For all switching power supplies, the layout is an impor-
tant step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitor should be placed close to the PVDD
and GND. Connect the capacitor and PVDD/GND with
short and wide trace without any via holes for good input
voltage filtering. The distance between PVDD/GND to
capacitor less than 2mm respectively is recommended.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed as
close as possible to the LX pin to minimize the noise
coupling into other circuits.
3. The output capacitor should be place closed to VOUT
and GND.
4. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX) on the PCB. Therefore
place the feedback divider and the feedback compensa-
tion network close to the IC to avoid switching noise.
Connect the ground of feedback divider directly to the
GND pin of the IC using a dedicated ground trace.
5. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
Figure 1. APW7153/A/B Layout Suggestion
5
1
8
9
10
4
3
2
7
6
Rc
L1
C2 C1
Cc
CFF
R2
R1
RT
VIN
VOUT
PGND
Via To VOUT
LX
FB
R4
C2
Via To GND
GND
Via To GND
Recommended Minimum Footprint
Layout
Package outline
5
1
8
9
10
4
3
2
7
6
0.011
0.04
0.06
0.1
0.06
TDFN3x3-10
Unit: Inch
0.011
The via diameter = 0.012
Hole size = 0.008
0.029
0.212
0.072
0.050
0.024
1 2 3 4
8 7 6 5
0.118
0.138
Unit : Inch
SOP-8P
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw15
Package Information
TDFN3x3-10
D
E
Pin 1
A
A1
A3
b
Note : 1. Followed from JEDEC MO-229 VEED-5.
Pin 1
Corner
D2
E2L
e
K
0.70
0.069
0.028
0.002
0.50 BSC 0.020 BSC
0.20 0.008
K
2.90 3.10 0.114 0.122
2.90 3.10 0.114 0.122
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.18 0.30
2.20 2.70
0.05
1.40
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN3x3-10
0.30 0.50
1.75
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.007 0.012
0.087 0.106
0.055
0.012 0.020
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw16
Package Information
SOP-8P
THERMAL
PAD
D
D1
E2
E1
E
eb
A2
A
A1
VIEW AL
0.25
GAUGE PLANE
SEATING PLANE
θ
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
0.020
0.010
0.020
0.050
0.006
0.063
MAX.
0.40L
θ0oC
E
e
h
E1
0.25
D
c
b
0.17
0.31
0.016
1.27
8oC0oC8oC
0.50
1.27 BSC
0.51
0.25
0.050 BSC
0.010
0.012
0.007
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.00
1.25
SOP-8P
MAX.
0.15
1.60
MIN.
0.000
0.049
INCHES
D1 2.50 0.098
2.00 0.079E2
3.50
3.00
0.138
0.118
4.80 5.00 0.189 0.197
3.80 4.00 0.150 0.157
5.80 6.20 0.228 0.244
h X 45o
c
SEE VIEW A
-T- SEATING PLANE < 4 mils
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw17
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN3x3-10
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±0.20
1.30±0.20
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8P
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Carrier Tape & Reel Dimensions
Devices Per Unit
Package Type Unit Quantity
TDFN3x3-10 Tape & Reel 3000
SOP-8P Tape & Reel 2500
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw18
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
SOP-8P
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw19
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Profile
Classification Reflow Profiles
Supplier Tp≧Tc
Supplier tp
User Tp≦Tc
User tp
t
tS
Time
Temperature
Tp
TL
tpTC -5oC
25 Time 25oC to Peak
Max. Ramp Up Rate = 3oC/s
Max. Ramp Down Rate = 6oC/s
Preheat Area
Tsmax
Tsmin
TC
TC -5oC
Copyright ANPEC Electronics Corp.
Rev. A.6 - Aug., 2012
APW7153/A/B
www.anpec.com.tw20
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Reliability Test Program
Classification Reflow Profiles (Cont.)