M24C02-RMN6TP/W - STMicroelectronics

1/29March 2004

M24C16, M24C08

M24C04, M24C02, M24C01

16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY

■Two Wire I2C Serial Interface

Sup ports 400kHz Protocol

■Sin gle Supply Vo ltage:

– 4.5 to 5.5V for M24Cxx

– 2.5 to 5.5V for M24C xx-W

– 1.8 to 5.5V for M24C xx-R

■Wri t e Control Input

■BYTE and P AG E WR ITE (up to 16 Bytes)

■RANDOM and SEQUENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enh anced ESD/ Latch -Up Behavior

■More than 1 Million Erase/Write Cycles

■More than 40 Yea r Data Retention

Figure 1. Packages

PDIP8 (BN)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

TSSOP8 (DS)

3x3mm² body size (MSO P)

UFDFPN8 (MB)

2x3mm² (MLP)

M24C16, M 24C08, M24C04, M24C 02, M 24C01

2/29

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP, SO, TSSOP and MLP Conne ctions (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Maximum RL Value versus Bus Capacitance (CBUS ) for an I2C Bus . . . . . . . . . . . . . . . 5

Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Memo ry Add ressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. Write Mode Sequenc es with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Write Mode Sequenc es with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minim izing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9. Read Mode Sequenc es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

R andom Add ress Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

C urre nt Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3/29

M24C16, M24C08, M24C04, M24C02, M 24C01

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Table 5. Operating C onditions (M2 4Cxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Operating C onditions (M2 4Cxx-W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Operating C onditions (M2 4Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. A C Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. I nput Paramet ers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 10. DC Characteristics (M24Cxx, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 11. DC Characteristics (M24Cxx, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 12. DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13. DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 14. DC Characteristics (M24 Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 15. AC Characteristics (M24Cxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 16. AC C haracteristics (M24Cxx, Device Grade 3; M24Cx x-W, Device Grade 6 or 3) . . . . . 18

Table 17. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Figure 12.P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outlin e . . . . . . . . . . . . . . . . . 21

Table 18. P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package M echanical Data. . . . . . . . . . 21

Figure 13.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22

Table 19. SO8 nar row – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data

Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fi ne pitch Dual Flat Package No lead 2x3mm ², Outline

Table 20. UF D FPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.

Figure 15.TSS OP 8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24

Table 21. TSS OP 8 – 8 lead Thin Shrink Sma ll Outline, Package Mechani ca l Data . . . . . . . . . . . . 24

Figure 16.TSS OP 8 3x3m m² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline

Table 22. TSSOP8 3x3mm ² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechani cal Data

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 24. How t o Identify Current and New Products by t he Process Identification Letter . . . . . . . 27

REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 25. Document Re vision Histo ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M24C16, M 24C08, M24C04, M24C 02, M 24C01

4/29

SUMMA RY DESCRIP T ION

These I2C-compatible electrically erasable pro-

grammabl e memor y (EEPROM) devices are orga-

nized as 2048/1024/512/256/128 x 8 (M24C16,

M24C08, M24C04, M24C02, M24C01).

Figure 2. Logic Diagram

I2C uses a two wire seria l interface, comprising a

bi-directional data line and a clock line. The devic-

es carry a built- in 4-bit Dev ice Type Identifier code

(1010) in accordance with the I 2C bus definition.

The device behaves as a sl ave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start c ondi tion, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 2.),

terminated by an acknowledge bit.

When writing data to the memory, the device in-

serts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledg es the receipt of the data byte

in t he same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Table 1. Signal Names

Power On Reset: VCC Lock-Out Write Protec t

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. At Power-up, the

internal rese t is held ac tive unt il VCC has re ached

the POR threshold value, and all operations are

disabled – the devi ce wil l not respond to any com-

mand. In the same way, when VCC drops from the

operating voltage, below the POR threshold value,

all operations are disabled and the device will not

respond to any command .

A stable and val id VCC (as defined in Table 6. and

Table 7.) must be applied bef or e apply ing any log-

ic signal.

Figure 3. DIP, SO, TSSOP an d ML P Conn e c t ions (To p View)

N ote: 1. NC = Not Connec ted

2. See PACKAG E MECH ANI CAL section fo r package di m ensions, and how to id entify pin-1.

AI02033

E0-E2 SDA

VCC

M24Cxx

SCL

VSS

E0, E1, E2 Chip Enable

SDA Serial Data

SCL Serial Clock

WC Write Control

VCC Supply Volta ge

VSS Ground

SDAVSS SCL

VCC

/ E2

AI02034E

M24Cxx

/ E2/ E2/ E2NC / E1

/ E1/ E1/ NCNC / E0

/ E0/ NC/ NCNC /1Kb

/2Kb/4Kb/8Kb16Kb

5/29

M24C16, M24C08, M24C04, M24C02, M 24C01

SIGNAL DESCRIPTION

Serial Clock (SCL). This input signal is used to

strobe all data in and out of the devic e. In applica-

tions where t his signal is used by slave devi ces to

synchronize the bus to a slower clock, the bus

master must have an open drain output, and a

pull-up resistor can be connected from Serial

Clock (SCL) to VCC. (Figure 4. indicates how the

value of the pull-up resistor can be calculated). In

most applications, though, this method of synchro-

nization is not employe d, and so the pull-up resis-

tor is not necessary, prov ided that the bus ma ster

has a push-pull (rather th an open drain) output.

Serial Data (S DA). This bi-directional signal is

used to transfer data in or out of the device. It is an

open drain output that may be wire-OR’ed with

other open drain or open collector signa ls on the

bus. A pull up resistor must be connected from Se-

rial Data (SDA) to VCC. (Figure 4. indicates how

the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1, E2). These input signals

are used to set the value that is t o be l ooked for on

the three least significant bits (b3, b2, b1) of t he 7-

bit Device Select Code. These inputs must be tied

to VCC or VSS, to establish the Device Select

Code.

Write Control (WC). This input signal is useful

for protecting the entire contents of the memory

from inadvertent write operations. Write opera-

tions are disabled to the entire memory array when

Write Control (WC) is driven High. When uncon-

nected, the signal is internally read as VIL, and

Write operations are allowed.

When Write Control (WC) is driven High, Device

Select and Address bytes are acknowledged,

Data bytes are not acknowledged.

Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

AI01665

VCC

CBUS

SDA

MASTER

SCL CBUS

100

CBUS (pF)

Maximum RP value (kΩ)

10 1000

fc = 400kHz

fc = 100kHz

M24C16, M 24C08, M24C04, M24C 02, M 24C01

6/29

Figure 5. I2C Bus Protocol

Table 2. Device Select Code

Note: 1. The most significant bit, b7, is sent first.

2. E0, E1 and E2 are com pared against the respect i ve external pins on the memory devi ce.

3. A10, A9 and A8 represent m ost significant bi ts of the address.

Device Type Identifier1Chip Enable2,3 RW

b7 b6 b5 b4 b3 b2 b1 b0

M24C01 Select Code1010E2E1E0RW

M24C02 Select Code1010E2E1E0RW

M24C04 Select Code1010E2E1A8RW

M24C08 Select Code1010E2A9A8RW

M24C16 Select Code1010A10A9A8RW

SCL

SDA

SCL

SDA

START

Condition

SDA

Input SDA

Change

AI00792B

STOP

Condition

123 789

MSB ACK

START

Condition

SCL 123 789

MSB ACK

STOP

Condition

7/29

M24C16, M24C08, M24C04, M24C02, M 24C01

DEVICE OPERATION

The device supports the I2C protocol. This i s sum-

mari zed in Figure 5.. Any device that sends data

on to the bus is defined to be a transmitter, and

any device that reads the data to be a receiver.

The device that controls the data transfer is known

as the bus master, and the other as the slave de-

vice. A data transfer can only be initiated by the

bus master, which will also provide t he serial clock

for synchronization. The M24Cxx device is always

a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except duri n g a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not re spond unles s one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminat es comm unica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a W rite command triggers the internal EE-

P R OM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whet her it be

bus master or slave device, releases Serial Data

(SDA) after sending eight bits of data. During the

9th clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change only when Serial Clock (S CL) i s driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus maste r must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 2.

(on Serial Data (SDA ), most significant bit first).

The Device Select Code consists of a 4-bit Devi ce

Type Identifier, and a 3-bit Chip Enable “Add ress”

(E2, E1, E0). To address the memory array, t he 4-

bit Device T ype Identifier is 1010b.

Each device is given a unique 3-bit code on the

Chip Enable (E0, E1, E2) inputs. When the Device

Select Code is received, the device only responds

if the Chip Enable Address is the same as the val-

ue on the Chip Enable (E0, E1, E2) inputs. How-

ever, those devices with larger memory capacities

(the M24C16, M24C08 and M24C04) need more

address bit s. E0 is not available for use on devices

that need to use address line A8; E1 is not avail-

able for devices that n eed t o use address line A9,

and E2 is not available for devices that need to use

address line A10 (see Figure 3. and Table 2. for

details). Using the E0, E1 and E2 inputs, up to

eight M24C02 (or M24C01), four M24C04, two

M24C08 or one M24C16 devices can be conn ect-

ed to one I2C bus. In each case, and in the hybrid

cases, this gives a total memory capacity of

16 Kbits, 2 KBytes (except where M 24C01 devic-

es are used).

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SD A) du ring the 9 th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 3. O peratin g Modes

No te: 1. X = VIH or VIL.

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = 1

Random Address Read 0X1START, Device Select, RW = 0, Address

1 X reSTART, Device Select, RW = 1

Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = 0

Page Write 0 VIL ≤ 16 START, Device Select, RW = 0

M24C16, M 24C08, M24C04, M24C 02, M 24C01

8/29

Figure 6. Write Mode Sequences with WC=1 (data writ e inhibite d)

Write Operations

Following a Start condition the bus master sends

a Device Select Code with the RW bi t re set t o 0.

The device acknowledges t hi s, as shown in Figure

7., an d waits for an address byte. The device re-

sponds to the address byte with an acknowledge

bit, and th en waits for the data byte.

When th e bus mast er generate s a S top con dition

immediately af ter the Ack bi t (in the “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Seria l Da ta (SDA)

and Serial Clock (SCL) are ignored, and the de-

vice does not respond to any requests.

Byte Write

After the Device Select code and the address byte,

the bus master sends one data byte. If the ad-

dressed location is Write-protected, by Wri te Con-

trol (WC) being driven High (during the period from

the Start condition until the end of the address

byte), the device replies to the data byte with

NoAck, as show n in Figure 6., and t he location is

not modified. If, instead, the address ed location is

not Write-protected, the device replies with Ack.

The bus ma ster terminates the transf er by gener-

ating a Stop condi tion, as shown in Figure 7. .

Page Write

The Pag e Write m ode allows u p to 16 byt es to be

written in a single Write cycle, provided that they

are all located in the same page in the memory:

that is, the most significant memory address bits

are t he same. If more bytes are sent than will fit up

to the end of the pa ge, a c ond ition known as ‘ roll-

over’ occurs. This should be avoided, as data

starts to become overwrit ten in an implementation

dependent way.

The bus master sends f rom 1 to 16 b ytes of data,

each of which is acknowledged by the device if

Write Control (WC ) is Low. If the addres sed loca-

tion is Write-protected, by Write Control (WC) be-

ing driven High (during the period from the Start

STOP

START

Byte Write DEV SEL BYTE ADDR DATA IN

START

Page Write DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

DATA IN 3

AI02803C

Page Write

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK ACK NO ACK

R/W

ACK ACK NO ACK NO ACK

R/W

NO ACK NO ACK

9/29

M24C16, M24C08, M24C04, M24C02, M 24C01

condition until the end of the address byte), the de-

vice replies to the data bytes with NoAck, as

shown in Figure 6., and the locations are not mod-

ified. After each byte is transferred, the internal

byte address counter (the 4 least significant ad-

dress bits onl y) is i ncremented. The transfer i s t er-

minated by the bus master generating a Stop

condition.

Figure 7. Write Mode Sequences with WC=0 (data writ e enabled )

STOP

START

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

DATA IN 3

AI02804B

PAGE WRITE

(cont'd)

WC (cont'd)

STOP

DATA IN N

ACK

R/W

ACK ACK

ACK ACK ACK ACK

R/W

ACKACK

M24C16, M 24C08, M24C04, M24C 02, M 24C01

10/29

Figu re 8. Wri t e C yc le Pol l in g Fl owchart usi n g A C K

Minimizing System Delays by Polling On ACK

During the internal Write cycle, the device discon-

nects itself from the bus, and writes a copy of the

data from its internal latches to the memory cells.

The maximum Write time (tw) is shown in Table

15. to Table 17., but the typical time is shorter. To

make use of this, a polling s equence c an be us ed

by the bus master.

The sequence , as shown in Figure 8., is :

– Initial condition: a Write cycle is in progress.

– Step 1: the bus master issues a Start condition

followed by a Device Select Code (the first

byte of the new instruction).

– Step 2: if the device is bus y with the internal

Wri te cycle, no Ack will be returned and the

bus master goes back to Step 1. If the device

has terminated the internal Write cy cle, it

respo nds with an Ack, indicating that the

devi ce is ready to receive t he second part of

the instruction (the first byte of this instruction

hav ing been sent during Step 1).

WRITE Cycle

in Progress

AI01847C

Operation is

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

YESNO

ReSTART

STOP

DATA for the

WRITE Operation DEVICE SELECT

with RW = 1

Send Address

and Receive ACK

First byte of instruction

with RW = 0 already

decoded by the device

YESNO START

Condition

Continue the

WRITE Operation Continue the

Random READ Operation

11/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Figure 9. Read Mode Sequences

Note: Th e seven mo st signif i cant bit s of the Device Select Code of a Rando m Read (in the 1st and 3rd by tes) must b e ide n tical.

Read Operation s

Read operations are performed independently of

the state of the Wri te Control (WC) signal.

The device has an internal address counter which

is incremented each time a byte is read.

Random Address Read

A dummy Write is first performed to load the ad-

dress into this address counter (as shown in Fig-

ure 9.) but without sending a Stop condition. Then,

the bus master sends another St art c ondition, and

repeats the Device Select Code, with the RW bit

set to 1. The device acknowled ges this, and out-

puts the conten ts of the addressed byte. The bus

ma ster must not acknowledge the byte, and t e rmi-

nates the transfer with a Stop condition .

Current Address Read

For the Current Address Read operation, following

a Start condition, the bus master only sends a De-

vice Select Code with the RW bit set to 1. The de-

vice acknowledges this, and outputs the byte

addressed by the internal address counter. The

counter is then incremented. T he bus master ter-

minates the transfer with a Stop condition, as

shown in Figure 9., without acknowledging the

byte.

START

DEV SEL * BYTE ADDR

START

DEV SEL DATA OUT 1

AI01942

DATA OUT N

STOP

START

CURRENT

ADDRESS

READ DEV SEL DATA OUT

RANDOM

ADDRESS

READ

STOP

START

DEV SEL * DATA OUT

SEQUENTIAL

CURRENT

READ

STOP

DATA OUT N

START

DEV SEL * BYTE ADDR

SEQUENTIAL

RANDOM

READ

START

DEV SEL * DATA OUT 1

STOP

ACK

R/W

NO ACK

ACK

R/W

ACK ACK

R/W

ACK ACK ACK NO ACK

R/W

NO ACK

ACK ACK

R/W

ACK ACK

R/W

ACK NO ACK

M24C16, M 24C08, M24C04, M24C 02, M 24C01

12/29

Sequenti al Re ad

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master does acknowledge the data byte output,

and sends additional cl ock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 9..

The output data com es from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address count er ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, f or an acknowledgment duri ng the

9th bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the devi ce t ermi-

nates the data transfer and s witches to its St and-

by mode.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh).

13/29

M24C16, M24C08, M24C04, M24C02, M 24C01

M A XI MUM RAT IN G

Stressing the device ab ove t he rating listed in t he

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hese or

any other con ditions ab ove those i ndicated in t he

Operating sections of this specification is not im-

plied. Exposure to Absolute Max imum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 4. Absolute Maximum Ratings

Note : 1. Comp li ant wit h JED EC Std J- STD- 020 B (for small bod y, Sn-Pb or Pb asse mbl y), the ST ECOP ACK ® 7191395 s pecificat i on, and

the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoHS) 2002/ 95/EU

2. JED EC St d JESD22-A11 4A (C1=100 pF, R1 =1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input or Output range –0.50 6.5 V

VCC Supply Voltage –0.50 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2–4000 4000 V

M24C16, M 24C08, M24C04, M24C 02, M 24C01

14/29

DC AND A C PARAMETERS

This section summarizes the operating and mea-

surement condition s, and the DC and AC charac-

teristics o f the de vi ce . The parameters in the DC

and AC Characteristic tables that follow are de-

rived from tests performed under the Measure-

ment Conditions summarized in the relevant

tables. Des igners shoul d c heck that the operating

conditions in t heir circuit matc h the measurem ent

conditions when relying on the quoted parame-

ters.

Table 5. Operating Conditions (M24Cxx )

Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range .

Table 6. Operating Conditions (M24Cxx-W)

Table 7. Operating Conditions (M24Cxx-R)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 4.5 5.5 V

TAAmbient Operating Temperature (Device Grade 6) –40 85 °C

Ambient Operating Temperature (Device Grade 3) –40 125 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.5 5.5 V

TAAmbient Operating Temperature (Device Grade 6) –40 85 °C

Ambient Operating Temperature (Device Grade 3) –40 125 °C

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.8 5.5 V

TAAmb ient Operati ng Tem peratur e –40 85 °C

15/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Table 8. AC Measu rem en t Conditions

Figu re 10. AC Measure m e nt I/ O Wa veform

Table 9. Input Parameters

Note: 1. TA = 25°C, f = 400kHz

2. Sampled only, not 100% t ested.

Table 10. DC Characteristics (M24 Cxx, Device Grade 6)

Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx6 range.

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Levels 0.2VCC to 0.8VCC V

Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V

Symbol Parameter1,2 Test Condition Min.Max.Unit

CIN Input Capa citanc e (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance VIN < 0.5 V 5 70 kΩ

ZWCH WC Input Impedance VIN > 0.7VCC 500 kΩ

tNS Pulse width ignored

(Input Filter on SCL and SDA) Single glitch 100 n s

Symbol Parameter Test Condition

(in addition to those in Table 5.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC=5V, fc=400kHz (rise/fall time < 30ns) 2mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5 V 1µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.45 0.3VCC V

Input Low Voltage (WC) –0.45 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

M24C16, M 24C08, M24C04, M24C 02, M 24C01

16/29

Table 11. DC Characteristics (M24Cxx, Device Grade 3)

Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx3 range.

Table 12. DC Characteristics (M24Cxx-W, Device Grade 6)

Symbol Parameter Test Condition

(in addition to those in Table 5.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC=5V, fc=400kHz (rise/fall time < 30ns) 3mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 5 V 5µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.45 0.3VCC V

Input Low Voltage (WC) –0.45 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V

Symbol Parameter Test Condition

(in addition to those in Table 6.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 2.5 V 0.5 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.45 0.3VCC V

Input Low Voltage (WC) –0.45 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

17/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Table 13. DC Characteristics (M24Cxx-W, Device Grade 3)

Note: 1. This is preliminary data.

Table 14. DC Character istics (M24 Cxx-R)

Symbol Parameter Test Condition

(in addition to those in Table 6.)Min.1Max.1Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 3mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 2.5 V 2µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) –0.45 0.3VCC V

Input Low Voltage (WC) –0.45 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V

Symbol Parameter Test Condition

(in addition to those in Table 7.)Min. Max. Unit

ILI Input Leaka ge Curren t

(SCL, SDA) VIN = VSS or VCC ± 2 µA

ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA

ICC Supply Current VCC =1 . 8 V, f c=400kHz (rise/f all time < 30ns) 0.8 mA

ICC1 Stand -by Supply Current VIN = VSS or VCC , VCC = 1.8 V 0.3 µA

VIL

Input Low Voltage

(E2, E1, E0, SCL, SDA) 2.5 V ≤ VCC –0.45 0.3 VCC V

1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V

Input Low Voltage (WC) –0.45 0.5 V

VIH Input High Volta ge

(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V

VOL Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V 0.2 V

M24C16, M 24C08, M24C04, M24C 02, M 24C01

18/29

Table 15. AC Characteristics (M24 Cxx, Device Grade 6)

Note: 1. F or a reSTA RT condition, or fo l l owing a Wri te cycle .

2. Sampled only, not 100% t ested.

3. To avoid spurious START and STOP c onditions, a minimum delay i s placed between SCL=1 and the fal ling or ris ing edge of SDA.

4. This is preliminary data for M24Cxx-Wxx3.

Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3)

Note: 1. F or a reSTA RT condition, or fo l l owing a Wri te cycle .

2. Sampled only, not 100% t ested.

3. To avoid spurious START and STOP c onditions, a minimum delay i s placed between SCL=1 and the fal ling or ris ing edge of SDA.

4. 10ms write t ime is offered on the standard device. 5ms write t ime is offered on new products bearing the Process Identification letter

“W” or “G ” on the package, as described in Table 24..

Test conditions specified in Table 8. and Table 5.

Symbol Alt. Parameter Min.4Max.4Unit

fCfSCL Clock Fre quenc y 400 kHz

tCHCL tHIGH Clock Pulse Width High 600 ns

tCLCH tLOW Clock Pulse Width Low 1300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 100 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 600 ns

tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns

tWtWR Write Time 5 ms

Test conditions specified in Table 8. and Table 5. or Table 6.

Symbol Alt. Parameter Min. Max. Unit

fCfSCL Clock Fre quenc y 400 kHz

tCHCL tHIGH Clock Pulse Width High 600 ns

tCLCH tLOW Clock Pulse Width Low 1300 ns

tDL1DL2 2tFSDA Fall Time 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 100 ns

tCLDX tHD:DAT Data In Hold Time 0 ns

tCLQX tDH Data Out Hold Time 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 600 ns

tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns

tWtWR Write Time 10 or4 5 ms

19/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Table 17. AC Characteristics (M24Cxx-R)

Note: 1. F or a reSTA RT condition, or fo l l owing a Wri te cycle .

2. Sampled only, not 100% t ested.

3. To avoid spurious START and STOP c onditions, a minimum delay i s placed between SCL=1 and the fal ling or ris ing edge of SDA.

4. 100kHz clock frequency is offered on the standard device. 400kHz clock frequency is offered on new products bearing the Process

Ident i fication letter “W” or “G” on the package, as descri bed in T a ble 24 ..

Test conditions specified in Table 8. and Table 7.

Symbol Alt. Parameter Min. Max. Min.4Max.4Unit

fCfSCL Clock Fre quenc y 100 400 kHz

tCHCL tHIGH Clock Pulse Width High 4000 600 ns

tCLCH tLOW Clock Pulse Width Low 4700 1300 ns

tDL1DL2 2tFSDA Fall Time 20 300 20 300 ns

tDXCX tSU:DAT Data In Set Up Time 250 100 ns

tCLDX tHD:DAT Data In Hold Time 0 0 ns

tCLQX tDH Data Out Hold Time 200 200 ns

tCLQV 3tAA Clock Low to Next Data Valid (Access

Time) 200 3500 200 900 ns

tCHDX 1tSU:STA Start Condition Set Up Time 4700 600 ns

tDLCL tHD:STA Start Condition Hold Time 4000 600 ns

tCHDH tSU:STO Stop Condition Set Up Time 4000 600 ns

tDHDL tBUF Time between Stop Condition and

Next Start Condition 4700 1300 ns

tWtWR Write Time 10 10 ms

M24C16, M 24C08, M24C04, M24C 02, M 24C01

20/29

Figure 11. AC Waveforms

SCL

SDA In

SCL

SDA Out

SCL

SDA In

tCHCL

tDLCL

tCHDX

START

Condition

tCLCH

tDXCXtCLDX

SDA

Input

SDA

Change tCHDH tDHDL

STOP

Condition

Data Valid

tCLQV tCLQX

tCHDH

STOP

Condition

tCHDX

START

Condition

Write Cycle

AI00795C

START

Condition

21/29

M24C16, M24C08, M24C04, M24C02, M 24C01

P ACKAGE ME CHANICA L

Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead fram e, Packag e Outline

No te : Drawing is not to scal e.

Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Pac kage Mech anical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 5.33 0.210

A1 0.38 0.015

A2 3.30 2.92 4.95 0.130 0.115 0.195

b 0.46 0.36 0.56 0.018 0.014 0.022

b2 1.52 1.14 1.78 0.060 0.045 0.070

c 0.25 0.20 0.36 0.010 0.008 0.014

D 9.27 9.02 10.16 0.365 0.355 0.400

E 7.87 7.62 8.26 0.310 0.300 0.325

E1 6.35 6.10 7.11 0.250 0.240 0.280

e2.54––0.100––

eA 7.62 – – 0.300 – –

eB 10.92 0.430

L 3.30 2.92 3.81 0.130 0.115 0.150

PDIP-B

M24C16, M 24C08, M24C04, M24C 02, M 24C01

22/29

Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline

No te : Drawing is not to scal e.

Table 19. SO8 narrow – 8 lead Plastic Small Outli ne, 150 mils body width, Package Mechanical Data

Symb. mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27––0.050––

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α0° 8° 0° 8°

N8 8

CP 0.10 0.004

SO-a

LA1 α

h x 45˚

23/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline

Note: 1. Drawing is not to scale.

2. The c ent ral pad (the area E2 by D2 in the above illustra ti on) is pul l ed, inte rnally, to VSS. It must not be al lo wed to be c onnect ed to

any ot her vol tage or si gnal line on the PC B, for example du ri ng the sol derin g process.

Table 20. U FDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm ², Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 0.55 0.50 0.60 0.022 0.020 0.024

A1 0.00 0.05 0.000 0.002

b 0.25 0.20 0.30 0.010 0.008 0.012

D 2.00 0.079

D2 1.55 1.65 0.061 0.065

ddd 0.05 0.002

E 3.00 0.118

E2 0.15 0.25 0.006 0.010

e 0.50 – – 0.020 – –

L 0.45 0.40 0.50 0.018 0.016 0.020

L1 0.15 0.006

L3 0.30 0.012

N8 8

UFDFPN-01

A1 ddd

M24C16, M 24C08, M24C04, M24C 02, M 24C01

24/29

Figure 15. TSS OP8 – 8 lead Thin Shrink S mall Outline, Packa ge Ou tline

No te : Drawing is not to scal e.

Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechan ical Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α0° 8° 0° 8°

TSSOP8AM

EE1

A2A

25/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Figure 16. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline

No te : Drawing is not to scal e.

Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data

Symbol mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.100 0.0433

A1 0.050 0.150 0.0020 0.0059

A2 0.850 0.750 0.950 0.0335 0.0295 0.0374

b 0.250 0.400 0.0098 0.0157

c 0.130 0.230 0.0051 0.0091

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

E 4.900 4.650 5.150 0.1929 0.1831 0.2028

E1 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

CP 0.100 0.0039

L 0.550 0.400 0.700 0.0217 0.0157 0.0276

L1 0.950 0.0374

α0° 6° 0° 6°

TSSOP8BM

EE1

A2A

M24C16, M 24C08, M24C04, M24C 02, M 24C01

26/29

PART NUMBERING

Table 23. Ordering Information Scheme

Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-

tified F l ow (HRCF) is described in the quality note QNE E9 801. Please ask your nearest ST sale s of f i ce for a copy .

2. 2.5 to 5.5V devices bearing the process letter “W” or “G” in the package marking (on the top side of the pac kage, on the right sid e ,

see Table 24.), guarantee a maximum write t ime of 5ms, instead of the standard 10ms. For more information about these devices,

and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/EE/0061 and 0062

(PCE E 0061 an d P CE E0062).

3. Used only for Dev i ce Grade 3

4. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.

Example: M24C08 – W DW 6 T P /W

Device Type

M24 = I2C serial access EEPROM

Device Function

16 = 16 Kbit (2048 x 8)

08 = 8 Kbit (1024 x 8)

04 = 4 Kbit (512 x 8)

02 = 2 Kbit (256 x 8)

01 = 1 Kbit (128 x 8)

Operating Voltage

blank 4 = VCC = 4.5 to 5.5V (400kHz)

W 2 = VCC = 2.5 to 5.5V (400kHz)

R = VCC = 1.8 to 5.5V (400kHz)

Package

BN = PDIP8

MN = SO8 (150 mil width)

MB = UDFDFPN8 (MLP8)

DW = TSSOP8 (169 mil width)

DS = TSSOP8 (3x3mm² body size, MSOP8)

Device Grade

6 = Industrial: device tested with standard test flow over –40 to 85 °C

3 = Automotive: device tested with High Reliability Certified Flow1 over –40 to 125 °C

Option

T = Tape & Reel Packing

Plating Technology

blank = Standard SnPb plating

P = Lead-Free and RoHS compliant

G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

Process3

blank = F6SP20%

/W = F6SP36%

/G = F6SP36%

27/29

M24C16, M24C08, M24C04, M24C02, M 24C01

For a list of available options (speed, package,

etc.) or for further i nf ormation on any aspect of this device, please c ontact your neares t ST Sales O f-

fice.

Table 24. H ow to Identify Current and New Products by the Process Identification Letter

Note: 1. T hi s example co m es fro m the S0 8 package. Other package s have simi l ar i nformation . For fur ther information, ple ase ask your ST

Sales O ffi ce for Process Change Not i ces PCN M P G/EE/00 61 and 0062 (PCEE0061 and PC EE006 2).

Markings on Current Products1Markings on New Products1

24CxxW6

ST xxxxL24CxxW6

ST xxxxW24CxxW6

ST xxxxG

M24C16, M 24C08, M24C04, M24C 02, M 24C01

28/29

REVISION HISTORY

Table 25. Document Revi sion History

Date Version Description of Revision

10-Dec-1999 2.4 TSSOP8 Turned-Die package removed (p 2 and order information)

Lead temperature added for TSSOP8 in table 2

18-Apr-2000 2.5 Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13

05-May-2000 2.6 Extra labelling to Fig-2D

23-Nov-2000 3.0 SBGA package information removed to an annex document

-R range changed to being the -S range, and the new -R range added

19-Feb-2001 3.1

SBGA package information put back in this document

Lead Soldering Temperature in the Absolute Maximum Ratings table amended

Write Cycle Polling Flow Chart using ACK illustration updated

References to PSDIP changed to PDIP and Package Mechanical data updated

Wording brought in to line with standard glossary

20-Apr-2001 3.2 Revision of DC and AC characteristics for the -S series

08-Oct-2001 3.3 Ball numbers added to the SBGA connections and package mechanical illustrations

09-Nov-2001 3.4 Specification of Test Condition for Leakage Currents in the DC Characteristics table

improved

30-Jul-2002 3.5 Document reformatted using new template. SBGA5 package removed

TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage range added

04-Feb-2003 3.6 Document title spelt out more fully. “W”-marked devices with tw=5ms added.

05-May-2003 3.7 -R voltage range upgraded to 400kHz working, and no longer preliminary data.

5V voltage range at temperature range 3 (-xx3) no longer preliminary data.

-S voltage range removed. -Wxx3 voltage+temp ranged added as preliminary data.

07-Oct-2003 4.0 Table of contents, and Pb-free options added. Minor wording changes in Summary

Description, Power-On Reset, Memory Addressing, Read Operations. VIL(min) improved to

-0.45V. tW(max) value for -R voltage range corrected.

17-Mar-2004 5.0

MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed.

Soldering temperature information clarified for RoHS compliant devices. Device grade

information clarified. Process identification letter “G” information added. 2.2-5.5V range is

removed, and 4.5-5.5V range is now Not for New Design

29/29

M24C16, M24C08, M24C04, M24C02, M 24C01

Information furnished is believed to b e accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e s ubjec t

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronic s products are not

authorized for us e as crit i cal com ponents in lif e support devices or sy stems w i th out expre ss written app rov al of STMi croelect ronics.

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