SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 D D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 13 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control SN54HC191 . . . J OR W PACKAGE SN74HC191 . . . D, N, OR NS PACKAGE (TOP VIEW) B QB QA CTEN D/U QC QD GND 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D QB B NC VCC A QA CTEN NC D/U QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 CLK RCO NC MAX/MIN LOAD QD GND NC D C The outputs of the four flip-flops are triggered on a low- to high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down. 16 2 SN54HC191 . . . FK PACKAGE (TOP VIEW) description/ordering information The 'HC191 devices are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. 1 NC - No internal connection ORDERING INFORMATION PACKAGE TA PDIP - N -40C -40 C to 85 85C C -55C 125C -55 C to 125 C ORDERABLE PART NUMBER TOP-SIDE MARKING Tube of 25 SN74HC191N Tube of 40 SN74HC191D Reel of 2500 SN74HC191DR Reel of 250 SN74HC191DT SOP - NS Reel of 2000 SN74HC191NSR HC191 CDIP - J Tube of 25 SNJ54HC191J SNJ54HC191J CFP - W Tube of 150 SNJ54HC191W SNJ54HC191W SOIC - D SN74HC191N HC191 LCCC - FK Tube of 55 SNJ54HC191FK SNJ54HC191FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* &)$#!" #&(! ! 0 1 2 343 (( &%!%" % !%"!%) $(%"" !+%-"% !%)* (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 description/ordering information (continued) These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be cascaded easily by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 logic diagram (positive logic) 12 CTEN 4 13 D/U 5 CLK 14 LOAD 11 A 15 S 3 C1 1D R B MAX/MIN RCO QA 1 S 2 QB C1 1D R C 10 S 6 C1 1D R D QC 9 S C1 1D R 7 QD Pin numbers shown are for the D, J, N, NS, and W packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 typical load, count, and inhibit sequence The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A Data Inputs B C D CLK D/U CTEN QA Data Outputs QB QC QD MAX/MIN RCO 13 14 15 0 1 2 2 Count Up Load POST OFFICE BOX 655303 1 0 15 14 Count Down Inhibit 4 2 * DALLAS, TEXAS 75265 13 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC191 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage 0 Input transition rise/fall time SN74HC191 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci 6 VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25C TYP MAX SN54HC191 MIN MAX SN74HC191 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 8 160 80 A 3 10 10 10 pF 6V 2 V to 6 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency LOAD low tw Pulse duration CLK high or low Data before LOAD CTEN before CLK tsu Setup time D/U before CLK LOAD inactive before CLK Data after LOAD th Hold time CTEN after CLK D/U after CLK CLK POST OFFICE BOX 655303 TA = 25C MIN MAX SN54HC191 MIN MAX SN74HC191 MIN MAX 2V 4.2 2.8 3.3 4.5 V 21 14 17 6V 24 16 19 2V 120 180 150 4.5 V 24 36 30 6V 21 31 26 2V 120 180 150 4.5 V 24 36 30 6V 21 31 26 2V 150 230 188 4.5 V 30 46 38 6V 25 38 32 2V 205 306 255 4.5 V 41 61 51 6V 35 53 44 2V 205 306 255 4.5 V 41 61 51 6V 35 53 44 2V 150 225 190 4.5 V 30 45 38 6V 25 38 32 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 * DALLAS, TEXAS 75265 UNIT MHz ns ns ns 7 SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD A, B, C, or D Any Q QA, QB, QC, or QD RCO CLK Any Q tpd MAX/MIN RCO D/U MAX/MIN CTEN tt RCO Any VCC MIN TA = 25C TYP MAX SN54HC191 MIN MAX SN74HC191 MIN 2V 4.2 8 2.8 3.3 4.5 V 21 42 14 17 6V 24 48 16 19 MAX UNIT MHz 2V 130 264 396 330 4.5 V 40 53 79 66 6V 33 45 67 56 2V 135 240 360 300 4.5 V 36 48 72 60 6V 30 41 61 51 2V 58 120 180 150 4.5 V 17 24 36 30 6V 14 21 31 26 2V 107 192 288 240 4.5 V 31 38 58 48 6V 26 32 49 41 2V 123 252 378 315 4.5 V 39 50 76 63 6V 32 43 65 54 2V 102 228 342 285 4.5 V 29 46 68 57 6V 24 38 59 49 2V 86 192 288 240 4.5 V 24 38 58 48 6V 20 32 49 41 2V 50 132 198 165 4.5 V 15 26 40 33 6V 13 23 34 28 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25C PARAMETER Cpd 8 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TYP 50 UNIT pF SCLS121D - DECEMBER 1982 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-8689101EA ACTIVE CDIP J 16 1 TBD Call TI Call TI SN54HC191J ACTIVE CDIP J 16 1 TBD SN74HC191D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 25 Pb-Free (RoHS) SN74HC191N ACTIVE PDIP N 16 SN74HC191N3 OBSOLETE PDIP N 16 TBD N / A for Pkg Type CU NIPDAU N / A for Pkg Type Call TI Call TI SN74HC191NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) SN74HC191NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC191NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC191FK ACTIVE LCCC FK 20 1 TBD SNJ54HC191J ACTIVE CDIP J 16 1 TBD Addendum-Page 1 CU NIPDAU N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 Samples (Requires Login) 5962-86891012A A42 (3) N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC191, SN74HC191 : * Catalog: SN74HC191 * Military: SN54HC191 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC191DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC191NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC191DR SN74HC191NSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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