CS42L56 Ultralow Power, Stereo Codec with Class H Headphone Amp DIGITAL to ANALOG FEATURES ANALOG to DIGITAL FEATURES 5 mW Stereo Playback Power Consumption 3.5 mW Stereo Record Power Consumption 99 dB Dynamic Range (A-wtd) 95 dB Dynamic Range (A-wtd) -86 dB THD+N -87 dB THD+N Configurable Analog Inputs - Two Pseudo-differential Stereo Inputs or - One Pseudo-differential Stereo Inputs + One Standard Stereo Input + One Standard Mono Input or - Three Standard Stereo Inputs - Pseudo-differential Inputs Reduce Common Mode Signal Noise - 3:1 Stereo Input MUX for ADC or Passthrough Digital Signal Processing Engine - - - - - Bass & Treble Tone Control, De-emphasis Master Volume Control (+12 to -102 dB in 0.5 dB steps) Soft-ramp & Zero-cross Transitions Programmable Peak-detect and Limiter Beep Generator with Full Tone Control Stereo Headphone and Line Amplifiers Step-down/Inverting Charge Pump Analog Programmable Gain Amplifier (PGA) Class H Amplifier - Automatic Supply Adj. - - - - High Efficiency Low EMI Pseudo-differential Ground-centered Outputs Programmable, Low-noise MIC Bias Output High HP Power Output at -75 dB THD+N - +12 to -6 dB in 0.5 dB steps +10 dB or +20 dB Additional Gain for Microphone Inputs Programmable Automatic Level Control (ALC) 2 x 20 mW Into 16 @ 1.8 V - - 1 VRMS Line Output @ 1.8 V Analog Vol. Ctl. (+12 to -60 dB in 1 dB steps) Noise Gate for Noise Suppression Programmable Threshold & Attack/Release Rates Analog In to Analog Out Passthrough Independent ADC Channel Control Pop and Click Suppression High-pass Filter Disable for DC Measurements Analog Supply (VA) +1.62 V to +2.75 V Charge Pump Supply (VCP) +1.62 V to +2.75 V Digital Supply (VLDO) +1.62 V to +2.75 V Step-Down LDO Regulator ALC Left Input 1 Beep 0, +10, or +20 dB -6 to +12 dB 0.5 dB Steps Left Input 2 Multi-bit ADC Mono mix, Limiter, Bass, Treble Adjust Attenuator, Boost, Mix -VHP + Pseudo Diff. Input / Left Input 3 Right Input 1 Inverting +VHP Pseudo Diff. Input Multi-bit DAC + - Pseudo Diff. Input / Right Input 3 Right Input 2 ALC - Programmable Mic Bias Control Port Level Shifter http://www.cirrus.com IC or SPI Control IS or Left Justified Serial Audio Input/ Output Copyright Cirrus Logic, Inc. 2014 (All Rights Reserved) Left Line Output Pseudo Diff. Input Serial Audio Port + +1.62 V to +3.63 V Interface Supply Right Headphone Output HPF + Mic Bias Output Left Headphone Output - Right Line Output Ground-Centered Amplifiers FEB '14 DS851F2 CS42L56 SYSTEM FEATURES Audio (11.2896 MHz or 12.288 MHz) or USB (12 MHz) Master Clock Input Low-power Operation - Stereo Anlg. Passthrough: 3.3 mW @1.8 V - Stereo Rec. and Playback: 8.3 mW @1.8 V Headphone Detect Input High Performance 24-bit Converters - Multi-bit Delta-Sigma Architecture Integrated High Efficient Power Management Reduces Power Consumption - Step-down Charge Pump Improves Efficiency - Inverting Charge Pump Accommodates Low System Voltage by Providing Negative Rail for HP/Line Amp - LDO Reg. Provides Low Digital Supply Voltage Digital Power Reduction - Very Low ADC/DAC Oversampling Rate - Bursted Serial Clock Providing up to 24 Bits per Sample Power Down Management - ADC, DAC, CODEC, PGA, DSP Analog & Digital Routing/Mixes - Line/Headphone Out = Analog In (ADC Bypassed) - Line/Headphone Out = ADC Out - Internal Digital Loopback - Mono Mixes IC or SPITM Control Port IS or Left-justified Digital Interface Format Flexible Clocking Options - Master or Slave Operation - Wide Range of Sample Rates Supported APPLICATIONS HDD and Flash-based Portable Audio Players PDAs Personal Media Players Portable Game Consoles Digital Voice Recorders MD Players/Recorders Digital Camcorders Digital Cameras GENERAL DESCRIPTION The CS42L56 is a highly integrated, 24-bit, ultra-lowpower stereo CODEC based on multi-bit delta-sigma modulation. Both the ADC and DAC offer many features suitable for low power portable system applications. The analog input path allows independent channel control of a variety of features. The Programmable Gain Amplifier (PGA) provides analog gain with zero cross transitions. The ADC path includes a digital volume attenuator with soft ramp transitions and a programmable ALC and noise gate monitor the input signals and adjust the volume appropriately. An analog passthrough also exists, accommodating a lower noise, lower power analog in to analog out path to the headphone and line amplifiers, bypassing the ADC and DAC. The DAC output path includes a fixed-function digital signal processing engine. Tone control provides bass and treble adjustment at four selectable corner frequencies. The digital mixer provides independent volume control for both the ADC output and PCM input signal paths, as well as a master volume control. Digital volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. The DAC path also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The Class H stereo headphone amplifier combines the efficiency of an integrated step-down and inverting charge pump with the linearity and low EMI of a Class AB amplifier. A step-down/inverting charge pump operates in two modes: VCP mode or VCP/2) mode. Based on the amplifier's output signal, internal logic automatically adjusts the output of the charge pump, +VHPFILT and -VHPFILT, to optimize efficiency. With these features, the amplifier delivers a ground-centered output with a large signal swing even at low voltages and eliminates the need for external DC-blocking capacitors. These features make the CS42L56 the ideal solution for portable applications which require extremely low power consumption in a minimal amount of space. The CS42L56 is available in a 40-pin QFN package for the Commercial (-40 to +85 C) grade. The CDB42L56 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 93 for complete details. Smart Phones 2 DS851F2 CS42L56 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .............................................................................................................................. 8 1.1 I/O Pin Characteristics .................................................................................................................... 10 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 14 RECOMMENDED OPERATING CONDITIONS ................................................................................... 14 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 14 ANALOG INPUT CHARACTERISTICS ................................................................................................ 14 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 17 HP OUTPUT CHARACTERISTICS ...................................................................................................... 18 LINE OUTPUT CHARACTERISTICS ................................................................................................... 19 ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 21 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...............................21 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 22 SWITCHING SPECIFICATIONS - IC CONTROL PORT ..................................................................... 23 SWITCHING CHARACTERISTICS - SPI CONTROL PORT ................................................................ 24 ANALOG OUTPUT ATTENUATION CHARACTERISTICS .................................................................. 25 DC CHARACTERISTICS ...................................................................................................................... 26 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 27 POWER CONSUMPTION - ALL SUPPLIES = 1.8 V ............................................................................ 28 POWER CONSUMPTION - ALL SUPPLIES = 2.5 V ........................................................................... 29 4. APPLICATIONS ................................................................................................................................... 30 4.1 Overview ......................................................................................................................................... 30 4.1.1 Basic Architecture ................................................................................................................. 30 4.1.2 Line Inputs ............................................................................................................................. 30 4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 30 4.1.4 Fixed-function DSP Engine ................................................................................................... 30 4.1.5 Beep Generator ..................................................................................................................... 30 4.1.6 Power Management .............................................................................................................. 30 4.2 Analog Inputs .................................................................................................................................. 31 4.2.1 Pseudo-differential Inputs ...................................................................................................... 32 4.2.2 Large-scale Inputs ................................................................................................................. 32 4.2.3 Microphone Inputs ................................................................................................................. 34 4.2.3.1 External Passive Components ................................................................................... 34 4.2.4 Optional VCM Buffer ............................................................................................................. 34 4.2.5 Automatic Level Control (ALC) .............................................................................................. 34 4.2.5.1 Attack/Release Time Calculations: ............................................................................ 36 4.3 Analog In to Analog Out Passthrough ............................................................................................ 36 4.4 Analog Outputs .............................................................................................................................. 37 4.5 Class H Amplifier ............................................................................................................................ 38 4.5.1 Power Control Options .......................................................................................................... 39 4.5.1.1 Standard Class AB Mode (setting 01 and 10) ........................................................... 39 4.5.1.2 Adapt to Volume Mode (setting 00) ........................................................................... 39 4.5.1.3 Adapt to Output Mode (setting 11) ............................................................................. 42 4.5.2 Power Supply Transitions ...................................................................................................... 42 4.5.3 Efficiency ............................................................................................................................... 43 4.6 Beep Generator .............................................................................................................................. 44 4.7 Limiter ............................................................................................................................................. 45 4.8 Serial Port Clocking ........................................................................................................................ 46 4.9 Digital Interface Format .................................................................................................................. 49 4.10 Initialization ................................................................................................................................... 49 4.11 Recommended DAC to HP or Line Power Sequence .................................................................. 49 4.11.1 Power-Up Sequence ........................................................................................................... 49 DS851F2 3 CS42L56 4.11.2 Power-Down Sequence ....................................................................................................... 50 4.12 Recommended PGA to HP or Line Power Sequence (Analog Passthrough) .............................. 51 4.12.1 Power-Up Sequence ........................................................................................................... 51 4.12.2 Power-Down Sequence ....................................................................................................... 52 4.13 Control Port Operation .................................................................................................................. 53 4.13.1 SPI Control .......................................................................................................................... 53 4.13.2 IC Control ........................................................................................................................... 53 4.13.3 Memory Address Pointer (MAP) .......................................................................................... 54 4.13.3.1 Map Increment (INCR) ............................................................................................. 54 5. REGISTER QUICK REFERENCE ........................................................................................................ 55 6. REGISTER DESCRIPTION .................................................................................................................. 57 6.1 Device I.D. Register (Address 01h) (Read Only) ............................................................................ 57 6.1.1 Device I.D. (Read Only) ........................................................................................................ 57 6.2 Device Revision Register (Address 02h) (Read Only) ................................................................... 57 6.2.1 Alpha Revision (Read Only) .................................................................................................. 57 6.2.2 Numeric Revision (Read Only) .............................................................................................. 57 6.3 Power Control 1 (Address 03h) ...................................................................................................... 57 6.3.1 Power Down VCM Bias Buffer .............................................................................................. 57 6.3.2 Power Down MIC Bias .......................................................................................................... 58 6.3.3 Power Down ADC Charge Pump .......................................................................................... 58 6.3.4 Power Down ADC x ............................................................................................................... 58 6.3.5 Power Down .......................................................................................................................... 58 6.4 Power Control 2 (Address 04h) ...................................................................................................... 58 6.4.1 Headphone Power Control .................................................................................................... 58 6.4.2 Line Power Control ................................................................................................................ 59 6.5 Clocking Control 1 (Address 05h) ................................................................................................... 59 6.5.1 Master/Slave Mode ............................................................................................................... 59 6.5.2 SCLK Polarity ........................................................................................................................ 59 6.5.3 SCLK Equals MCLK .............................................................................................................. 59 6.5.4 MCLK Pre-Divide ................................................................................................................... 59 6.5.5 MCLK Divide ......................................................................................................................... 60 6.5.6 MCLK Disable ....................................................................................................................... 60 6.6 Clocking Control 2 (Address 06h) ................................................................................................... 60 6.6.1 Clock Ratio Auto-Detect ........................................................................................................ 60 6.6.2 Clock Ratio ............................................................................................................................ 61 6.7 Serial Format (Address 07h) .......................................................................................................... 61 6.7.1 CODEC Digital Interface Format ........................................................................................... 61 6.8 Class H Control (Address 08h) ....................................................................................................... 62 6.8.1 Adaptive Power Adjustment .................................................................................................. 62 6.8.2 Charge Pump Frequency ...................................................................................................... 62 6.9 Misc. Control (Address 09h) ........................................................................................................... 62 6.9.1 Digital MUX ........................................................................................................................... 62 6.9.2 Analog Soft Ramp ................................................................................................................. 63 6.9.3 Analog Zero Cross ................................................................................................................ 63 6.9.4 Digital Soft Ramp .................................................................................................................. 63 6.9.5 Freeze Registers ................................................................................................................... 63 6.10 Status (Address 0Ah) (Read Only) ............................................................................................... 64 6.10.1 HPDETECT Pin Status (Read Only) ................................................................................... 64 6.10.2 Serial Port Clock Error (Read Only) .................................................................................... 64 6.10.3 DSP Engine Overflow (Read Only) ..................................................................................... 64 6.10.4 MIXx Overflow (Read Only) ................................................................................................. 64 6.10.5 ADCx Overflow (Read Only) ............................................................................................... 64 6.11 Playback Control (Address 0Bh) .................................................................................................. 65 6.11.1 Power Down DSP ................................................................................................................ 65 4 DS851F2 CS42L56 6.11.2 HP/Line De-Emphasis ......................................................................................................... 65 6.11.3 Playback Channels B=A ...................................................................................................... 65 6.11.4 Invert PCM Signal Polarity .................................................................................................. 65 6.12 DSP Mute Controls (Address 0Ch) ............................................................................................... 66 6.12.1 ADC Mixer Channel x Mute ................................................................................................. 66 6.12.2 PCM Mixer Channel x Mute ................................................................................................ 66 6.12.3 Master Playback Mute ......................................................................................................... 66 6.13 ADCx Mixer Volume: ADCA (Address 0Dh) & ADCB (Address 0Eh) ........................................... 66 6.13.1 ADC Mixer Channel x Volume ............................................................................................. 66 6.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h) .......................................... 67 6.14.1 PCM Mixer Channel x Volume ............................................................................................ 67 6.15 Analog Input Advisory Volume (Address 11h) .............................................................................. 68 6.15.1 Analog Input Advisory Volume ............................................................................................ 68 6.16 Digital Input Advisory Volume (Address 12h) ............................................................................... 68 6.16.1 Digital Input Advisory Volume ............................................................................................. 68 6.17 Master Volume Control: MSTA (Address 13h) & MSTB (Address 14h) ...................................................................................... 69 6.17.1 Master Volume Control ........................................................................................................ 69 6.18 Beep Frequency & On Time (Address 15h) ................................................................................. 69 6.18.1 Beep Frequency .................................................................................................................. 69 6.18.2 Beep On Time ..................................................................................................................... 70 6.19 Beep Volume & Off Time (Address 16h) ...................................................................................... 70 6.19.1 Beep Off Time ..................................................................................................................... 70 6.19.2 Beep Volume ....................................................................................................................... 71 6.20 Beep & Tone Configuration (Address 17h) ................................................................................... 71 6.20.1 Beep Configuration .............................................................................................................. 71 6.20.2 Treble Corner Frequency .................................................................................................... 71 6.20.3 Bass Corner Frequency ...................................................................................................... 72 6.20.4 Tone Control Enable ........................................................................................................... 72 6.21 Tone Control (Address 18h) ......................................................................................................... 72 6.21.1 Treble Gain .......................................................................................................................... 72 6.21.2 Bass Gain ............................................................................................................................ 72 6.22 ADC & PCM Channel Mixer (Address 19h) .................................................................................. 73 6.22.1 PCM Mix Channel Swap ..................................................................................................... 73 6.22.2 ADC Mix Channel Swap ...................................................................................................... 73 6.23 AIN Reference Configuration, ADC MUX (Address 1Ah) ............................................................. 73 6.23.1 Analog Input 2 x Reference Configuration .......................................................................... 73 6.23.2 Analog Input 1 x Reference Configuration .......................................................................... 73 6.23.3 ADC x Input Select .............................................................................................................. 74 6.24 HPF Control (Address 1Bh) .......................................................................................................... 74 6.24.1 ADCx High-Pass Filter ........................................................................................................ 74 6.24.2 ADCx High-Pass Filter Freeze ............................................................................................ 74 6.24.3 HPF x Corner Frequency .................................................................................................... 74 6.25 Misc. ADC Control (Address 1Ch) ................................................................................................ 75 6.25.1 ADC Channel B=A .............................................................................................................. 75 6.25.2 PGA Channel B=A .............................................................................................................. 75 6.25.3 Digital Sum .......................................................................................................................... 75 6.25.4 Invert ADC Signal Polarity ................................................................................................... 75 6.25.5 ADC Mute ............................................................................................................................ 75 6.26 Gain & Bias Control (Address 1Dh) .............................................................................................. 76 6.26.1 PGA x Preamplifier Gain ..................................................................................................... 76 6.26.2 Boostx ................................................................................................................................. 76 6.26.3 Microphone Bias Output Level ............................................................................................ 76 6.27 PGA x MUX, Volume: PGA A (Address 1Eh) & PGA B (Address 1Fh) ........................................ 76 DS851F2 5 CS42L56 6.27.1 PGA x Input Select .............................................................................................................. 76 6.27.2 PGAx Volume ...................................................................................................................... 77 6.28 ADCx Attenuator Control: ADCAATT (Address 20h) & ADCBATT (Address 21h) ....................... 77 6.28.1 ADCx Volume ...................................................................................................................... 77 6.29 ALC Enable & Attack Rate (Address 22h) .................................................................................... 78 6.29.1 ALCx .................................................................................................................................... 78 6.29.2 ALC Attack Rate .................................................................................................................. 78 6.30 ALC Release Rate (Address 23h) ................................................................................................ 78 6.30.1 ALC Limit All Channels ........................................................................................................ 78 6.30.2 ALC Release Rate ............................................................................................................... 79 6.31 ALC Threshold (Address 24h) ...................................................................................................... 79 6.31.1 ALC Maximum Threshold .................................................................................................... 79 6.31.2 ALC Minimum Threshold ..................................................................................................... 80 6.32 Noise Gate Control (Address 25h) ............................................................................................... 80 6.32.1 Noise Gate All Channels ..................................................................................................... 80 6.32.2 Noise Gate Enable .............................................................................................................. 80 6.32.3 Noise Gate Threshold and Boost ........................................................................................ 81 6.32.4 Noise Gate Delay Timing .................................................................................................... 81 6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 26h) ................................................ 81 6.33.1 ALCx Soft Ramp Disable ..................................................................................................... 81 6.33.2 ALCx Zero Cross Disable .................................................................................................... 81 6.33.3 Limiter Soft Ramp Disable ................................................................................................... 81 6.34 Automute, Line & HP MUX (Address 27h) ................................................................................... 82 6.34.1 Auto Mute ............................................................................................................................ 82 6.34.2 Line Input Select .................................................................................................................. 82 6.34.3 Headphone Input Select ...................................................................................................... 82 6.35 Headphone Volume Control: HPA (Address 28h) & HPB (Address 29h) ..................................... 82 6.35.1 Headphone Channel x Mute ................................................................................................ 82 6.35.2 Headphone Volume Control ................................................................................................ 83 6.36 Line Volume Control: LINEA (Address 2Ah) & LINEB (Address 2Bh) .......................................... 83 6.36.1 Line Channel x Mute ........................................................................................................... 83 6.36.2 Line Volume Control ............................................................................................................ 83 6.37 Limiter Min/Max Thresholds (Address 2Ch) ................................................................................. 84 6.37.1 Limiter Maximum Threshold ................................................................................................ 84 6.37.2 Limiter Cushion Threshold .................................................................................................. 84 6.38 Limiter Control, Release Rate (Address 2Dh) .............................................................................. 85 6.38.1 Peak Detect and Limiter ...................................................................................................... 85 6.38.2 Peak Signal Limit All Channels ........................................................................................... 85 6.38.3 Limiter Release Rate ........................................................................................................... 85 6.39 Limiter Attack Rate (Address 2Eh) ............................................................................................... 86 6.39.1 Limiter Attack Rate .............................................................................................................. 86 7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 87 7.1 Power Supply ................................................................................................................................. 87 7.2 Grounding ....................................................................................................................................... 87 7.3 QFN Thermal Pad .......................................................................................................................... 87 8. ANALOG VOLUME NON-LINEARITY (DNL & INL) ............................................................................ 88 9. ADC & DAC DIGITAL FILTERS .......................................................................................................... 89 10. PARAMETER DEFINITIONS .............................................................................................................. 90 11. PACKAGE DIMENSIONS .................................................................................................................. 91 THERMAL CHARACTERISTICS .......................................................................................................... 91 12. ORDERING INFORMATION .............................................................................................................. 92 13. REFERENCES .................................................................................................................................... 92 14. REVISION HISTORY .......................................................................................................................... 92 6 DS851F2 CS42L56 LIST OF FIGURES Figure 1.Typical Connection Diagram - Four Pseudo-Differential Analog Inputs ...................................... 11 Figure 2.Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs ... 12 Figure 3.Typical Connection Diagram - Six Single-Ended Analog Inputs ................................................. 13 Figure 4.CMRR Test Configuration ........................................................................................................... 16 Figure 5.AINxREF Input Voltage Test Configuration ................................................................................ 16 Figure 6.HP Output Test Configuration ..................................................................................................... 20 Figure 7.Line Output Test Configuration ................................................................................................... 20 Figure 8.Serial Port Timing (Slave Mode) ................................................................................................. 22 Figure 9.Serial Port Timing (Master Mode) ............................................................................................... 22 Figure 10.IC Control Port Timing ............................................................................................................. 23 Figure 11.Control Port Timing - SPI Format .............................................................................................. 24 Figure 12.Power Consumption Test Configuration ................................................................................... 27 Figure 13.Analog Input Signal Flow .......................................................................................................... 31 Figure 14.Stereo Pseudo-Differential Input ............................................................................................... 32 Figure 15.Analog Input Attenuation ........................................................................................................... 33 Figure 16.Example Analog Input Attenuation ............................................................................................ 33 Figure 17.MIC Input Mix w/Common Mode Rejection ............................................................................... 34 Figure 18.ALC Operation .......................................................................................................................... 35 Figure 19.DSP Engine Signal Flow ........................................................................................................... 37 Figure 20.Analog Output Stage ................................................................................................................. 38 Figure 21.Class H Volume-Adapt Paths ................................................................................................... 39 Figure 22.Volume Sum Effects ................................................................................................................. 40 Figure 23.Channel/Amp Effect .................................................................................................................. 40 Figure 24.HP/Line Channel Effects ........................................................................................................... 41 Figure 25.VHPFILT Transitions ................................................................................................................. 42 Figure 26.VHPFILT Hysteresis ................................................................................................................. 43 Figure 27.Class H Power to Load vs. Power from VCP Supply - 32 W .................................................... 43 Figure 28.Class H Power to Load vs. Power from VCP Supply - 16 W .................................................... 44 Figure 29.Beep Configuration Options ...................................................................................................... 45 Figure 30.Peak Detect & Limiter ............................................................................................................... 46 Figure 31.Serial Port Timing in Master Mode ............................................................................................ 48 Figure 32.IS Format ................................................................................................................................. 49 Figure 33.Left-Justified Format ................................................................................................................. 49 Figure 34.Control Port Timing in SPI Mode .............................................................................................. 53 Figure 35.Control Port Timing, IC Write ................................................................................................... 54 Figure 36.Control Port Timing, IC Read ................................................................................................... 54 Figure 37.PGA Step Size vs. Volume Setting ........................................................................................... 88 Figure 38.PGA Output Volume vs. Volume Setting .................................................................................. 88 Figure 39.HP/Line Step Size vs. Volume Setting ...................................................................................... 88 Figure 40.HP/Line Output Volume vs. Volume Setting ............................................................................. 88 Figure 41.ADC Frequency Response ....................................................................................................... 89 Figure 42.ADC Stopband Rejection .......................................................................................................... 89 Figure 43.ADC Transition Band ................................................................................................................ 89 Figure 44.ADC Transition Band Detail ...................................................................................................... 89 Figure 45.DAC Frequency Response ....................................................................................................... 89 Figure 46.DAC Stopband .......................................................................................................................... 89 Figure 47.DAC Transition Band ................................................................................................................ 89 Figure 48.DAC Transition Band (Detail) .................................................................................................... 89 DS851F2 7 CS42L56 Pin Name SDIN SCLK MCLK SDOUT VL VDFILT VLDO RESET HPDETECT AIN2B AIN2REF/AIN3B 40 39 38 37 36 35 34 33 32 31 1. PIN DESCRIPTIONS SDIN 1 30 AIN2A LRCK 2 29 AIN1B SDA/CDIN 3 28 AIN1REF/AIN3A SCL/CCLK 4 27 AIN1A AD0/CS 5 26 MICBIAS VCP 6 25 AFILTB FLYP 7 24 AFILTA +VHPFILT 8 23 VQ 22 FILT+ 21 AGND # 1 19 20 LINEOUTB VA 16 TSTN LINEREF 15 TSTN 18 14 HPOUTB 17 13 HPREF LINEOUTA 12 10 HPOUTA FLYN 11 9 Top-Down (Through-Package) View 40-Pin QFN Package -VHPFILT FLYC GND/Thermal Pad Pin Description Serial Audio Data Input (Input) - Input for two's complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data lines. Serial Control Data (Input/Output) - SDA is the bidirectional data pin for the IC control interface. CDIN is the input data pin for the SPI control interface. Serial Control Port Clock (Input) - Serial clock for the IC and SPI control interfaces. Chip Address (IC) / Chip Select (SPI) (Input) - For IC operation, this pin must remain static high or low. For SPI, CS is the chip-select pin. LRCK 2 SDA/CDIN 3 SCL/CCLK 4 AD0/CS 5 VCP 6 Step-Down Charge Pump Power (Input) - Power supply for the step-down charge pump. FLYP 7 Charge Pump Cap Positive Node (Output) - Positive node for the step-down charge pump's flying capacitor. +VHPFILT 8 Step-Down Charge Pump Filter Connection (Output) - Power supply from the step-down charge pump that provides the positive rail for the headphone and line amplifiers FLYC 9 Charge Pump Cap Common Node (Output) - Common positive node for the step-down and inverting charge pumps' flying capacitors. FLYN 10 Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump's flying capacitor. 8 DS851F2 CS42L56 -VHPFILT 11 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the headphone and line amplifiers. HPOUTA HPOUTB 12 14 Headphone Audio Output (Output) - The full-scale output level is specified in "HP Output Characteristics" on page 19. HPREF 13 Pseudo Diff. Headphone Output Reference (Input) - Ground reference for the headphone amplifiers TSTN 15 16 Test Input (Input) - This pin is an input used for test purposes only and should be tied to ground for normal operation. LINEOUTA LINEOUTB 17 19 Line Audio Output (Output) - The full-scale output level is specified in "Line Output Characteristics" on page 20. LINEREF 18 Pseudo Diff. Line Output Reference (Input) - Ground reference for the line amplifiers. VA 20 Analog Power (Input) - Power supply for the internal analog section. AGND 21 Analog Ground (Input) - Ground reference for the internal analog section. FILT+ 22 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VQ 23 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage. AFILTA AFILTB 24 25 Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs. 26 Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. AIN1A AIN1B AIN2A AIN2B 27 29 30 32 Analog Inputs 1 & 2 (Input) - The full-scale level is specified in "Analog Input Characteristics" on page 14. AIN1REF/AIN3A AIN2REF/AIN3B 28 31 Pseudo Differential Analog Input Reference/Analog Input 3 (Input) - Configurable as the ground reference for the programmable gain amplifiers (PGA) or as additional analog inputs. The full-scale level is specified in "Analog Input Characteristics" on page 14. HPDETECT 33 Headphone Detect (Input) - The HPDETECT circuit can be set to control the power down of the left and/or right channel of the line and/or headphone outputs as described in "Headphone Power Control" on page 59 and "Line Power Control" on page 60 and/or cause an interrupt. This pin is debounced such that the signal must remain stable in the new state for approximately 10 ms before a change is passed on to the internal HPDETECT circuit. RESET 34 Reset (Input) - The device enters a low power mode when this pin is driven low. VLDO 35 Low Dropout Regulator (LDO) Power (Input) - Power supply for the LDO regulator. VDFILT 36 Low Dropout Regulator (LDO) Filter Connection (Output) - Power supply from the LDO regulator that provides the low voltage power to the digital section. VL 37 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and IC control port. MICBIAS SDOUT 38 Serial Audio Data Output (Output) - Output for two's complement serial audio data. MCLK 39 Master Clock (Input) - Clock source for the delta-sigma modulators. SCLK 40 Serial Clock (Input/Output) - Serial clock for the serial audio interface. GND/ Thermal Pad DS851F2 - Ground reference for the internal charge pump and digital section; thermal relief pad. 9 CS42L56 1.1 I/O Pin Characteristics Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage. Power Supply VL VA 10 Pin Name I/O RESET SCL SDA AD0 CCLK CDIN CS MCLK Input Input Input/Output Input Input Input Input Input LRCK Input/Output SCLK Input/Output SDOUT Output SDIN HPDETECT Input Input Internal Connections Weak Pull-up (~1 M Weak Pull-up (~1 M Weak Pull-up (~1 M - Driver Receiver CMOS/Open Drain - 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V 1.8 V - 3.3 V, CMOS - - 1.8 V - 3.3 V 1.8 V - 2.5 V, with Hysteresis DS851F2 CS42L56 2. TYPICAL CONNECTION DIAGRAMS 1 F ** ** VDFILT 0.1 F VLDO ** +1.65 V to +2.75 V 0.1 F VA 47 k HPREF Note 1 +VHPFILT ** 2.2 F HPOUTB HPOUTA ** 33 Headphone Out Left & Right 33 ** 0.1 F Note 1 +1.65 V to +2.75 V HPDETECT VCP 2.2 F 0.1 F ** CS42L56 Note 2 2.2 F ** 2. 2 F ** FLYP LINEOUTA FLYC LINEOUTB Note 1 ** 3300 pF Rext LPF is Optional * LINEREF FLYN 2.2 F 562 Rex t * 3300 pF Line Level Out Left & Right 562 -VHPFILT Note 4 AIN1A AIN1REF 1800 pF 1 F ** MCLK ** 1 F * ** 1800 pF AIN1B SCLK * 100 100 k 100 100 k 100 100 k Analog Input 1 1 F LRCK SDIN Digital Audio Processor SDOUT RESET SCL\CCLK ** AIN2A 1 F 1800 pF * 1 F AIN2REF SDA\CDIN ** AIN2B 1800 pF * ** 100 Analog Input 2 100 k 1 F AD0\CS Rp Rp +1.65 V to +3.63 V VL ** Note 3 AGND 0.1 F * 1000 pF TSTN TSTN GND/Thermal Pad AFILTA AFILTB VQ FILT+ * 1000 pF ** ** 2.2 F 2.2 F * NPO /C0G dielectric capacitors. ** Low ESR, X7R/X5R dielectric capacitors. Notes: Notes: 1. The headphone amplifier's output power and distortion are rated the nominal shown. Largershown capacitance reduces the ripple on the internal 1. The headphone amplifier's output powerusing and distortion are ratedcapacitance using the nominal capacitance . Larger capacitance amplifiers' supplies and in turn reduces distortion at high output Smaller capacitance not sufficiently reducesthe the amplifier's ripple on the internal amplifiers' supplies andpower in turn levels. reduces the amplifier's distortion atmay high output power levels.reduce ripple to achieve the Smaller capacitance may not sufficiently reduce ripple to achieve the rated output power and distortion . Since the actual value rated output power and distortion. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the of typical X7R/Xbe 5Rselected ceramic capacitors deviates from the nominal value by a and percentage specified in the manufacturer's manufacturer's data sheet, capacitors should based on the minimum output power maximum distortion required. data sheet, capacitors should be selected based on the minimum output power and maximum distortion required 2. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown and using the .default charge pump switching frequency. 2. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown and using the default The required capacitance follows an inverse relationship with the charge pump's switching frequency. When increasing the switching frequency, the capacitance charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump's switching may decrease; when lowering thefrequency. switching frequency, mustthe increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates When increasingthe the capacitance switching frequency, capacitance may decrease; when lowering the switching frequency, from the nominal value by a percentage specified in increase the manufacturer's capacitors shouldcapacitors be selected based on nominal the minimum output power, maximum the capacitance must . Since the actualdata valuesheet, of typical X7R/X5R ceramic deviates from the value by a percentage in therequired. manufacturer's data sheet, capacitors should be selected based on the minimum output distortion and maximum charge pump switchingspecified frequency , maximum distortion and maximum charge pump switching frequency required. 3. Additional bulk capacitance maypower be added to improve PSRR at low frequencies. 3. Additional bulk capacitance may be added to improve PSRR at low frequencies. 4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as close as possible to the inputs. They 4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as are only needed when the PGA (Programmable Gain Amplifier) is bypassed. close as possible to the inputs. They are only needed when the PGA (Programmable Gain Amplifier ) is bypassed. Figure 1. Typical Connection Diagram - Four Pseudo-Differential Analog Inputs DS851F2 11 CS42L56 1 F 1 F ** ** ** VDFILT VDFILT 0.1 F **0.1 F ** VLDO VLDO VA +1.65 V to +2.75 V 0.1 F +1.65 V to +2.75 V ** F 0.1 VA 47 k HPREF HPREF Note 1 Note 1 2.2 F 0.1 F 0.1 F +VHPFILT +VHPFILT ** ** 2.2 F ** 33 ** HPOUTB HPOUTB HPOUTA HPOUTA ** +1.65 V to +2.75 V CS42L56 LINEOUTA 2.2 F ** 2.2 F ** 2. 2 F ** FLYP FLYP 2.2 F ** 3300 pF FLYC FLYN LINEOUTB MICBIAS -VHPFILT -VHPFILT 1 F 562 Note 4 1 F 1800 pF 1 F 1 F AIN1B ** * * 1800 pF SDOUT SDOUT RESET RESET SCL\CCLK SCL\CCLK AD0\CS Analog Input 1 100 k 100 Microphone 2 Note 5 ** * 1 F 1800 pF AIN2REF * AIN2B 100 ** 1800 pF * ** 1800 pF AIN2B 100 1 F 1 F * ** Left 100 k Analog Analog Input 2 100 k 100 k 100 Note 4 AIN3B 1800 pF 1 F ** * Rp 1 F VL 100 Input 2 100 k 100 1 F Rp ** ** RL Note1800 4 pF** AIN2A SDA\CDIN AD0\CS 0.1 F 100 k Note 6 1 F AIN2A SDA\CDIN 0.1 F Microphone 1 100 1 F 1 F SDIN SDIN ** Line Level Out Left & Right RL AIN1B LRCK LRCK +1.65 V to +3.63 V Rex t ** SCLK SCLK Rp Rext Note 5 MCLK MCLK +1.65 V to +3.63 V Line Level Out Left & Right * 3300 pF AIN1A AIN1REF AIN1REF Rp Rext LINEREF AIN1A DigitalAudio Audio Digital Processor Processor Rext LPF is Optional * 562*3300 pF LINEOUTA LINEOUTB 3300 pF 562 LPF is Optional * FLYC Note 1 Note 1** 562 LINEREF FLYN 2.2 F 33 ** 0.1 F HPDETECT VCP ** Note 2 2.2 F ** Note 2 Headphone Out Headphone Out Left & Right Left & Right HPDETECT VCP 2.2 F 2.2 F ** 33 33 0.1 F Note 1 Note 1 +1.65 V to +2.75 V 47 k 100 k Right Analog Input 2 Analog Input 3 Note 3 VL Note 3 AGND AGND AFILTA AFILTA AFILTB VQ AFILTB FILT+ VQ TSTN TSTN TSTN TSTN GND/Thermal Pad GND/Thermal Pad FILT+ * ** * 1000 pF * 1000 pF 1000 pF * 1000 pF 2.2 F ** ** 2.2 F ** 2.2 F 2.2 F * NPO /C0G dielectric capacitors. ** Low ESR, X7R/X5R dielectric capacitors. * NPO /C0G dielectric capacitors. ** Low ESR, X7R/X5R dielectric capacitors. Notes: 1. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown. Larger capacitance reduces the ripple on the internal amplifiers' supplies and in turn reduces the amplifier's distortion at high output power levels. Notes: Smaller capacitanceNotes: may not sufficiently reduce ripple to achieve the rated output power and distortion . Since the actual value of typical X7 R/X5R ceramic capacitors deviates from the nominal value bythe a percentage specified thenominal manufacturer's data shown 1. The headphone amplifier's output powerusing and distortion are rated usinginthe capacitance . Larger capacitance 1. The headphone amplifier's output power and distortion are rated nominal capacitance shown. Larger capacitance reduces the ripple on the internal sheet, capacitors should be selected based on internal the minimum output supplies power andand maximum distortion required . reduces the ripple on the amplifiers' in turn reduces the amplifier's distortion atmay high output power levels.reduce ripple to achieve the amplifiers' supplies and in turn reduces the amplifier's distortion at high output power levels.shown Smaller capacitance not sufficiently 2. The headphone amplifier's output powermay and distortion are rated using ripple the nominal capacitance and power using the default Smaller capacitance not sufficiently reduce to achieve the rated output and distortion . Since the actual value rated output power and distortion. Since the actual value of typicaldeviates X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the charge pump switching frequency. The capacitance an inverse relationship pump's switching of typical X7R/X 5Rrequired ceramic capacitorsfollows from the nominal with valuethe bycharge a percentage specified in the manufacturer's data When increasing the switching frequency,based the capacitance may decrease; output when lowering the and switching frequency, distortion required. manufacturer's datafrequency. sheet, capacitors beshould selected on the minimum power maximum sheet,should capacitors be selected based on the minimum output power and maximum distortion required. the capacitance must increase . Since the actual value of typical X 7R/X5 R ceramic capacitors deviates from the nominal value 2. The headphone amplifier's output power and distortion are rated the nominal capacitance shown and using theand default charge 2. The headphone amplifier's output powerusing and distortion are rated using the nominal capacitance shown using the defaultpump switching frequency. by a percentage specified in the manufacturer's data sheet, capacitors should be selected based on the minimum output charge pump switching frequency. The capacitance follows an inverse relationship with the charge pump's switchingfrequency, the capacitance The required capacitance followsdistortion an inverse relationship withswitching the required charge pump's frequency. When increasing the switching power, maximum and maximum charge pump frequency requiredswitching . frequency. When increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, capacitance mayfrequency, be added to improve PSRR at low frequencies. may decrease; when3. Additional loweringbulk the switching the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates the capacitance must . Since theswitched actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value 4. These serve as a charge reservoir the internal capacitor ADC modulators and should be placed as from the nominal value by acapacitors percentage specified in increase the for manufacturer's data sheet, capacitors should be selected based on the minimum output power, maximum a inputs percentage specified in thewhen manufacturer's data sheet, capacitors should be selected based on the minimum output close as possible tobythe . They are only needed the PGA (Programmable Gain Amplifier ) is bypassed. distortion and maximum charge pump switching frequency required. , maximum distortion charge microphones, pump switching frequency required . 5. The value of RL, apower current-limiting resistor used and with maximum electret condenser is dictated by the microphone 3. Additional bulk capacitance may3. be addedbulk to capacitance improve PSRR low to frequencies. cartridge. Additional may beat added improve PSRR at low frequencies. The negative terminal ofreservoir thecapacitors microphone inputs to reservoir the ground pinthe of the microphone cartridge . Gain is applied onlybe placed 4. These asconnects a charge for internal switched capacitor ADC modulators and should placedas aspossible to the inputs. They 4. These capacitors 6.serve as a charge forserve the internal switched capacitor ADC modulators and should asbeclose to the positive terminal . as possible to the inputs. They are only needed when the PGA (Programmable Gain Amplifier ) is bypassed. close are only needed when the PGA (Programmable Gain Amplifier) is bypassed. 5. The value of RL, a current-limiting resistor used with electret condenser microphones, is dictated by the microphone cartridge. 6. The negative terminal of the microphone inputs connects to the ground pin of the microphone cartridge. Gain is applied only to the positive terminal. Figure 2. Typical Connection Diagram - Two Pseudo-Differential / Three Single-Ended Analog Inputs 12 DS851F2 CS42L56 1 F ** ** VDFILT 0.1 F VLDO ** +1.65 V to +2.75 V 0.1 F VA 47 k HPREF 0.1 F +VHPFILT Note 1 ** 2.2 F HPOUTB HPOUTA ** 33 Headphone Out Left & Right 33 ** 0.1 F Note 1 +1.65 V to +2.75 V VCP 2.2 F ** HPDETECT CS42L56 LINEOUTA Note 2 2.2 F ** 2.2 F ** 562 3300 pF FLYP LINEOUTB FLYC R ext LPF is Optional * LINEREF R ext * 3300 pF Line Level Out Left & Right 562 FLYN 2.2 F ** Note 4 AIN1A Note 1 1800 pF -VHPFILT * ** 1 F * ** 1800 pF AIN1B 100 100 k 100 k 100 1 F Note 4 AIN2A 1800 pF MCLK ** * * AIN2B SCLK ** 1800 pF 100 100 k 100 k 100 1 F LRCK SDIN Digital Audio Processor 1 F SDOUT Left Analog Input 1 Right Analog Input 1 Left Analog Input 2 Right Analog Input 2 Microphone 1 AIN3A 1 F RESET SCL\CCLK SDA\CDIN MICBIAS RL 1 F AD0\CS Note 5 RL AIN3B 1 F Rp Rp +1.65 V to +3.63 V Microphone 2 Note 6 VL ** 0.1 F Note 3 AGND TSTN * TSTN 1000 pF GND/Thermal Pad AFILTA AFILTB VQ FILT+ * 1000 pF ** ** 2.2 F 2.2 F * NPO /C0G dielectric capacitors. ** Low ESR, X7R/X5R dielectric capacitors. Notes: 1. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown. Larger capacitance Notes: reduces the ripple on the internal amplifiers' supplies and in turn reduces the amplifier's distortion at high output power levels. 1. The headphoneSmaller amplifier's output and distortion are ratedtheusing the nominal capacitance Larger capacitance reduces the ripple on the internal capacitance may power not sufficiently reduce ripple to achieve rated output power and distortion . Since theshown. actual value amplifiers' suppliesof and the amplifier's distortion atvalue highbyoutput power levels. Smaller capacitance may not sufficiently reduce ripple to achieve the typicalinX7turn R/X5Rreduces ceramic capacitors deviates from the nominal a percentage specified in the manufacturer's data sheet, capacitors should be selected based on the minimum output power and maximum distortion required . rated output power and distortion. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the 2. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown and using the default manufacturer's data sheet, capacitors should be selected based on the minimum output power and maximum distortion required. charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump's switching 2. The headphonefrequency. amplifier's power and distortion are rated using the nominal capacitance shown and using the default charge pump switching frequency. Whenoutput increasing the switching frequency, the capacitance may decrease ; when lowering the switching frequency, the capacitance mustan increase . Sincerelationship the actual value with of typical R ceramic capacitors deviates from the nominal valueincreasing the switching frequency, the capacitance The required capacitance follows inverse theX7R/X5 charge pump's switching frequency. When by a percentage specified in the manufacturer's data sheet, capacitors should be selected based on the minimum output may decrease; when lowering the switching frequency, the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates power, maximum distortion and maximum charge pump switching frequency required. from the nominal value by abulk percentage intothe manufacturer's data sheet, capacitors should be selected based on the minimum output power, maximum 3. Additional capacitance specified may be added improve PSRR at low frequencies. 4. These charge capacitorspump serve asswitching a charge reservoir for the internal switched capacitor ADC modulators and should be placed as distortion and maximum frequency required. close as possible to the inputs. They are only needed when the PGA (Programmable Gain Amplifier ) is bypassed. 3. Additional bulk capacitance may be added to improve PSRR at low frequencies. 5. The value of RL, a current-limiting resistor used with electret condenser microphones, is dictated by the microphone 4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as close as possible to the inputs. They cartridge. are only needed when PGA (Programmable is bypassed. 6. The the negative terminal of the microphoneGain inputsAmplifier) connects to the ground pin of the microphone cartridge. Gain is applied only positive terminal. resistor used with electret condenser microphones, is dictated by the microphone cartridge. 5. The value of R ,toathecurrent-limiting L 6. The negative terminal of the microphone inputs connects to the ground pin of the microphone cartridge. Gain is applied only to the positive terminal. Figure 3. Typical Connection Diagram - Six Single-Ended Analog Inputs DS851F2 13 CS42L56 3. CHARACTERISTIC AND SPECIFICATION TABLES RECOMMENDED OPERATING CONDITIONS GND = AGND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Analog Charge Pump LDO Regulator for Digital Serial/Control Port Interface Ambient Temperature (Note 1) (Note 1) Commercial - CNZ Symbol Min Max Units VA VCP VLDO VL TA 1.62 1.62 1.62 1.62 -40 2.75 VA 2.75 3.63 +85 V V V V C ABSOLUTE MAXIMUM RATINGS GND = AGND = 0 V; all voltages with respect to ground. Parameters Symbol DC Power Supply Analog, Charge Pump, LDO VA, VCP, VLDO Serial/Control Port Interface VL Input Current (Note 2) Iin External Voltage Applied to Analog Input (Note 3) VIN Min Max Units -0.3 -0.3 AGND-0.3 3.0 4.0 10 VA+0.3 V V mA V External Voltage Applied to Analog Output (Note 4) VIN -VHPFILT - 0.3 +VHPFILT + 0.3 V External Voltage Applied to Digital Input Ambient Operating Temperature (power applied) Storage Temperature (Note 3) VIND TA Tstg -0.3 -50 -65 VL+ 0.3 +115 +150 V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Due to the existence of parasitic body diodes between VCP and VA, current flows from VCP to VA whenever the VA power supply is lower than VCP. This causes a "back-powering" effect on the VA power supply rails internal to the part; therefore, VA should be maintained at an equal or greater voltage than VCP at all times. While "back-powering" does not have any adverse effects on device operation with respect to performance and reliability, it does lead to extra power consumption and therefore should be avoided. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. 4. VHPFILT is specified in "DC Characteristics" on page 27. ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement signal path is AINxx to SDOUT. VA = 2.5 V Parameter Min Typ VA = 1.8 V Max Min Typ Max Unit Analog In to ADC (PGA bypassed) 14 DS851F2 CS42L56 ANALOG INPUT CHARACTERISTICS (CONTINUED) Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement signal path is AINxx to SDOUT. Dynamic Range A-weighted 89 95 unweighted 86 92 Total Harmonic Distortion + Noise -1 dBFS -85 -79 -20 dBFS -72 -60 dBFS -32 -26 Analog In to PGA to ADC, PREAMPx[1:0]=00 (0 dB Gain + PGA Setting) Dynamic Range PGA Setting: 0 dB A-weighted 88 94 unweighted 85 91 PGA Setting: +12 dB A-weighted 81 87 unweighted 78 84 Total Harmonic Distortion + Noise -87 -81 PGA Setting: 0 dB -1 dBFS -60 dBFS -31 -25 PGA Setting: +12 dB -1 dBFS -83 -77 Common Mode Rejection (Note 5) 66 Analog In to PGA to ADC, PREAMPx[1:0]=01 (+10 dB Gain + PGA Setting) Dynamic Range PGA Setting: 0 dB A-weighted 91 unweighted 88 PGA Setting: +12 dB A-weighted 81 unweighted 78 Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -77 PGA Setting: +12 dB -1 dBFS -64 Common Mode Rejection (Note 5) 66 Analog In to PGA to ADC, PREAMPx[1:0]=10 (+20 dB Gain + PGA Setting) Dynamic Range PGA Setting: 0 dB A-weighted 85 unweighted 82 PGA Setting: +12 dB A-weighted 73 unweighted 70 Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -71 PGA Setting: +12 dB -1 dBFS -63 Common Mode Rejection (Note 5) 58 DC Accuracy Interchannel Gain Mismatch 0.2 Gain Drift 100 Offset Error (Note 6) 352 Input Interchannel Isolation (1 kHz) (Note 7) 90 HP Amp to Analog Input Isolation RL = 3 k 90 83 RL = 16 Full-scale Input Voltage DS851F2 86 83 - 92 89 -85 -69 -29 -79 -23 dB dB dB dB dB 85 82 78 75 91 88 84 81 - dB dB dB dB - -85 -28 -81 66 -79 -22 -75 - dB dB dB dB - 88 86 78 75 - dB dB dB dB - -77 -64 66 - dB dB dB - 82 79 70 67 - dB dB dB dB - -71 -63 58 - dB dB dB - 0.2 100 352 - dB ppm/C LSB - 90 90 83 - dB dB dB ADC 0.76*VA 0.80*VA 0.84*VA 0.76*VA 0.80*VA 0.84*VA PGA (-1.5 dB) 0.95*VA 0.95*VA PGA (0 dB) 0.78*VA 0.82*VA 0.86*VA 0.78*VA 0.82*VA 0.86*VA PGA (+12 dB) 0.198*VA 0.198*VA Vpp Vpp Vpp 15 CS42L56 ANALOG INPUT CHARACTERISTICS (CONTINUED) Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz. Measurement signal path is AINxx to SDOUT. Full-scale Signal Input Voltage (Note 8) ADC 0.76*VA 0.80*VA 0.84*VA 0.76*VA 0.80*VA 0.84*VA PGA=-1.5 dB, PREAMPx[1:0]=00 0.95*VA 0.95*VA PGA=0 dB, PREAMPx[1:0]=00 0.78*VA 0.82*VA 0.86*VA 0.78*VA 0.82*VA 0.86*VA PGA=+12 dB, PREAMPx[1:0]=00 0.198*VA 0.198*VA PGA=0 dB, PREAMPx[1:0]=01 0.259*VA 0.259*VA PGA=0 dB, PREAMPx[1:0]=10 0.082*VA 0.082*VA PGA=+12 dB, PREAMPx[1:0]=01 0.064*VA 0.064*VA PGA=+12 dB, PREAMPx[1:0]=10 0.020*VA 0.020*VA AINxREF Input Voltage (Pseudo-Diff Mode)(Note 10) 0.300 0.300 Input Impedance (Note 9) ADC 60 60 PGA, PREAMPx[1:0]=00 40 40 PGA, PREAMPx[1:0]=01 12.65 12.65 PGA, PREAMPx[1:0]=10 4 4 DC Voltage at Analog Input (Pin Floating) VA/2 VA/2 - Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp k k k k V Notes: 5. See Figure 4. 6. SDOUT Code with HPFx=1 and HPFRZx=0. 7. See "Parameter Definitions" on page 91. 8. The full scale input voltage values given in the table refers to the maximum voltage difference between the AINxx and AINxREF pins. Providing an input signal at these pins that exceeds the full scale input voltage may result in clipping the analog input. 9. Measured between AINxx and AGND. 10. Providing a signal level higher than 300 mVpp on the AINxREF pin may degrade the PGA linearity and adversely affect analog input performance. See Figure 5. 100 mVPP, 25 Hz 100 AINxA 1 F AINxREF Figure 4. CMRR Test Configuration AINxx 100 300 mVPP, 1 kHz 1 F 1 F AINxREF Figure 5. AINxREF Input Voltage Test Configuration 16 DS851F2 CS42L56 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 11) Frequency Response (20 Hz to 20 kHz) Passband to -0.05 dB corner to -3 dB corner Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) (Note 12) Passband to -3.0 dB corner to -0.05 dB corner Frequency Response Phase Deviation @ 20 Hz Filter Settling Time (Note 13) Min Typ Max Unit -0.07 0.52 33 - 0.421 0.495 4.3/Fs +0.02 - dB Fs Fs Fs dB s - 1.87 17.15 5.3 0.15 - Hz Hz dB Deg s 105/Fs Notes: 11. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 41 to Note 44 on page 90) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz. 12. Characteristics are based on the default setting in register "HPF Control (Address 1Bh)" on page 75. 13. Settling time decreases at higher corner frequency settings. DS851F2 17 CS42L56 HP OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 k CL = 150 pFfor a line load, and test load RL = 16 CL = 150 pF for a headphone load (See Figure 6 on page 21); Measurement signal path is SDIN to HPOUTx. VA = 2.5 V Parameter (Note 15) Min Typ VA = 1.8 V Max Min Typ Max Unit Line Load RL = 10 k(+2 dB Analog Gain) (Note 14) Dynamic Range 18 to 24-Bit A-weighted 98 90 96 92 unweighted 89 95 87 93 16-Bit A-weighted 96 94 unweighted 94 92 Total Harmonic Distortion + Noise (Note 16) 18 to 24-Bit 0 dB -84 -78 -85 -79 -20 dB -75 -73 -60 dB -35 -30 -33 -28 16-Bit 0 dB -82 -83 -20 dB -74 -72 -60 dB -34 -32 Full-scale Output Voltage (Note 17) 1.56*VA 1.64*VA 1.73*VA 1.56*VA 1.64*VA 1.73*VA HP Load RL = 16 (-4 dB Analog Gain) (Note 14) Dynamic Range 18 to 24-Bit A-weighted 89 95 88 94 unweighted 92 85 91 86 16-Bit A-weighted 93 92 unweighted 90 89 Total Harmonic Distortion + Noise (Note 16) -75 -69 -75 -69 Full-scale Output Voltage (Note 17) 0.76*VA 0.82*VA 0.88*VA 0.76*VA 0.82*VA 0.88*VA Output Power (Note 16) 32 17 Other Characteristics for RL = 16 or 10 k Interchannel Isolation (Note 17) Interchannel Gain Mismatch Output Offset (Note 17) Gain Drift Load Resistance (RL) Load Capacitance (CL) 18 10 k 16 (Note 17) Mute 0 dB Analog Gain (Note 17) (Note 17) (Note 17) dB dB dB dB dB dB dB dB dB dB VPP dB dB dB dB dB VPP mW 16 90 90 0.1 0.5 3.9 100 - 0.28 1.0 15.1 - 16 90 90 0.1 0.5 3.1 100 - 0.28 1.0 11.4 - dB dB dB mV mV ppm/C - - 150 - - 150 pF DS851F2 CS42L56 LINE OUTPUT CHARACTERISTICS Test conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 k CL = 150 pF (see Figure 6 on page 21); Measurement signal path is SDIN to LINEOUTx. VA = 2.5 V Parameter (Note 15) (+2 dB Analog Gain) (Note 14) Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Full-scale Output Voltage Other Characteristics Interchannel Isolation Interchannel Gain Mismatch Output Offset (Note 17) Gain Drift Output Impedance Load Resistance (RL) Load Capacitance (CL) Min Typ VA = 1.8 V Max Min Typ Max A-weighted 93 99 91 97 unweighted 90 96 88 94 A-weighted 96 94 unweighted 94 92 (Note 16) 0 dB -84 -78 -86 -80 -20 dB -76 -74 -60 dB -36 -30 -34 -28 0 dB -82 -84 -20 dB -74 -72 -60 dB -34 -32 (Note 17) 1.50*VA 1.58*VA 1.71*VA 1.50*VA 1.58*VA 1.71*VA (Note 17) (Note 17) Mute 0 dB Analog Gain (Note 17) Unit dB dB dB dB dB dB dB dB dB dB VPP (Note 17) 10 90 0.1 0.5 3.6 100 100 - 0.32 1.0 14.6 - 10 90 0.1 0.5 2.8 100 100 - 0.32 1.0 10.6 - dB dB mV mV ppm/C k (Note 17) - - 150 - - 150 pF Notes: 14. The analog gain setting ("Headphone Volume Control" on page 84 or "Line Volume Control" on page 84) must be configured as indicated to achieve the specified output characteristics. 15. One LSB of triangular PDF dither is added to data. 16. VCP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the specified THD+N performance at full-scale output voltage and power may not be achieved. 17. See Figure 6 and Figure 7. Refer to "Parameter Definitions" on page 91. 18. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 45 to Note 48 on page 90) have been normalized to Fs and can be denormalized by multiplying the X-axis scale by Fs. 19. Measurement bandwidth is from Stopband to 3 Fs. DS851F2 19 CS42L56 Test Load Symbolized component values are specified in table "HP Output Characteristics" on page 19 HPOUTx HPREF GND/AGND 33 CL RL 0.1 F + Measurement Device Figure 6. HP Output Test Configuration Symbolized component values are specified in table "Line Output Characteristics" on page 20 Test Load LINEOUTx CL RL LINEREF GND/AGND + Measurement Device Figure 7. Line Output Test Configuration 20 DS851F2 CS42L56 ANALOG PASSTHROUGH CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; Input test signal is a 1 kHz sine wave through the passive input filter shown in Figure 1, PGA and HP/Line gain = 0 dB; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Measurement signal path is AINxx to HPOUTx or LINEOUTx. Parameter Analog In to HP Amp (ADC is powered down) RL = 10 k(+2 dB Output Analog Gain) (Note 14) Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 16) -1 dB -20 dB -60 dB Full-scale Input Voltage (Note 8) Full-scale Output Voltage (Note 17) Frequency Response RL = 16 (-4 dB Output Analog Gain) (Note 14) Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 16) -1 dB -20 dB -60 dB Full-scale Input Voltage (Note 8) Output Power (Note 16) Frequency Response Analog In to Line Amp (ADC is powered down) RL = 10 k(+2 dB Output Analog Gain) (Note 14) Dynamic Range A-weighted unweighted Total Harmonic Distortion + Noise (Note 16) -1 dB -20 dB -60 dB Full-scale Input Voltage (Note 8) Full-scale Output Voltage (Note 17) Frequency Response Min VA = 2.5 V Typ Max Min VA = 1.8 V Typ Max Unit - 94 91 - - 91 88 - dB dB - -70 -71 -31 0.80*VA 0.93*VA 0/-0.3 - - -80 -68 -28 0.80*VA 0.93*VA 0/-0.3 - dB dB dB Vpp Vpp dB - 94 91 - - 91 88 - dB dB - -70 -71 -31 0.80*VA 12 0/-0.3 - - -80 -68 -28 0.80*VA 6.5 0/-0.3 - dB dB dB Vpp mW dB - 94 91 - - 91 88 - dB dB - -70 -71 -31 0.80*VA 0.89*VA 0/-0.3 - - -80 -68 -28 0.80*VA 0.89*VA 0/-0.3 - dB dB dB Vpp Vpp dB COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 18) Frequency Response 20 Hz to 20 kHz Passband Stopband Stopband Attenuation Total Group Delay De-emphasis Error DS851F2 Fs = 48.000 kHz Fs = 44.118 kHz to -0.05 dB corner to -3 dB corner (Note 19) Fs = 44.118 kHz Min Typ Max Unit -0.007 -0.081 0.55 49 - 0.48 0.49 6.5/Fs - +0.007 +0.081 +0.05/-0.25 dB dB Fs Fs Fs dB s dB 21 CS42L56 SWITCHING SPECIFICATIONS - SERIAL PORT Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF. Parameters Symbol RESET pin Low Pulse Width (Note 20) Min Max Units 1 (See "Serial Port Clocking" on page 47) 45 55 MCLK Frequency MCLK Duty Cycle Slave Mode (Figure 8) (See "Serial Port Clocking" on page 47) 45 55 68*Fs 1/tPs 45 55 40 tss(LK-SK) 20 tss(SDO-SK) 30 ths(SK-SDO) 20 tss(SD-SK) 20 ths Input Sample Rate (LRCK) Fs LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Master Mode (Figure 9) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK = MCLK mode All Other Modes RATIO[4:0] = `xxx00' or `xxx11' RATIO[4:0] = `xxx01' (Note 21) SCLK Duty Cycle (See "Serial Port Clocking" on page 47) 45 55 1/tPm 12.0000 68*Fs 1/tPm 45 55 33 66 2 tsm(LK-SK) 20 tsm(SDO-SK) 30 thm(SK-SDO) 20 tsm(SD-SK) 20 thm Fs LRCK Time Before SCLK Falling Edge SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge ms MHz % kHz % Hz % ns ns ns ns ns Hz % MHz Hz % % ns ns ns ns ns Notes: 20. After powering up the CS42L56, RESET should be held low after the power supplies and clocks are settled. This specification is valid with the recommended capacitor on VDFILT. 21. When the RATIO[1:0] = `01', the device will periodically extend the SCLK high time to compensate for the resulting fractional MCLK/SCLK ratio. // LRCK tss(LK-SK) SCLK // SDIN // // // // // // tss(SD-SK) // ths(SK-SDO) // MSB // SCLK MSB // tsm(LK-SK) tPm // // // // tsm(SDO-SK) SDOUT // // ths Figure 8. Serial Port Timing (Slave Mode) 22 // tP // tss(SDO-SK) SDOUT // LRCK SDIN // tsm(SD-SK) // thm(SK-SDO) // MSB // thm MSB // Figure 9. Serial Port Timing (Master Mode) DS851F2 CS42L56 SWITCHING SPECIFICATIONS - IC CONTROL PORT Inputs: Logic 0 = GND = AGND, Logic 1 = VL (Note 22) . Parameter Symbol Min Max Unit tirs 500 - ns RESET Rising Edge to Start SCL Clock Frequency fscl - 550 kHz Start Condition Hold Time (prior to first clock pulse) thdst 0.6 - s Clock Low Time tlow 1.3 - s Clock High Time thigh 0.6 - s tsust 0.6 - s thddi 0 0.9 s Setup Time for Repeated Start Condition SDA Input Hold Time from SCL Falling (Note 23) SDA Output Hold Time from SCL Falling thddo 0.2 0.9 s SDA Setup Time to SCL Rising tsud 100 - ns Rise Time of SCL and SDA trc - 300 ns Fall Time SCL and SDA tfc - 300 ns Setup Time for Stop Condition tsusp 0.6 - s Bus Free Time Between Transmissions tbuf 1.3 - s SDA Bus Capacitance CL - 400 pF SDA Pull-Up Resistance Rp 500 - Notes: 22. All specifications are valid for the signals at the pins of the CS42L56 with the specified load capacitance. 23. Data must be held for sufficient time to bridge the transition time, tf, of SCL. RESET t irs Stop Repeated Start Start Stop SDA t buf t t high t hdst tf hdst t susp SCL t low t hdd t sud t sust tr Figure 10. IC Control Port Timing DS851F2 23 CS42L56 SWITCHING CHARACTERISTICS - SPI CONTROL PORT Inputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL = 30 pF. Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RESET Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.0 - s CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 24) tdh 15 - ns Rise Time of CCLK and CDIN (Note 25) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 25) tf2 - 100 ns Notes: 24. Data must be held for sufficient time to bridge the transition time of CCLK. 25. For fsck <1 MHz. RESET tsrs CS tcsh tcss tsch tscl tr2 CCLK tf2 tdsu tdh CDIN Figure 11. Control Port Timing - SPI Format 24 DS851F2 CS42L56 ANALOG OUTPUT ATTENUATION CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; GND = AGND = 0 V. Attenuation is referenced to the full-scale voltage for the given output. Test load RL = 3 k CL = 150 pFfor a line load, and test load RL = 16 CL = 150 pF for a headphone load (See Figure 6 and Figure 7 on page 21). Power Status Parameters Headphone Line Min Typ Max Units Headphone Mute Attenuation (HPxMUTE=1) (Note 26) OFF OFF ON ON OFF ON OFF ON - 90 90 90 90 - dB dB dB dB Line Mute Attenuation (LINExMUTE=1) (Note 26) OFF OFF ON ON OFF ON OFF ON - 90 90 90 90 - dB dB dB dB Notes: 26. Assumes no external impedance on HPREF or LINEREF. External impedance on HPREF or LINEREF will impact the attenuation. DS851F2 25 CS42L56 DC CHARACTERISTICS Test Conditions (unless otherwise specified): Connections to the CS42L56 are shown in the "Typical Connection Diagrams" on page 11; GND = AGND = 0 V; all voltages with respect to ground. Parameters Min Typ Max Units VHPFILT Characteristics (Note 27) VCP Mode +VHPFILT -VHPFILT - VCP -VCP - V V VCP/2 Mode +VHPFILT -VHPFILT - VCP/2 -VCP/2 - V V BIAS_LVL[1:0] = 00 BIAS_LVL[1:0] = 01 BIAS_LVL[1:0] = 10 BIAS_LVL[1:0] = 11 - 0.9*VA 0.8*VA 0.7*VA 0.6*VA - V V V V MIC BIAS Characteristics Nominal Voltage DC Output Current (Note 28) - - 1.22 mA BIAS_LVL[1:0] = 00 BIAS_LVL[1:0] = 01 BIAS_LVL[1:0] = 10 BIAS_LVL[1:0] = 11 - 45 50 50 50 - dB dB dB dB FILT+ VQ VDFILT - VA VA/2 0.9 - V V V PGA to ADC PGA (Pseudo Differential) to ADC ADC PGA to HP & Line Amps PGA (Pseudo Differential) to HP & Line Amps DAC to HP & Line Amps - 47 58 57 44 54 56 - dB dB dB dB dB dB - 35 25 50 60 - dB dB dB dB Power Supply Rejection Ratio (PSRR) @ 1 kHz Misc. DC Filter Characteristics Power Supply Rejection Ratio (PSRR) Characteristics PSRR with 100 mVpp, 1 kHz signal (Note 29) PSRR with 100 mVpp, 60 Hz signal (Notes 29, 30) PGA to ADC ADC PGA to HP & Line Amps DAC to HP & Line Amps Notes: 27. No load connected to HPOUTx and LINEOUTx. 28. VA = 2.71 V, BIAS_LVL[1:0] = 00, total equivalent external impedance to ground = 2 k. 29. Valid with the recommended capacitor values on FILT+ and VQ, no load on HP and Line. Increasing the capacitance on FILT+ and VQ will also increase the PSRR. 30. The PGA is biased with VQ, created by a resistor divider from the VA supply. Increasing the capacitance on FILT+ and VQ will also increase the PSRR at low frequencies. A 10 F capacitor on VQ improves the PSRR to 42 dB. 26 DS851F2 CS42L56 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS Parameters (Note 31) Symbol Min Max Units Iin - 10 10 A pF 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) VOH VL - 0.2 - V Low-Level Output Voltage (IOL = 100 A) VOL - 0.2 V 0.30*VL V V 0.35*VA V V Input Leakage Current Input Capacitance High-Level Input Voltage VL = 1.65 V VL = 1.8 V VL = 2.0 V VL > 2.0 V Low-Level Input Voltage VIL 0.83*VL 0.76*VL 0.68*VL 0.65*VL - HPDETECT Input High-Level Input Voltage Low-Level Input Voltage HPDVIH HPDVIL 0.65*VA - VIH 31. See "I/O Pin Characteristics" on page 10 for serial and control port power rails. 1 Power Supply VCP 2.2 F 1 + - VA 0.1 F 1 VLDO 0.1 F 1 + Voltmeter + - VL GND/AGND 0.1 F + - Note: Current is derived from the voltage drop across a 1 resistor in series with each supply input. Figure 12. Power Consumption Test Configuration DS851F2 27 CS42L56 POWER CONSUMPTION - ALL SUPPLIES = 1.8 V ADC PGA to ADC 4 Stereo Record (Note 35) ADC PGA to ADC 5 Mono Play to HP No Effects Effects 6 Mono Play to Line No Effects Effects 7 8 Stereo Play to HP Stereo Play to Line No Effects x 1 1 1 0 0 0 0 0 ADCAMUX[1:0] Mono Record (Note 35) x x x x 0 0 0 0 1 ADCBMUX[1:0] (Note 34) MCLKDIS=x 3 x x x x 1 1 0 0 1 PDN_LINA[1:0] MCLKDIS=0 x x x x 0 0 0 0 1 PDN_LINB[1:0] Standby (Note 33) MCLKDIS=1 Typical Current (mA) 08h page 74 PDN_HPA[1:0] Off (Note 32) 03h page 59 PDN_HPB[1:0] 1 2 02h page 58 PDN_CHRG PDN_ADCB PDN_ADCA PDN Operation Test Conditions (unless otherwise specified): All zeros input, slave mode, sample rate = 48 kHz; No load. Refer to Figure 12 on page 28. ADC, Line, HP Sel. Registers LINEBMUX LINEAMUX HPBMUX HPAMUX PDN_DSP - 0Fh page 66 Power Ctl. Registers x x x x 11 11 11 11 11 x x x x 11 11 11 11 10 x x x x 11 11 11 11 11 x x x x 11 11 11 11 11 x x x x xx xx 01 00 xx x x x x 01 00 01 00 xx 1 1 1 0 11 10 11 11 xx 1 1 1 0 11 11 11 10 xx 1 1 1 0 11 11 11 10 xx 1 1 1 0 10 10 11 11 xx Effects 1 1 1 0 10 10 11 11 xx No Effects 1 1 1 0 11 11 10 10 xx Effects 1 1 1 0 11 11 10 10 xx iVCP iVA iVLDO Class H Mode page 63 0.001 0.001 0.007 0.002 0.001 0.001 0.053 0.007 0.11 0.001 0.010 0.292 0.007 0.56 0.001 0.001 0.020 0.001 0.04 0.001 0.915 0.671 0.018 2.89 0.001 1.056 0.672 0.017 3.14 0.001 1.207 0.824 0.023 3.70 0.002 1.469 0.826 0.022 4.17 0.407 1.100 0.718 0.007 4.02 VCP 0.949 1.107 0.718 xx x x x 0 0 VCP/2 0.407 1.100 1.050 VCP 0.948 1.107 1.050 xx x 0 x x 1 VCP/2 0.392 1.101 0.719 VCP 0.844 1.107 0.717 xx x 0 x x 0 VCP/2 0.392 1.101 1.046 VCP 0.844 1.107 1.046 xx x x 0 0 1 VCP/2 0.604 1.587 0.720 0.007 5.01 0.007 4.62 0.007 5.60 0.007 3.99 0.007 4.82 0.007 4.58 0.007 5.41 0.007 5.25 VCP 1.420 1.594 0.717 xx x x 0 0 0 VCP/2 0.604 1.587 1.090 VCP 1.419 1.594 1.090 xx 0 0 x x 1 VCP/2 0.570 1.589 0.718 VCP 1.205 1.597 0.719 xx 0 0 x x 0 VCP/2 0.570 1.589 1.089 VCP 1.205 1.597 1.088 xx x x 1 1 x VCP/2 0.565 1.180 0.213 0.007 6.73 0.007 5.92 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x 1 VCP/2 4.69 3.55 0 1 0 0 11 10 11 11 xx PGA In, HP Out Effects 0 1 0 0 11 10 11 11 xx No Effects 0 0 0 0 10 10 11 11 00 PGA In, HP Out 13 Stereo Play to HP 6.35 5.86 0.007 VCP 1.198 1.188 0.213 Effects 0.007 0.007 0 1 1 0 11 11 10 10 xx xx 1 1 x x x VCP/2 0.571 1.183 0.213 0.007 Stereo Passthrough to Line Stereo Rec. & Play 7.40 5.19 7.01 10 12 0.007 0.007 3.54 0 1 1 0 10 10 11 11 xx No Effects 0.02 0.007 Stereo Passthrough to HP Mono Rec. & Play Total Power (mW) 0.007 9 11 iVL 0 0 0 0 10 10 11 11 00 VCP 1.205 1.190 0.213 00 x x x 0 1 VCP/2 0.408 1.921 1.084 VCP 0.950 1.928 1.089 00 x x x 0 0 VCP/2 0.408 1.921 1.415 VCP 0.952 1.928 1.412 00 x x 0 0 1 VCP/2 0.604 2.820 1.239 VCP 1.422 2.827 1.240 00 x x 0 0 0 VCP/2 0.604 2.820 1.613 0.007 4.71 0.018 6.18 0.018 7.17 0.018 6.77 0.018 7.76 0.023 8.43 0.023 9.92 0.023 VCP 1.424 2.827 1.612 0.023 No Effects 1 1 1 0 10 10 11 11 xx xx x x 0 0 1 VCP/2 2.725 1.579 0.737 0.008 9.11 10.59 9.09 16 load (Note 36) 28 DS851F2 CS42L56 POWER CONSUMPTION - ALL SUPPLIES = 2.5 V 4 Stereo Record (Note 35) ADC PGA to ADC 5 6 7 8 Mono Play to HP Mono Play to Line Stereo Play to HP Stereo Play to Line No Effects ADCAMUX[1:0] ADC PGA to ADC x 1 1 1 0 0 0 0 0 ADCBMUX[1:0] Mono Record (Note 35) x x x x 0 0 0 0 1 PDN_LINA[1:0] 3 x x x x 1 1 0 0 1 PDN_LINB[1:0] MCLKDIS=0 (Note 34) MCLKDIS=x x x x x 1 1 1 1 1 PDN_HPA[1:0] Off (Note 32) Standby (Note 33) MCLKDIS=1 x x x x 11 11 11 11 11 x x x x 11 11 11 11 10 x x x x 11 11 11 11 11 x x x x 11 11 11 11 11 x x x x xx xx 01 00 xx x x x x 01 00 01 00 xx x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x 1 Effects 1 1 1 0 11 10 11 11 xx xx x x x 0 0 No Effects 1 1 1 0 11 11 11 10 xx xx x 0 x x 1 Effects 1 1 1 0 11 11 11 10 xx xx x 0 x x 0 No Effects 1 1 1 0 10 10 11 11 xx xx x x 0 0 1 Effects 1 1 1 0 10 10 11 11 xx xx x x 0 0 0 No Effects 1 1 1 0 11 11 10 10 xx xx 0 0 x x 1 Effects 1 1 1 0 11 11 10 10 xx xx 0 0 x x 0 9 Stereo Passthrough to HP 1 1 1 0 10 10 11 11 xx xx x x 1 1 x 10 Stereo Passthrough to Line 1 1 1 0 11 11 10 10 xx xx 1 1 x x x 11 Mono Rec. & Play PGA In, HP Out 1 1 0 0 11 10 11 11 xx 00 x x x 0 1 No Effects Effects 12 Stereo Rec. & Play PGA In, HP Out No Effects Typical Current (mA) 08h page 74 PDN_HPB[1:0] 1 2 03h page 59 PDN_CHRG PDN_ADCB PDN_ADCA PDN Operation Test Conditions (unless otherwise specified): All zeros input, slave mode, sample rate = 48 kHz; No load. Refer to Figure 12 on page 28. MUX Registers LINEBMUX LINEAMUX HPBMUX HPAMUX PDN_DSP - 0Fh page 66 Power Ctl. Registers 02h page 58 iVCP Class H Mode page 63 VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 VCP VCP/2 iVA iVLDO iVL Total Power (mW) 0.004 0.012 0.012 0.003 0.026 0.026 0.033 0.033 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.012 0.05 0.26 1.25 0.10 3.91 4.35 5.11 5.94 7.35 10.53 8.19 11.36 7.28 10.11 8.12 10.95 9.46 13.48 10.39 14.40 9.31 12.65 10.24 13.58 5.78 9.15 5.80 9.14 0.723 2.148 1.157 0.026 10.14 VCP 1.981 2.160 1.162 0.026 13.32 10.97 14.15 0.002 0.003 0.003 0.003 0.003 0.003 0.003 0.003 0.723 1.984 0.723 1.982 0.693 1.819 0.693 1.819 0.936 2.530 0.934 2.526 0.873 2.197 0.873 2.196 0.870 2.202 0.874 2.196 0.002 0.003 0.017 0.003 0.789 0.963 1.089 1.419 1.469 1.480 1.468 1.480 1.469 1.481 1.469 1.481 2.099 2.113 2.099 2.113 2.102 2.115 2.102 2.115 1.203 1.218 1.206 1.220 0.013 0.084 0.466 0.032 0.744 0.748 0.919 0.922 0.734 0.736 1.071 1.069 0.736 0.732 1.073 1.069 0.737 0.736 1.109 1.109 0.737 0.736 1.110 1.108 0.228 0.228 0.228 0.228 1 1 0 0 11 10 11 11 xx 00 x x x 0 0 VCP/2 0.723 2.148 1.491 0.026 VCP 1.983 2.160 1.489 0.027 VCP/2 1 0 0 0 10 10 11 11 00 00 x x 0 0 1 0.936 3.233 1.335 0.033 VCP 2.532 3.247 1.336 0.033 Effects 1 0 0 0 10 10 11 11 00 00 x x 0 0 0 VCP/2 0.936 3.233 1.710 0.033 No Effects 1 1 1 0 10 10 11 11 xx xx x x 0 0 1 VCP/2 3.032 2.081 0.754 0.012 VCP 2.534 3.247 1.710 0.033 13 Stereo Play to HP 13.84 17.87 14.78 18.81 14.70 16 load (Note 36) Notes: 32. 33. 34. 35. 36. DS851F2 RESET pin and clock/data lines held LO, PDN=x. RESET pin held HI, PDN=1. Clock/data lines held HI. Either inputs 1 or 2 may be selected. Input 1 is shown for simplicity. In accordance with the JEITA CP-2905B standard, 0.1 mW (per channel) is delivered to the headphone load. 29 CS42L56 4. APPLICATIONS 4.1 4.1.1 Overview Basic Architecture The CS42L56 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised of stereo A/D and D/A converters with pseudo-differential stereo input and output amplifiers. The ADC and DAC are designed using multi-bit delta-sigma techniques; both converters operate at a low oversampling ratio of 64xFs, maximizing power savings while maintaining high performance. The CODEC accepts and is capable of generating serial audio clocks (SCLK, LRCK) derived from a USB or a standard audio input Master Clock (MCLK). Designed with a very low voltage digital core and low voltage Class H amplifiers (powered from an integrated low-dropout regulator and a step-down/inverting charge pump, respectively), the CS42L56 provides significant reduction in overall power consumption. 4.1.2 Line Inputs The analog input portion of the CODEC allows selection from up to three stereo line-level sources into a Programmable Gain Amplifier (PGA). The optional line pseudo-differential configuration provides common-mode noise rejection for single-ended inputs and is available on AIN1x or AIN2x. If pseudo-differential operation is not required, the pins can also be configured independently as two additional analog inputs (AIN3x). 4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) The analog output portion of the CODEC includes separate pseudo-differential headphone and line out Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage equal to the input or one-half the input supply for the amplifiers, allowing an adaptable, full-scale output swing centered around ground. The inverting architecture eliminates the need for large DC-blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. The step-down architecture allows the amplifier's power supply to adapt to the required output signal. This adaptive power supply scheme converts traditional Class AB amplifiers into more power-efficient Class H amplifiers. 4.1.4 Fixed-function DSP Engine The fixed function digital signal processing engine processes both the PCM serial input data and ADC output data allowing a mix between the two. Independent volume control, left/right channel swaps, mono mixes, tone control comprise the DSP engine. 4.1.5 Beep Generator The beep generator delivers tones at select frequencies across approximately two octave major scales. With independent volume control, beeps may be configured to occur continuously, periodically or at single time intervals. 4.1.6 Power Management Several control registers and bits provide independent power down control of the ADC, PGA, DSP, headphone and line outputs, allowing operation in select applications with minimal power consumption. 30 DS851F2 CS42L56 4.2 Analog Inputs PGAAMUX[1:0] BOOSTA ADCAMUTE DIGSFT ADCAATT[7:0] ADCB=A HPFRZA HPFA HPFA_CF[1:0] PDN_ADCA INV_ADCA PDN_CHRG AIN1A AIN2A PREAMPA[1:0] Gain Adjust ADC AIN1REF / AIN3A PGA A ADCAMUX[1:0] VQ NGALL NG THRESH[3:0] NGDELAY[1:0] PDN_ADCB PGABVOL[5:0] PGAB=A ANLGZC AIN1B_REF AIN2B_REF Noise Gate ALC ALCARATE[5:0] ALCRRATE[5:0] ALCMAX[2:0] ALCMIN[2:0] ALCB ALCBSRDIS ALCBZCDIS DIGSUM[1:0] Swap/ Mix DIGMUX PCM Serial Interface PDN_ADCA PGAAVOL[5:0] PGAB=A ANLGZC AIN1A_REF AIN2A_REF ALCA ALCASRDIS ALCAZCDIS ADCBMUX[1:0] AIN2REF / AIN3B PGA B Gain Adjust ADC PREAMPB[1:0] AIN2B AIN1B PDN_ADCB INV_ADCB PDN_CHRG PGABMUX[1:0] ANALOG PASSTHRU TO HEADPHONE, LINE AMPLIFIER MUX HPFRZB HPB HPFB_CF[1:0] BOOSTB ADCBMUTE DIGSFT ADCBATT[7:0] ADCB=A TO DSP Engine FROM DSP ENGINE Figure 13. Analog Input Signal Flow Referenced Control Analog Front End AIN1x_REF AIN2x_REF PREAMPx[1:0] PGAxMUX[1:0] PDN_ADCx PGAxVOL[5:0] PGAB=A ANLGZCx ADCxMUX[1:0] INV_ADCx PDN_CHRG HPFRZx HPFx HPFx_CF[1:0] Digital Volume BOOSTx ADCxMUTE ADCxATT[7:0] DIGSFT ADCB=A ALCx ALCxSRDIS ALCxZCDIS ALCARATE[5:0] ALCRRATE[5:0] MAX[2:0] MIN[2:0] NGALL NG THRESH[3:0] NGDELAY[1:0] Miscellaneous DIGSUM[1:0] DIGMUX DS851F2 Register Location "Analog Input 1 x Reference Configuration" on page 74 "Analog Input 2 x Reference Configuration" on page 74 "PGA x Preamplifier Gain" on page 77 "PGA x Input Select" on page 77 "Power Down ADC x" on page 59 "PGAx Volume" on page 78 "PGA Channel B=A" on page 76 "Analog Zero Cross" on page 64 "ADC x Input Select" on page 75 "Invert ADC Signal Polarity" on page 76 "Power Down ADC Charge Pump" on page 59 "ADCx High-Pass Filter Freeze" on page 75 "ADCx High-Pass Filter" on page 75 "HPF x Corner Frequency" on page 75 "Boostx" on page 77 "ADC Mute" on page 76 "ADCx Volume" on page 78 "Digital Soft Ramp" on page 64 "ADC Channel B=A" on page 76 "ALCx" on page 79 "ALCx Soft Ramp Disable" on page 82 "ALCx Zero Cross Disable" on page 82 "ALC Attack Rate" on page 79 "ALC Release Rate" on page 80 "ALC Maximum Threshold" on page 80 "ALC Minimum Threshold" on page 81 "Noise Gate All Channels" on page 81 "Noise Gate Enable" on page 81 "Noise Gate Threshold and Boost" on page 82 "Noise Gate Delay Timing" on page 82 "Digital Sum" on page 76 "Digital MUX" on page 63 31 CS42L56 4.2.1 Pseudo-differential Inputs The CS42L56 implements a pseudo-differential input stage. The AINxREF inputs are intended to be used as a pseudo-differential reference signal. This feature provides common mode noise rejection with singleended signals. Figure 14 shows a basic diagram outlining the internal implementation of the pseudo-differential input stage, including a recommended stereo pseudo-differential input topology. If pseudo-differential input functionality is not required, the AINxREF pin should be AC-coupled to GND. Common-Mode Cancellation, Invert, and Gain VCM V=? VCM xIN Signal+ - DC-Block xREF Parallel PCB traces from signal source ADC + Digital Full Scale AntiAliasing Filter VCM VA - R VCM VQ + VCM R AGND AFILTx Figure 14. Stereo Pseudo-Differential Input It should be noted that the AINxREF inputs are intended to be used solely to provide a low-level, pseudodifferential reference signal for the internal input amplifiers when in pseudo-differential mode. Using the analog input pins in a fully differential configuration by providing a large signal on the AINxREF pin is not recommended. The output of the PGA will clip if the voltage difference between AINxx and AINxREF exceeds the full-scale voltage specification (See Note 10 on page 17). 4.2.2 Large-scale Inputs The CS42L56 allows the user to input signals that would be larger than the ADC full-scale input voltage by using the PGA to attenuate the signal prior to going to the ADC. Table 1 shows the PGA gain setting needed to stay under the maximum ADC input voltage. Supply Voltage (V) 1.8 2.5 PGA Gain Setting (dB) 0.0 -0.5 -1.0 -1.5 0.0 -0.5 -1.0 -1.5 Maximum Input Voltage (VPP) (mVRMS) 509 1.44 539 1.52 571 1.62 604 1.71 707 2.00 748 2.12 793 2.24 840 2.38 Table 1. Input Voltage PGA Settings 32 DS851F2 CS42L56 If signals larger than what is shown in Table 1 are needed, an external resistor divider should be used as shown in Table 15. When using an external resistor divider, the PGA must be configured to be in-circuit. R1 1 F Input AINxx R3 R2 Figure 15. Analog Input Attenuation Three parameters determine the values of resistors R1 and R2 as shown in Figure 15: source impedance, attenuation, and input impedance. Table 2 shows the design equation used to determine these values. * Source Impedance: Source impedance is defined as the impedance as seen from the PGA looking back into the signal network. The PGA achieves optimal THD+N performance with a source impedance less than 5 k. * Attenuation: The required attenuation factor depends on the magnitude of the input signal. The fullscale input voltage is specified under "Analog Input Characteristics" on page 14. The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied by the attenuation factor is less than or equal to the full-scale input voltage of the device. * Input Impedance: Input impedance is the impedance from the signal source to the PGA analog input pins, including the PGA. The PGA's input impedance (R3 in Figure 15, Table 2, and Figure 16) is given in the "Analog Input Characteristics" on page 14. Source Impedance R1 R2 ----------------------- R1 + R2 Attenuation Factor R2 R3 ---------------------------------------------------------------------------- R1 R2 + R2 R3 + R1 R3 Input Impedance --------------------------------------------------R1 R3 + R2 R3 R1 + R2 + R3 Table 2. Analog Input Design Parameters Figure 16 illustrates an example configuration with the PGA in-circuit using one 7.87 kresistor for R1 and one 4.75 k resistor for R2. Based on the discussion above, this circuit provides an optimal interface for both the PGA and the signal source. First, consumer equipment frequently requires an approximate input impedance of 10 kwhich the combination of the resistors provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the PGA, 0.7 Vrms when VA = 2.5 V. Finally, at approximately 3 kthe source impedance is within the allowable range of the PGA. 7.87 k Input 4.75 k 1 F AINxx R3 Figure 16. Example Analog Input Attenuation DS851F2 33 CS42L56 4.2.3 Microphone Inputs Any of the line inputs can be configured as a microphone input by using the MICBIAS pin to power the external microphone circuit and by configuring the additional +10 or +20 dB gain in the PGA to properly boost the low-level microphone signal. 4.2.3.1 External Passive Components The analog inputs are internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The analog input resistance may be combined with an external capacitor to achieve the desired cutoff frequency. The equation below gives an example: 1 fc = -------------------------------------------- = 39.79 Hz 2 4 k 1 F An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the BIAS_LVL[1:0] bits. The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. MICBIAS MICx+ + // // + MICx- Figure 17. MIC Input Mix w/Common Mode Rejection Referenced Control Register Location BIAS_LVL[1:0] ..................... "Microphone Bias Output Level" on page 77 4.2.4 Optional VCM Buffer Leaving an analog input pin floating when not being used might inject distortion in the analog input signal path. To prevent this, the analog inputs may be internally biased to VCM by using a weak internal VCM buffer when not being used. The VCM buffer outputs a weakly buffered version of the internal commonmode voltage and biases the chip-side of the analog input AC-coupling capacitor to a constant DC level. This prevents the analog signal from being distorted when that particular channel is not selected by either the PGA or ADC input MUX. If an analog signal is routed to any place other than just the CS42L56, it is recommended to set this bit to 0b. If all analog signals are only routed to the CS42L56, this bit may be left set to 1b. Referenced Control Register Location PDN_VBUF[1:0]................... "Power Down VCM Bias Buffer" on page 58 4.2.5 Automatic Level Control (ALC) The function of the ALC is to maintain the level of the analog input signal between the maximum and minimum threshold settings programmed in the ALCMAX[2:0] and ALCMIN[2:0] registers. When enabled, the ALC monitors the signal level after the digital volume control block in the input signal path and detects 34 DS851F2 CS42L56 whenever a threshold violation occurs. It then modifies the signal level by adjusting the gain settings in the PGA and ADC digital volume control accordingly. As shown in Figure 18, if the input signal level rises above the maximum threshold, the ALC first lowers the PGA gain settings. It then decreases the ADC digital volume at a programmable "attack" rate and maintains the resulting level below the maximum threshold. In contrast, if the input signal level falls below the minimum threshold, the ALC first increases the ADC digital volume settings and then increases the PGA gain settings at a programmable "release" rate. However, once an attack or release operation has been performed on an input signal, the ALC does not change the PGA or the digital volume control settings until the next threshold violation occurs. Input (before ALC) ALCMAX[2:0] below full scale ALCMIN[2:0] below full scale PGA Response ADC Vol. Cntrl. Response Total ALC Response Output (after ALC) ALCMAX[2:0] ALCMIN[2:0] below full scale below full scale ARATE[5:0] RRATE[5:0] ARATE[5:0] Figure 18. ALC Operation DS851F2 35 CS42L56 4.2.5.1 Attack/Release Time Calculations: The time taken by the ALC to perform an attack or a release operation is a function of the PGA/ADC digital volume control gain settings, ADC soft ramp/zero-cross settings, sample rate (Fs), maximum/minimum threshold settings, attack/release rate settings and the signal level after the digital volume control block. Since the PGA and the ADC digital volume control blocks perform gain increment/decrement steps at different rates, this must be taken into account to get an accurate attack/release time duration calculation. The attack and release rates for each block is determined by the formulas given below: 1 ADC Digital Volume Attack/Release Rate = ---------------------------------------------------------------- dB/LRCK 16 ALCxRATE[5:0] + 1 0.5 PGA Attack/Release Rate = ---------------------------------------------------------------16 ALCxRATE[5:0] + 1 dB/LRCK The maximum amount of time that can be taken by the ALC to perform an attack or release operation on a signal with a specific maximum/minimum threshold, PGA gain and ADC digital volume setting is determined by the formulae below: For attack operations: PGAxVOL[5:0] - (-6) (-ALCMAX[2:0]) Maximum Attack Time = ---------------------------------------------------------------- + ---------------------------------------------------------------- s PGA Attack Rate Fs ADC Attack Rate Fs For release operations: ADCxATT[7:0] - ALCMAX[2:0] PGAxVOL[5:0] - (-6) Maximum Release Time = --------------------------------------------------------------------------------- + -------------------------------------------------------------------- ADC Release Rate Fs PGA Release Rate Fs s Recommended settings: Best level control may be realized with a fast attack and a slow release setting with soft ramp enabled in the control registers. It should be noted that the ALC can only apply the gain up to the amount set in the PGAxVOL and ADCxATT registers and that the ALC maintains the output signal between the ALCMIN and ALCMAX thresholds. As a result when the input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds. 4.3 Referenced Control Register Location PGAxVOL[5:0] ..................... ADCxATT[7:0] ...................... ALCMAX[2:0], ALCMIN[2:0] ALCARATE[5:0].................... ALCRRATE[5:0].................... "PGAx Volume" on page 78 "ADCx Volume" on page 78 "ALC Threshold (Address 24h)" on page 80 "ALC Enable & Attack Rate (Address 22h)" on page 79 "ALC Release Rate (Address 23h)" on page 79 Analog In to Analog Out Passthrough The CS42L56 accommodates analog routing of the analog input signal directly to the headphone and line out amplifiers. This feature is useful in applications that utilize an FM tuner where audio recovered over-theair must be transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This analog passthrough path reduces power consumption and is immune to modulator switching noise that could interfere with some tuners. This path is selected using the Line and/or HP mux bits and powering down the ADC. Referenced Control Register Location PDN_ADCx ......................... "Power Down ADC x" on page 59 HPxMUX.............................. "Headphone Input Select" on page 83 LINExMUX........................... "Line Input Select" on page 83 36 DS851F2 CS42L56 4.4 Analog Outputs INPUTS FROM ADCA and ADCB Fixed Function DSP MSTAVOL[7:0] MSTBVOL[7:0] AMIXAMUTE AMIXBMUTE AMIXAVOL[6:0] AMIXBVOL[6:0] VOL PCM Serial Interface PMIXAMUTE PMIXBMUTE PMIXAVOL[6:0] PMIXBVOL[6:0] Demph DEEMPH VOL LIMARATE[7:0] LIMRRATE[7:0] LMAX[2:0] CUSH[2:0] LIMSRDIS LIMIT LIMIT_ALL Channel Swap Chnl Vol. Settings Limiter ADCASWAP[1:0] ADCBSWAP[1:0] Peak Detect PCMASWAP[1:0] PCMBSWAP[1:0] Channel Swap VOL INV_PCMA INV_PCMB MSTAMUTE MSTBMUTE DIGSFT BPVOL[4:0] OFFTIME[2:0] ONTIME[3:0] FREQ[3:0] BEEP[1:0] Digital Mix to ADC Serial Interface Bass/ Treble/ Control VOL * to HP and Line MUX TC_EN BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] PLYBCKB=A Beep Generator DAC PDN_DSP * MSTxVOL[7:0], MSTxMUTE and DIGSFT are always available regardless of the PDN_DSP setting. Figure 19. DSP Engine Signal Flow Referenced Control DSP PDN_DSP DEEMPH PMIXxMUTE PMIXxVOL[6:0] INV_PCMx PCMxSWAP[1:0] AMIXxMUTE AMIXxVOL[6:0] ADCxSWAP[1:0] MSTxVOL[7:0] MSTxMUTE DIGSFT PLYBCKB=A TC_EN BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] Limiter LIMIT LIMIT_ALL LIMSRDIS LMAX[2:0] CUSH[2:0] LIMARATE[7:0] LIMRRATE[7:0] Beep Generator DS851F2 Register Location "Power Down DSP" on page 66 "HP/Line De-Emphasis" on page 66 "PCM Mixer Channel x Mute" on page 67 "PCM Mixer Channel x Volume" on page 68 "Invert PCM Signal Polarity" on page 66 "PCM Mix Channel Swap" on page 74 "ADC Mixer Channel x Mute" on page 67 "ADC Mixer Channel x Volume" on page 67 "ADC Mix Channel Swap" on page 74 "Master Volume Control" on page 70 "Master Playback Mute" on page 67 "Digital Soft Ramp" on page 64 "Playback Channels B=A" on page 66 "Tone Control Enable" on page 73 "Bass Corner Frequency" on page 73 "Treble Corner Frequency" on page 72 "Bass Gain" on page 73 "Treble Gain" on page 73 "Peak Detect and Limiter" on page 86 "Peak Signal Limit All Channels" on page 86 "Limiter Soft Ramp Disable" on page 82 "Limiter Maximum Threshold" on page 85 "Limiter Cushion Threshold" on page 85 "Limiter Attack Rate" on page 87 "Limiter Release Rate" on page 86 Refer to "Beep Generator" on page 45 for all referenced controls 37 CS42L56 VCP Step-down/Inverting Charge Pump ADPTPWR[1:0] Class H Control = HP and Line Supply HP Detection +VCP +VCP/2 HPDETECT PDN_HPx[1:0] PDN_LINx[1:0] -VCP -VCP/2 +VHPFILT CHGFREQ[3:0] +HP Supply from PGAx from DACx +Line Supply HPOUTA HPOUTB - HPxMUX HPxVOL[6:0] HPxMUTE ANLGZC PLYBCKB=A + HPREF LINEOUTA LINEOUTB + LINExMUX LINExVOL[6:0] LINExMUTE ANLGZC PLYBCKB=A LINEREF -HP Supply -Line Supply -VHPFILT Figure 20. Analog Output Stage 4.5 Referenced Control Register Location Analog Output ADPTPWR[1:0] CHGFREQ[3:0] PDN_HPx[1:0] PDN_LINx[1:0] HPxMUTE HPxVOL[7:0] LINExMUTE LINExVOL[7:0] ANLGZC PLYBCKB=A HPxMUX LINExMUX "Adaptive Power Adjustment" on page 63 "Charge Pump Frequency" on page 63 "Headphone Power Control" on page 59 "Line Power Control" on page 60 "Headphone Channel x Mute" on page 83 "Headphone Volume Control" on page 84 "Line Channel x Mute" on page 84 "Line Volume Control" on page 84 "Analog Zero Cross" on page 64 "Playback Channels B=A" on page 66 "Headphone Input Select" on page 83 "Line Input Select" on page 83 Class H Amplifier The CS42L56 headphone and line output amplifiers use a Cirrus Logic patented Bi-Modal Class H technology. This technology maximizes operating efficiency of the typical Class AB amplifier while maintaining high performance. In a Class H amplifier design, the rail voltages supplied to the amplifier vary with the needs of the music passage that is being amplified. This prevents unnecessarily wasting energy during low power passages of program material or when the program material is played back at a low volume level. The central component of the Bi-Modal Class H technology found in the CS42L56 is the internal charge pump, which creates the rail voltages for the headphone and line amplifiers of the device. The charge pump receives its input voltage from the voltage present on the VCP pin of the CS42L56. From this input voltage, the charge pump creates the differential rail voltages that are supplied to the amplifier output stages. The charge pump is capable of supplying two sets of differential rail voltages. One set is equal to VCP and the other is equal to VCP/2. 38 DS851F2 CS42L56 4.5.1 Power Control Options The method by which the CS42L56 decides which set of rail voltages is supplied to the amplifier output stages depends on the settings of the Adaptive Power bits (ADPTPWR) found in "Class H Control (Address 08h)" section on page 63. As detailed in this section, there are four possible settings for these bits: standard Class AB mode (settings 01 and 10), adapt to volume mode (setting 00) and adapt to signal (setting 11). Referenced Control Register Location ADPTPWR[1:0] ................... "Adaptive Power Adjustment" on page 63 4.5.1.1 Standard Class AB Mode (setting 01 and 10) When the Adaptive Power bits are set to either 01 or 10, the rail voltages supplied to the amplifiers will be held to VCP/2 or VCP, respectively. For these two settings, the rail voltages supplied to the output stages are held constant, regardless of the signal level, internal volume settings, or the settings of the AIN and DIN advisory volume registers. In either of these two settings, the amplifiers in the CS42L56 simply operate in a traditional Class AB configuration. 4.5.1.2 Adapt to Volume Mode (setting 00) When the Adaptive Power bits are set to 00, the Class H controller decides which set of rail voltages to send to the amplifiers based upon the gain and attenuation levels of all active internal processing blocks. The active processing blocks are determined by the signal path configured; the configured path then dictates which volume settings affect the controller. The paths available in the CS42L56 are (1) analog-in to analog-out, (2) analog-in/digital-mix to analog-out and (3) digital-in to analog out. AINADV[7:0] 0 to -102dB MICxBOOST +10 or +20dB 1 PDNMICx Analog PGAAVOL [5:0] PGAB=A +12 to -6dB PDN_ADCx ADCB=A DIGSUM[1:0] ADCxMUX[ 1:0] BOOSTx 0 or +20dB PGA ADCxMUTE ADCxATT[7:0] 0 to -96dB AMIXxMUTE AMIXxVOL [6:0] Input Advisory Volume ADC Mix/ Swap HPxMUX BASS[3:0] TREB[3:0] PMIXxSWAP[1:0] +12 to -51.5dB Mix/ Swap 3 BEEP[1:0] +12 to -10.5dB Bass/Treble Boost/Cut TCEN PDN_DSP MSTxMUTE MSTxVOL[7:0] HP PLYBCKB=A LINE +12 to -102 dB DAC +12 to -60dB LINExMUX BPVOL [4:0] +6 to -50dB 0 to -102dB DINADV[7:0] Beep Generator HPxVOL [6:0] HPxMUTE PDN_HPx[1:0] HPDETECT (pin) +12 to -60dB 2 PMIXxMUTE PMIXxVOL[6:0] Digital ADCxSWAP[1:0] +12 to -51.5dB LINExVOL [6:0] LINExMUTE PDN_LINx[1:0] HPDETECT (pin) Non-volume controls (italicized ) affect how the Class H controller interprets the various volume settings. Figure 21. Class H Volume-Adapt Paths Certain controls for the processing blocks in the signal path (such as B=A, mux, swap, mix and various enables) do not directly affect the controller's total volume sum. These controls do, however, have an indirect effect since they determine how the volume setting of the relevant processing block contributes to the controller's sum. These controls (italicized in Figure 21) determine whether or not the associated volDS851F2 39 CS42L56 ume setting should be factored in with the volume settings of other control blocks in the signal path. The Class H controller can be affected by the combined effect of all the volume settings in the relevant path or the maximum sum in each channel (A, B) and the maximum sum in each amplifier (HP, Line). To determine the correct rail voltage for the amplifier, the controller assumes the input advisory volume is set correctly and that the signal level in each processing block does not exceed 0 dB. General Effect of Volume Sum in Signal Path If the total gain and attenuation set in the volume control registers would cause the amplifiers to clip a full- scale signal when operating from the lower set of rail voltages, the controller instructs the charge pump to supply the higher set of the two rail voltages (VCP) to the amplifiers (at this threshold, the total gain/attenuation has exceeded -10.5 dB). If the total gain and attenuation set in the volume control registers would not cause the amplifiers to clip a fullscale signal when operating from the lower set of rail voltages, the controller instructs the charge pump to supply the lower set of rail voltages (VCP/2) to the amplifiers (at this threshold, the total gain/attenuation is less than or equal to -10.5 dB). + + = VCP -10. 5 dB VCP/2 HP/LINE Supply Class H Controller Figure 22. Volume Sum Effects In order to adjust for external analog (line or microphone sources) or digital (DSP) input volume settings, the Class H controller also takes into account the settings of the AIN and DIN advisory volume registers. These volume settings do not affect the volume of the signal but serves to offset the total volume presented to the Class H controller. of A Path of B Path = Effect of Volume Sum in A or B Path = case2 HP/LINE Supply Decision: VCP VCP/2 Case 2 Result Case 1 Result -10.5 dB -10. 5 dB case1 case1 case2 Class H Controller Figure 23. Channel/Amp Effect 40 Since amplifier channels A and B share the same supply, the controller must consider the volume settings in the path of both these channels before supplying the appropriate rail voltage. For any of the three signal paths, the controller will instruct the charge pump to supply VCP to the amplifiers when the total gain/attenuation of either channel A or B exceeds the -10.5 dB threshold. Conversely, the charge pump will supply VCP/2 only when the total gain/attenuation of both channels A and B is less than or equal to -10.5 dB. DS851F2 CS42L56 of Line Path = Effect of Volume Sum in HP or Line Paths of HP Path = case2 HP/LINE Supply Decision: VCP VCP/2 Case 2 Result Case 1 Result -10.5 dB -10. 5 dB case1 case1 Since the HP and the Line amplifiers also share the same supply, the explanation above applies to the total gain/attenuation set in the HP and Line amplifiers. If enabled, the volume settings in the path of both amplifiers are considered before the charge pump supplies the appropriate rail voltage. case2 Class H Controller Figure 24. HP/Line Channel Effects DS851F2 Referenced Control Register Location AINADV[7:0] ........................ MICxBOOST ....................... PDNMICx ............................ PGAxVOL............................ ADCxMUX ........................... ADCxMUTE......................... DIGSUM[1:0] ....................... PDN_DSP ........................... HPxVOL[7:0] ....................... LINExVOL[7:0] .................... MSTxVOL[7:0]..................... MSTxMUTE......................... AMIXxVOL[6:0].................... PMIXxVOL[6:0].................... DINADV[7:0]........................ ADCxSWP........................... PCMxSWP .......................... HPxMUX.............................. LINExMUX........................... HPxMUTE ........................... LINExMUTE ........................ PDN_HPx ............................ PDN_LINEx ......................... TREB................................... BASS................................... TCEN................................... BEEP................................... BPVOL ................................ ADCB=A .............................. PGAB=A .............................. BOOSTx .............................. PLYBCKB=A........................ "Analog Input Advisory Volume" on page 69 "PGA x Preamplifier Gain" on page 77 "Power Down MIC Bias" on page 59 "PGAx Volume" on page 78 "ADC x Input Select" on page 75 "ADC Mute" on page 76 "Digital Sum" on page 76 "Power Down DSP" on page 66 "Headphone Volume Control" on page 84 "Line Volume Control" on page 84 "Master Volume Control" on page 70 "Master Playback Mute" on page 67 "ADC Mixer Channel x Volume" on page 67 "PCM Mixer Channel x Volume" on page 68 "Digital Input Advisory Volume" on page 69 "ADC Mix Channel Swap" on page 74 "PCM Mix Channel Swap" on page 74 "Headphone Input Select" on page 83 "Line Input Select" on page 83 "Headphone Channel x Mute" on page 83 "Line Channel x Mute" on page 84 "Headphone Power Control" on page 59 "Line Power Control" on page 60 "Treble Gain" on page 73 "Bass Gain" on page 73 "Tone Control Enable" on page 73 "Beep Configuration" on page 72 "Beep Volume" on page 72 "ADC Channel B=A" on page 76 "PGA Channel B=A" on page 76 "Boostx" on page 77 "Playback Channels B=A" on page 66 41 CS42L56 4.5.1.3 Adapt to Output Mode (setting 11) When the Adaptive Power bits are set to 11, the CS42L56 decides which of the two sets of rail voltages to send to the amplifiers based solely upon the level of the signal being sent to the amplifiers. If the signal that is sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail voltages, the control logic instructs the charge pump to provide the higher set of rail voltages (VCP) to the amplifiers. If the signal that is sent to the amplifiers would not cause the amplifiers to clip when operating on the lower set of rail voltages, the control logic instructs the charge pump to provide the lower set of rail voltages (VCP/2) to the amplifiers. This mode of operation eliminates the need to advise the CS42L56 of volume settings external to the device. Note: Signal detection is implemented using digital circuitry. This mode should, therefore, not be used with analog passthrough (PGA to HP/Line). 4.5.2 Power Supply Transitions Ideal Transition +VCP +VCP 2 Actual Transition caused by VHPFILT Capacitor Time Actual Transition caused by VHPFILT Capacitor -VCP 2 -VCP Ideal Transition Figure 25. VHPFILT Transitions Charge pump transitions from the lower set of rail voltages to the higher set of rail voltages occur on the next FLYN/P clock cycle. Despite the fast response time of the system, the capacitive elements on the VHPFILT pins prevent the rail voltages from changing instantaneously. Instead, the rail voltages ramp up from VCP/2 to VCP based on the time constant created by the output impedance of the charge pump and the capacitor on the VHPFILT pin (the transition time is approximately 20 s). This behavior is detailed in Figure 25. During this charging transition, a high dv/dt transient on the inputs may briefly clip the outputs before the rail voltages charge to the full VCP level. This transitory clipping has been found to be inaudible in listening tests. When the charge pump transitions from the higher set of rail voltages to the lower set, there is a one second delay before the charge pump supplies the lower rail voltages to the amplifiers. This hysteresis ensures that the charge pump does not toggle between the two rail voltages as signals approach the clip threshold. It also prevents clipping in the instance of repetitive high level transients in the input signal. The diagram for this transitional behavior is detailed in Figure 26. 42 DS851F2 CS42L56 Output Level 1 second -10 dB Time Amplifier Rail Voltage VCP VCP 2 Time - VCP 2 - VCP Figure 26. VHPFILT Hysteresis 4.5.3 Efficiency As discussed in previous sections, the amplifiers internal to the CS42L56 operate from one of two sets of rail voltages, based upon the needs of the signal being amplified or the total gain/attenuation settings. The power curves for the two modes of operation are shown in Figure 27 and Figure 28. This graph details the power supplied to a load versus the power drawn from the supply for each of the three use cases. All Supplies= 1.8 V RL = 32 VCP Class AB Amplifiers do not conserve power with typical headphone loads. Class H Amplifiers automatically switch between VCP and VCP/2 to conserve power with typical headphone loads. VCP/2 Figure 27. Class H Power to Load vs. Power from VCP Supply - 32 DS851F2 43 CS42L56 When the rail voltages are set to VCP, the amplifiers will operate in their least efficient mode. When the rail voltages are held at VCP/2, the amplifiers will operate in their most efficient mode, but will be clipped if required to amplify a full-scale signal. Note: The VCP/2 curve ends at the point at which the output of the amplifiers reaches 10% THD+N. The benefit of Bi-Modal Class H is shown in the solid trace on the graph. At lower output levels, the amplifiers operate on the VCP/2 curve. At higher output levels, they operate on the VCP curve. The duration the amplifiers will operate on either of the two curves (VCP/2 or VCP) depends on both the content and the output level of the program material being amplified. The highest efficiency operation will result from maintaining an output level that is close to, but not exceeding, the clip threshold of the VCP/2 curve. All Supplies= 1.8 V RL = 16 Figure 28. Class H Power to Load vs. Power from VCP Supply - 16 4.6 Beep Generator The Beep Generator generates audio frequencies across approximately two octave major scales. It offers three modes of operation: Continuous, multiple, and single (one-shot) beeps. Sixteen On and eight Off times are available. It should be noted that the beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be necessary to set the beep volume sufficiently below the threshold to prevent the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep volume, the DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits. 44 DS851F2 CS42L56 BEEP[1:0] = '11' CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared. BEEP[1:0] = '10' MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared. BEEP[1:0] = '01' SINGLE-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME. BEEP must be cleared and set for additional beeps. ... BPVOL[4:0] FREQ[3:0] ONTIME[3:0] OFFTIME[2:0] Figure 29. Beep Configuration Options 4.7 Referenced Control Register Location MSTxVOL[7:0]..................... PMIXxVOL[6:0].................... OFFTIME[2:0]...................... ONTIME[3:0] ....................... FREQ[3:0] ........................... BEEP[1:0]............................ BPVOL[4:0] ......................... "Master Volume Control: MSTA (Address 13h) & MSTB (Address 14h)" on page 70 "PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h)" on page 68 "Beep Off Time" on page 71 "Beep On Time" on page 71 "Beep Frequency" on page 70 "Beep Configuration" on page 72 "Beep Volume" on page 72 Limiter When enabled, the limiter monitors the digital input signal before the DAC modulators, detects when levels exceed the maximum threshold settings and lowers the master volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume returns to its original level set in the Master Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp settings and sample rate, Fs. Limiter soft ramp dependency may be independently enabled/disabled using the LIMSRDIS. It should be noted that the Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds Recommended settings: Best limiting performance may be realized with a fast attack and a slow release setting with soft ramp enabled in the control registers. The CUSH bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. Referenced Control Register Location Limiter Rates ....................... Limiter Thresholds LIMSRDIS............................ Master Volume Control ........ "Limiter Release Rate" on page 86, "Limiter Attack Rate" on page 87 "Limiter Maximum Threshold" on page 85, "Limiter Cushion Threshold" on page 85 "Limiter Soft Ramp Disable" on page 82 "Master Volume Control: MSTA (Address 13h) & MSTB (Address 14h)" on page 70 DS851F2 45 CS42L56 Input MAX[2:0] Limiter ATTACK/RELEASE SOUND CUSHION Volume Output (after Limiter) CUSH[2:0] MAX[2:0] ARATE[5:0] RRATE[5:0] Figure 30. Peak Detect & Limiter 4.8 Serial Port Clocking The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated clocks in Slave Mode (M/S = 0b) and will generate synchronous clocks derived from an input master clock (MCLK) in Master Mode (M/S = 1b). The RATIO[4:0] bits need to be set appropriately according to the clocks being used in the system for correct device functionality. Table 3. "Serial Port Clock Ratio Settings" beginning on page 47 shows possible clock frequencies achievable by the CS42L56 serial port and provides a reference on how the RATIO[4:0] bits need to be configured for different clock ratios. Figure 31 shows how SCLK and LRCK are internally derived in Master Mode. MCLK (MHz) LRCK (kHz) 22.5792 11.0250 22.0500 44.1000 11.0250 22.0500 44.1000 11.0250 22.0500 44.1000 (MKPREDIV=1b) (MCLKDIV2=1b) 11.2896 (MKPREDIV=0b) (MCLKDIV2=1b) 5.6448 (MKPREDIV=0b) (MCLKDIV2=0b) MCLK/ LRCK Clock Ratio 2048 1024 512 1024 512 256 512 256 128 SCLK (MHz) 0.7056 1.4112 2.8224 0.7056 1.4112 2.8224 0.7056 1.4112 2.8224 MCLK/SCLK Clock Ratio 32 16 8 16 8 4 8 4 2 RATIO[4:0] 11000 10000 01000 11000 10000 01000 11000 10000 01000 Table 3. Serial Port Clock Ratio Settings 46 DS851F2 CS42L56 MCLK (MHz) 24.0000 (MKPREDIV=1b) (MCLKDIV2=1b) 12.0000 (MKPREDIV=0b) (MCLKDIV2=1b) 6.0000 (MKPREDIV=0b) (MCLKDIV2=0b) 24.5760 (MKPREDIV=1b) (MCLKDIV2=1b) 12.2880 (MKPREDIV=0b) (MCLKDIV2=1b) 6.1440 (MKPREDIV=0b) (MCLKDIV2=0b) LRCK (kHz) 8.0000 11.0294 12.0000 16.0000 22.0588 24.0000 32.0000 44.1180 48.0000 8.0000 11.0294 12.0000 16.0000 22.0588 24.0000 32.0000 44.1180 48.0000 8.0000 11.0294 12.0000 16.0000 22.0588 24.0000 32.0000 44.1180 48.0000 8.0000 12.0000 16.0000 24.0000 32.0000 48.0000 8.0000 12.0000 16.0000 24.0000 32.0000 48.0000 8.0000 12.0000 16.0000 24.0000 32.0000 48.0000 MCLK/ LRCK Clock Ratio 3000 2176 2000 1500 1088 1000 750 544 500 1500 1088 1000 750 544 500 375 272 250 750 544 500 375 272 250 187.5 136 125 3072 2048 1536 1024 768 512 1536 1024 768 512 384 256 768 512 384 256 192 128 SCLK (MHz) 0.496 0.75 0.744 0.992 1.500 1.488 1.984 3.000 2.976 0.496 0.75 0.744 0.992 1.500 1.488 1.984 3.000 2.976 0.496 0.75 0.744 0.992 1.500 1.488 1.984 3.000 2.976 0.512 0.768 1.024 1.536 2.048 3.072 0.512 0.768 1.024 1.536 2.048 3.072 0.512 0.768 1.024 1.536 2.048 3.072 MCLK/SCLK Clock Ratio ~48 32 ~32 ~24 16 ~16 ~12 8 ~8 ~24 16 ~16 ~12 8 ~8 ~6 4 ~4 ~12 8 ~8 ~6 4 ~4 ~3 2 ~2 48 32 24 16 12 8 24 16 12 8 6 4 12 8 6 4 3 2 RATIO[4:0] 11101 11011 11001 10101 10011 10001 01101 01011 01001 11101 11011 11001 10101 10011 10001 01101 01011 01001 11101 11011 11001 10101 10011 10001 01101 01011 01001 11100 11000 10100 10000 01100 01000 11100 11000 10100 10000 01100 01000 11100 11000 10100 10000 01100 01000 Table 3. Serial Port Clock Ratio Settings (Continued) DS851F2 47 CS42L56 RATIO[4:0] MCLKDIS MCLKPREDIV MCLK MCLKDIV2 1 0 2 1 1 0 2 1 125 128 136 187.5 192 250 256 272 375 384 500 512 544 750 768 01001 01000 01011 01101 01100 10001 10000 10011 10101 10100 11001 11000 11011 11100 11101 LRCK SCK=MCK[1:0] NOTE: The SCLK divide ratios shown in the figure are not accurate when MCLK is a multiple of 6 MHz. For accurate SCLK frequency values please refer to Table 3. "Serial Port Clock Ratio Settings" beginning on page 47 and Note 21 on page 23. 010 011 100 101 110 111 00 SCLK RATIO[4:2] 10 11 Figure 31. Serial Port Timing in Master Mode 48 Referenced Control Register Location SCK=MCK[1:0] .................... MKPREDIV........................... MCLKDIV2........................... MCLKDIS............................. RATIO[4:0]........................... "SCLK Equals MCLK" on page 60 "MCLK Pre-Divide" on page 60 "MCLK Divide" on page 61 "MCLK Disable" on page 61 "Clock Ratio" on page 62 DS851F2 CS42L56 4.9 Digital Interface Format The serial port operates in standard IS or Left-Justified digital interface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 32-33 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 23 for exact timing relationship between clocks and data. For additional information, application note AN282 presents a tutorial of the 2-channel serial audio interface. AN282 can be downloaded from the Cirrus Logic web site at http://www.cirrus.com. LRCK L eft C h a n n el R ig ht C h a n n el SCLK SDIN MSB M SB LSB AOUTA / AINxA MSB LSB AOUTB / AINxB Figure 32. IS Format LRCK L eft C h a n n el R ig ht C h a n n el SCLK SDIN MSB LS B AOUTA / AINxA MSB LS B MSB AOUTB / AINxB Figure 33. Left-Justified Format 4.10 Initialization The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The charge pump, LDO, internal voltage reference and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in the "Register Description" on page 58. After the PDN bit is released and MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. MCLK occurrences are counted over one LRCK period to determine a valid MCLK/LRCK ratio and normal operation begins. 4.11 Recommended DAC to HP or Line Power Sequence 4.11.1 Power-Up Sequence 1. Hold RESET low until the power supplies are stable. Note: VA must be applied prior to VCP to maintain the relationship specified in "Recommended Operating Conditions" on page 14. RESET should be held low for a minimum of 1 ms after power supplies are stable. 2. Apply MCLK at the appropriate frequency, as discussed in Section 4.8. SCLK may be applied or set to master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1. 3. Bring RESET high. DS851F2 49 CS42L56 4. Wait a minimum of 500 ns before writing to the control port. 5. The default state of the master power down bit, PDN, is 1b. Load the following register settings while keeping the PDN bit set to 1b. 6. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation. Register Controls: PDN_HPx[1:0], PDN_LINx[1:0] 7. Configure the serial port I/O control for master or slave operation. Register Controls: M/S 8. Configure the master clock (MCLK) and bit clock (SCLK) I/O control as desired. Refer to 4.8 "Serial Port Clocking" on page 47 for the required configuration for a given master clock. Register Controls: MKPREDIV, MCLKDIV2, SCLK=MCLK 9. Configure the sample rate (LRCK) controls for the desired sample rate. Refer to 4.8 "Serial Port Clocking" on page 47 for the required configuration for a given sample rate. Register Controls: See Register 05h 10. The default state of the DSP engine's power down bit, PDN_DSP, is 0b. It is not necessary to power down the DSP before changing the various DSP functions. The DSP may be powered down for additional power savings. 11. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 12. After muting the headphone or line amplifiers, set the PDN bit to 0b. 13. Wait 75 ms for the headphone or line amplifier to power up. 14. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level. 15. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 4.11.2 Power Up Sequence Register Location Step 5, 12 ............................ Step 6 .................................. Steps 7-8 ............................. Step 9 .................................. Step 10 ................................ Step 11a,14a ....................... Step 11b,14b ....................... "Power Down" on page 59 "Power Control 2 (Address 04h)" on page 59 "Clocking Control 1 (Address 05h)" on page 60 "Clocking Control 2 (Address 06h)" on page 61 "Power Down DSP" on page 66 "Headphone Channel x Mute" on page 83, "Line Channel x Mute" on page 84 "Headphone Volume Control" on page 84, "Line Volume Control" on page 84 Power-Down Sequence 1. To minimize pops during volume transitions, mute the master volume with soft ramp enabled. Register Controls: MSTxMUTE, DIGSFT 2. The required wait time for muting the master volume as described in 1 above depends on the soft ramp rate, initial master volume setting and sample rate. For example, if the master volume is set to 0 dB and the sample rate is 48 kHz, the required wait time is at least: 8 [soft ramp rate is 1/8 dB per LRCK] x 102 [volume must transition from 0 dB to -102 dB] x 21 s [period of 48 kHz LRCK] = 17 ms. Wait at least [the delay required according to the details in this step]. 3. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 4. Disable soft ramp and zero cross volume transitions. Register Controls: ANLGSFT, ANLGZC, DIGSFT 5. Set the PDN bit to `1'b. 6. Wait at least 100 s. 50 DS851F2 CS42L56 The CODEC will be fully powered down after this 100 s delay. Prior to the removal of the master clock (MCLK), this delay of at least 100 s must be implemented after step 5 to avoid premature disruption of the CODEC's power down sequence. A disruption in the CODEC's power down sequence may abruptly stop the charge pump, causing the headphone and/or line amplifiers to drive the outputs up to the VCP supply. Such disruption may also cause clicks and pops on the output of the DAC's. 7. Optionally, MCLK may be removed at this time. 8. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be reset to their default state. 9. Power Supply Removal (Option 1): Switch power supplies to a high impedance state. Note: VCP must be removed prior to VA to maintain the relationship specified in "Recommended Operating Conditions" on page 14. 10. Power Supply Removal (Option2): To minimize pops when the power supplies are pulled to ground, a discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M resistor and a 2.2 F capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds. After step 5, wait the required time for FILT+ to ramp to ground before pulling VA to ground. Note: VCP must be pulled to ground prior to VA to maintain the relationship specified in "Recommended Operating Conditions" on page 14. 4.12 Power Down Sequence Register Location Step 1a ................................ Step 1b ................................ Step 4 .................................. Step 5 .................................. "Headphone Volume Control" on page 84, "Line Volume Control" on page 84 "Headphone Channel x Mute" on page 83, "Line Channel x Mute" on page 84 "Analog Soft Ramp" on page 64, "Analog Zero Cross" on page 64, "Digital Soft Ramp" on page 64 "Power Down" on page 59 Recommended PGA to HP or Line Power Sequence (Analog Passthrough) 4.12.1 Power-Up Sequence 1. Hold RESET low until the power supplies are stable. Note: VA must be applied prior to VCP to maintain the relationship specified in "Recommended Operating Conditions" on page 14. RESET should be held low for a minimum of 1 ms after power supplies are stable. 2. Apply MCLK at the appropriate frequency. 3. Bring RESET high. 4. Wait a minimum of 500 ns before writing to the control port. 5. The default state of the master power down bit, PDN, is `1'b. Load the following register settings while keeping the PDN bit set to `1'b. 6. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation. Register Controls: PDN_HPx[1:0], PDN_LINx[1:0] 7. Configure the HP and/or Line amplifiers to receive the analog output from the PGA. Register Controls: LINExMUX, HPxMUX 8. Power down the DSP engine. Register Controls: PDN_DSP 9. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 10. After muting the headphone and/or line amplifiers, set the PDN bit to `0'b. 11. Wait 75 ms for the headphone or line amplifier to power up. 12. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level. DS851F2 51 CS42L56 13. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. Power Up Sequence Register Location Step 5, 10 ............................ Step 6 .................................. Steps 7 ................................ Step 8 .................................. Step 9a,12a ......................... Step 9b,12b ......................... "Power Down" on page 59 "Power Control 2 (Address 04h)" on page 59 "AIN Reference Configuration, ADC MUX (Address 1Ah)" on page 74 "Power Down DSP" on page 66 "Headphone Channel x Mute" on page 83, "Line Channel x Mute" on page 84 "Headphone Volume Control" on page 84, "Line Volume Control" on page 84 4.12.2 Power-Down Sequence 1. To minimize pops on the headphone and/or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. To reduce the volume transition delay while minimizing pops, enable the analog zero cross function and disable the analog soft ramp function. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0], ANLGSFT, ANLGZC 2. The required wait time for muting the analog volume as described in 1 above depends on the worst case zero cross timeout of 150 ms in passthrough mode. Wait at least 150 ms. 3. Disable soft ramp and zero cross volume transitions. Register Controls: ANLGZC, DIGSFT 4. Set the PDN bit to `1'b. 5. Wait at least 100 s. The CODEC will be fully powered down after this 100 s delay. Prior to the removal of the master clock (MCLK), this delay of at least 100 s must be implemented after step 4 to avoid premature disruption of the CODEC's power down sequence. A disruption in the CODEC's power down sequence may abruptly stop the charge pump, causing the headphone and/or line amplifiers to drive the outputs up to the VCP supply. Such disruption may also cause clicks and pops on the output of the DAC's. 6. Optionally, MCLK may be removed at this time. 7. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be reset to their default state. 8. Power Supply Removal (Option 1): Switch power supplies to a high impedance state. Note: VCP must be removed prior to VA to maintain the relationship specified in "Recommended Operating Conditions" on page 14. 9. Power Supply Removal (Option 2): To minimize pops when the power supplies are pulled to ground, a discharge resistor must be added in parallel with the capacitor on the FILT+ pin. With a 1 M resistor and a 2.2 F capacitor on FILT+, FILT+ will ramp to ground in approximately 5 seconds. After step 5, wait the required time for FILT+ to ramp to ground before pulling VA to ground. Note: VCP must be pulled to ground prior to VA to maintain the relationship specified in "Recommended Operating Conditions" on page 14. 52 Power Down Sequence Register Location Step 1a................................ Step 1b................................ Step 1c ................................ Step 3.................................. Step 4.................................. "Analog Soft Ramp" on page 64, "Analog Zero Cross" on page 64 "Headphone Volume Control" on page 84, "Line Volume Control" on page 84 "Headphone Channel x Mute" on page 83, "Line Channel x Mute" on page 84 , "Analog Zero Cross" on page 64, "Digital Soft Ramp" on page 64 "Power Down" on page 59 DS851F2 CS42L56 4.13 Control Port Operation The control port is used to access the registers allowing the CODEC to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The device enters software mode only after a successful write command using one of two software protocols: SPI or IC, with the device acting as a slave. The SPI protocol is permanently selected whenever there is a high-to-low transition on the AD0/CS pin after reset. If using the IC protocol, pin AD0/CS should be permanently connected to either VL or GND; this option allows the user to slightly alter the chip address as desired. 4.13.1 SPI Control In Software Mode, CS is the CS42L56 chip-select signal, CCLK is the control port bit clock (input into the CS42L56 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ignored. Figure 34 shows the operation of the control port in Software Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS (WRITE) CDIN 1 0 0 1 0 1 0 MAP BYTE 0 INCR 6 5 4 3 DATA +n DATA 2 1 0 7 6 1 0 7 6 1 0 Figure 34. Control Port Timing in SPI Mode 4.13.2 IC Control SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. The signal timings for a read and write cycle are shown in Figure 35 and Figure 36. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L56 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the address field are fixed at 100101. Pin ADO forms the least significant bit of the chip address and should be connected to VL or DGND as desired. To communicate with the CS42L56, the chip address field, which is the first byte sent to the CS42L56, should match 100101+AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP); the MAP selects the register to be read or written. If the operation is a read, the contents of the DS851F2 53 CS42L56 register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42L56 after each input byte is read and is input to the CS42L56 from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 24 25 26 27 28 19 SCL CHIP ADDRESS (WRITE) 1 SDA 0 0 1 0 1 AD0 MAP BYTE 0 INCR 6 5 4 3 2 1 0 ACK 7 6 1 ACK DATA +n DATA +1 DATA 0 7 6 1 0 7 6 1 0 ACK ACK STOP START Figure 35. Control Port Timing, IC Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 1 0 0 1 STOP MAP BYTE 0 1 AD0 0 INCR 6 5 4 3 2 1 ACK CHIP ADDRESS (READ) 1 0 0 0 1 0 1 AD0 1 ACK START DATA START 7 ACK DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 36. Control Port Timing, IC Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 36, the write operation is aborted (after the acknowledge for the MAP byte) by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10010100 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto-increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10010101 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 4.13.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.13.3.1 Map Increment (INCR) The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. 54 DS851F2 CS42L56 5. REGISTER QUICK REFERENCE Default values are shown below the bit names. Unless otherwise specified, all "Reserved" bits must maintain their default value. Adr. Function 01h ID 1 p 58 (Read Only) 7 DEVID7 x 6 DEVID6 x 5 DEVID5 x 4 DEVID4 x 3 DEVID3 x 2 DEVID2 x 1 DEVID1 x 0 DEVID0 x AREVID1 x AREVID0 x MTLREVID1 x MTLREVID0 x PDN 1 PDN_LINA0 1 MCLKDIS 0 RATIO0 1 Reserved 0 CHGFREQ0 1 FREEZE 0 ADCAOVFL 0 02h ID 2 p 58 (Read Only) 03h Power Ctl 1 p 58 04h Power Ctl 2 p 59 05h Clocking Ctl 1 p 60 06h Clocking Ctl 2 p 61 07h Serial Format p 62 08h Class H Ctl p 63 09h Misc. Ctl p 63 0Ah Status p 65 (Read Only) Reserved x Reserved x Reserved x AREVID2 x Reserved 1 PDN_HPB1 1 Reserved 0 Reserved 0 Reserved 0 ADPTPWR1 0 DIGMUX 0 HPDETECT 0 Reserved 1 PDN_HPB0 1 M/S 0 Reserved 0 Reserved 0 ADPTPWR0 0 Reserved 0 SPCLKERR 0 PDN_VBUF 1 PDN_HPA1 1 INV_SCLK 0 AUTO 0 Reserved 0 Reserved 0 Reserved 0 DSPBOVFL 0 PDN_BIAS 1 PDN_HPA0 1 SCK=MCK1 0 RATIO4 0 Reserved 0 Reserved 0 ANLGSFT 0 DSPAOVFL 0 PDN_CHRG PDN_ADCB PDN_ADCA 1 1 1 PDN_LINB1 PDN_LINB0 PDN_LINA1 1 1 1 SCK=MCK0 MKPREDIV MCLKDIV2 0 0 0 RATIO3 RATIO2 RATIO1 1 0 1 DIF Reserved Reserved 0 0 0 CHGFREQ3 CHGFREQ2 CHGFREQ1 0 1 0 ANLGZC DIGSFT Reserved 1 1 0 MIXBOVFL MIXAOVFL ADCBOVFL 0 0 0 0Bh p 66 0Ch p 67 0Dh p 67 0Eh p 67 0Fh p 68 10h p 68 11h p 69 PDN_DSP 0 AMIXBMUTE 1 AMIXAVOL7 0 AMIXBVOL7 0 PMIXAVOL7 0 PMIXBVOL7 0 AINADV7 0 DEEMPH 0 AMIXAMUTE 1 AMIXAVOL6 0 AMIXBVOL6 0 PMIXAVOL6 0 PMIXBVOL6 0 AINADV6 0 Reserved 0 PMIXBMUTE 0 AMIXAVOL5 0 AMIXBVOL5 0 PMIXAVOL5 0 PMIXBVOL5 0 AINADV5 0 PLYBCKB=A 0 PMIXAMUTE 0 AMIXAVOL4 0 AMIXBVOL4 0 PMIXAVOL4 0 PMIXBVOL4 0 AINADV4 0 INV_PCMB 0 Reserved 0 AMIXAVOL3 0 AMIXBVOL3 0 PMIXAVOL3 0 PMIXBVOL3 0 AINADV3 0 INV_PCMA 0 Reserved 0 AMIXAVOL2 0 AMIXBVOL2 0 PMIXAVOL2 0 PMIXBVOL2 0 AINADV2 0 DINADV7 0 DINADV6 0 DINADV5 0 DINADV4 0 DINADV3 0 DINADV2 0 DINADV1 0 DINADV0 0 p 70 14h Master B Vol p 70 15h BEEP Freq, p 70 On Time MSTAVOL7 0 MSTBVOL7 0 FREQ3 0 MSTAVOL6 0 MSTBVOL6 0 FREQ2 0 MSTAVOL5 0 MSTBVOL5 0 FREQ1 0 MSTAVOL4 0 MSTBVOL4 0 FREQ0 0 MSTAVOL3 0 MSTBVOL3 0 ONTIME3 0 MSTAVOL2 0 MSTBVOL2 0 ONTIME2 0 MSTAVOL1 0 MSTBVOL1 0 ONTIME1 0 MSTAVOL0 0 MSTBVOL0 0 ONTIME0 0 16h BEEP Vol, p 71 Off Time OFFTIME2 0 OFFTIME1 0 OFFTIME0 0 BPVOL4 0 BPVOL3 0 BPVOL2 0 BPVOL1 0 BPVOL0 0 17h BEEP, p 72 Tone Cfg. BEEP1 0 BEEP0 0 Reserved 0 TREB_CF1 0 TREB_CF0 0 BASS_CF1 0 BASS_CF0 0 TC_EN 0 Playback Ctl DSP Mute Ctl ADCMIXA Vol ADCMIXB Vol PCMMIXA Vol PCMMIXB Vol Analog Input Advisory Vol 12h Digital Input p 69 Advisory Vol 13h Master A Vol Reserved Reserved 0 0 MSTBMUTE MSTAMUTE 0 0 AMIXAVOL1 AMIXAVOL0 0 0 AMIXBVOL1 AMIXBVOL0 0 0 PMIXAVOL1 PMIXAVOL0 0 0 PMIXBVOL1 PMIXBVOL0 0 0 AINADV1 AINADV0 0 0 TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 18h Tone Ctl p 73 1 0 0 0 1 0 0 19h Channel Mixer PCMBSWP1 PCMBSWP0 PCMASWP1 PCMASWP0 ADCBSWP1 ADCBSWP0 ADCASWP1 p 74 & Swap 0 0 0 0 0 0 0 BASS0 0 ADCASWP0 0 1Ah AIN Ref Conp 74 fig, ADC MUX ADCAMUX0 0 DS851F2 AIN2B_REF 0 AIN2A_REF 0 AIN1B_REF 0 AIN1A_REF 0 ADCBMUX1 ADCBMUX0 ADCAMUX1 0 0 0 55 CS42L56 Adr. 1Bh p 75 1Ch p 76 1Dh p 77 1Eh p 77 1Fh p 77 20h p 78 21h p 78 22h p 79 23h p 79 24h p 80 Function HPF Ctl Misc. ADC Ctl 7 HPFB 1 ADCB=A 0 PREAMPB1 0 6 HPFRZB 0 PGAB=A 0 PREAMPB0 0 5 HPFA 1 DIGSUM1 0 PREAMPA1 0 4 HPFRZA 0 DIGSUM0 0 PREAMPA0 0 Gain & Bias Ctl PGAAMUX1 PGAAMUX0 PGAAVOL5 PGAAVOL4 PGAA MUX, 0 0 0 0 Vol PGABMUX1 PGABMUX0 PGABVOL5 PGABVOL4 PGAB MUX, 0 0 0 0 Vol ADCA Attenu- ADCAATT7 ADCAATT6 ADCAATT5 ADCAATT4 0 0 0 0 ator ADCBATT7 ADCBATT6 ADCBATT5 ADCBATT4 ADCB Attenu0 0 0 0 ator ALCB ALCA ALCARATE5 AALCRATE4 ALC Enable, 0 0 0 0 Attack Rate ALC_ALL Reserved ALCRRATE5 ALCRRATE4 ALC Release 1 0 1 1 Rate ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALC Thresh0 0 0 0 olds NGALL 25h Noise Gate Ctl p 81 0 26h ALC, Limiter ALCASRDIS p 82 SFT, ZC 0 3 HPFB_CF1 0 INV_ADCB 0 BOOSTB 0 2 HPFB_CF0 0 INV_ADCA 0 BOOSTA 0 1 HPFA_CF1 0 ADCBMUTE 0 BIAS_LVL1 0 0 HPFA_CF0 0 ADCAMUTE 0 BIAS_LVL0 0 PGAAVOL3 0 PGAAVOL2 0 PGAAVOL1 0 PGAAVOL0 0 PGABVOL3 0 PGABVOL2 0 PGABVOL1 0 PGABVOL0 0 ADCAATT3 0 ADCAATT2 0 ADCAATT1 0 ADCAATT0 0 ADCBATT3 0 ADCBATT2 0 ADCBATT1 0 ADCBATT0 0 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0 0 0 0 0 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0 1 1 1 1 ALCMIN1 0 ALCMIN0 0 Reserved 0 Reserved 0 NG 0 ALCAZCDIS 0 NGBOOST 0 ALCBSRDIS 0 THRESH2 0 ALCBZCDIS 0 THRESH1 0 LIMSRDIS 0 THRESH0 0 Reserved 0 NGDELAY1 0 Reserved 0 NGDELAY0 0 Reserved 0 27h AMUTE, Line p 83 & HP MUX AMUTE 0 Reserved 0 Reserved 0 Reserved 0 LINEBMUX 0 LINEAMUX 0 HPBMUX 0 HPAMUX 0 28h Headphone A p 83 Volume HPAMUTE 0 HPAVOL6 0 HPAVOL5 0 HPAVOL4 0 HPAVOL3 0 HPAVOL2 0 HPAVOL1 0 HPAVOL0 0 29h Headphone B p 83 Volume HPBMUTE 0 HPBVOL6 0 HPBVOL5 0 HPBVOL4 0 HPBVOL3 0 HPBVOL2 0 HPBVOL1 0 HPBVOL0 0 2Ah Line A p 84 Volume LINEAMUTE 0 LINEAVOL6 0 LINEAVOL5 0 LINEAVOL4 0 LINEAVOL3 0 LINEAVOL2 0 LINEAVOL1 0 LINEAVOL0 0 2Bh Line B p 84 Volume LINEBMUTE 0 LINEBVOL6 0 LINEBVOL5 0 LINEBVOL4 0 LINEBVOL3 LINEBVOL2 LINEBVOL1 0 0 0 LINEBVOL0 0 2Ch Limit Threshp 85 olds Control 2Dh Limit Ctl, p 86 Release Rate LMAX2 0 LMAX1 0 LMAX0 0 CUSH2 0 LIMIT 0 LIMIT_ALL 1 LIMRRATE5 1 LIMRRATE4 1 LIMRRATE3 LIMRRATE2 LIMRRATE1 1 1 1 LIMRRATE0 1 2Eh Limiter Attack p 87 Rate Reserved 0 Reserved 0 LIMARATE5 0 LIMARATE4 0 LIMARATE3 LIMARATE2 LIMARATE1 0 0 0 LIMARATE0 0 56 CUSH1 0 CUSH0 0 Reserved 0 Reserved 0 DS851F2 CS42L56 6. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and revision register and the status register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. Unless otherwise specified, all "Reserved" bits must maintain their default value. IC Address: 1001010[R/W] 6.1 Device I.D. Register (Address 01h) (Read Only) 7 6 5 4 3 2 1 0 DEVID7 DEVID6 DEVID5 DEVID4 DEVID3 DEVID2 DEVID1 DEVID0 6.1.1 Device I.D. (Read Only) Device I.D. code for the CS42L56. 6.2 DEVID[7:0] Part Number 01010110 CS42L56 Device Revision Register (Address 02h) (Read Only) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved AREVID2 AREVID1 AREVID0 MTLREVID1 MTLREVID0 6.2.1 Alpha Revision (Read Only) CS42L56 alpha revision level. 6.2.2 AREVID[2:0] Alpha Revision Level 000 A Numeric Revision (Read Only) CS42L56 numeric revision level. 6.3 MTLREVID[1:0] Metal Revision Level 00 0 Power Control 1 (Address 03h) 7 6 5 4 3 2 1 0 Reserved Reserved PDN_VBUF PDN_BIAS PDN_CHRG PDN_ADCB PDN_ADCA PDN 6.3.1 Power Down VCM Bias Buffer Configures the power state of the weak internal VCM buffer. DS851F2 PDN_VBUF Weak VCM Status 0 All weak VCM buffers for the AINx inputs that are not selected (either through ADCxMUX[1:0] or PGAxMUX[1:0]) are powered up. The weak VCM buffers for the AINx inputs that are selected are powered down. 1 All weak VCM buffers are powered down. Application: "Optional VCM Buffer" on page 35 57 CS42L56 6.3.2 Power Down MIC Bias Configures the power state of the microphone bias output. 6.3.3 PDN_BIAS MIC Bias Status 0 Powered Up 1 Powered Down Power Down ADC Charge Pump Configures the power state of the ADC charge pump. For optimal ADC performance and power consumption, set to 1b when VA > 2.1 V and set to 0b when VA < 2.1 V. 6.3.4 PDN_CHRG ADC Charge Pump Status 0 Powered Up 1 Powered Down Power Down ADC x Configures the power state of ADC channel x. 6.3.5 PDN_ADCx ADC Status 0 Powered Up 1 Powered Down Power Down Configures the power state of the entire CODEC. 6.4 PDN CODEC Status 0 Powered Up 1 Powered Down Power Control 2 (Address 04h) 7 6 5 4 3 2 1 0 PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_LINB1 PDN_LINB0 PDN_LINA1 PDN_LINA0 6.4.1 Headphone Power Control Configures how the HPDETECT pin, controls the power for the headphone amplifier. 58 PDN_HPx[1:0] Headphone Status 00 Headphone channel is ON when the HPDETECT pin, is LO. Headphone channel is OFF when the HPDETECT pin, is HI. 01 Headphone channel is ON when the HPDETECT pin, is HI. Headphone channel is OFF when the HPDETECT pin, is LO. 10 Headphone channel is always ON. 11 Headphone channel is always OFF. DS851F2 CS42L56 6.4.2 Line Power Control Configures how the HPDETECT pin, 29, controls the power for the line amplifier. 6.5 PDN_LINx[1:0] Line Status 00 Line channel is ON when the HPDETECT pin, is LO. Line channel is OFF when the HPDETECT pin, is HI. 01 Line channel is ON when the HPDETECT pin, is HI. Line channel is OFF when the HPDETECT pin, is LO. 10 Line channel is always ON. 11 Line channel is always OFF. Clocking Control 1 (Address 05h) 7 6 5 4 3 2 1 0 Reserved M/S INV_SCLK SCK=MCK1 SCK=MCK0 MKPREDIV MCLKDIV2 MCLKDIS 6.5.1 Master/Slave Mode Configures the serial port I/O clocking. 6.5.2 M/S Serial Port Clocks 0 Slave (Input ONLY) 1 Master (Output ONLY) Application: "Serial Port Clocking" on page 47 SCLK Polarity Configures the polarity of the SCLK signal. 6.5.3 INV_SCLK SCLK Polarity 0 Not Inverted 1 Inverted SCLK Equals MCLK Configures the SCLK signal source and speed for master mode. SCK=MCK[1:0] Output SCLK 00 Re-timed, bursted signal with minimal speed needed to clock the required data samples 01 Reserved 10 MCLK signal after the MCLK divide by 2 (MCLKDIV2) circuit 11 MCLK signal before the MCLK divide by 2 (MCLKDIV2) circuit Note: The SCK=MCK[1:0] bits must be set to "00" when the device is in slave mode. 6.5.4 MCLK Pre-Divide Configures a divide of the input MCLK prior to all internal circuitry. DS851F2 MKPREDIV MCLK signal into CODEC 0 No divide 1 Divided by 2 Application: "Serial Port Clocking" on page 47 59 CS42L56 6.5.5 MCLK Divide Configures a divide of the MCLK after the MCLK pre-divide. 6.5.6 MCLKDIV2 MCLK signal into CODEC 0 No divide 1 Divided by 2 Application: "Serial Port Clocking" on page 47 MCLK Disable Configures the MCLK signal prior to all internal circuitry. MCLKDIS On 1 Off; Disables the clock tree to save power when the CODEC is powered down. Note: 6.6 MCLK signal into CODEC 0 This function should be enabled during power down (PDN=1) ONLY. Clocking Control 2 (Address 06h) 7 6 5 4 3 2 1 0 Reserved Reserved AUTO RATIO4 RATIO3 RATIO2 RATIO1 RATIO0 6.6.1 Clock Ratio Auto-Detect Configures the power status of the Auto-Detect circuitry. When enabled, the Auto-Detect circuitry detects when the LRCK changes and automatically adjusts internal clock divide-ratios eliminating the need of a register write to account for the change. It should be noted that the Auto-detect circuitry can only detect when the LRCK changes by a factor of two while the MCLK stays the same (for instance, Mclk = 6.000 MHz; LRCK changes from 48 kHz to 24 kHz). Any other major clock frequency changes must be accounted for by appropriate control port writes. AUTO Auto-detection of Clock Ratio 0 Disabled 1 Enabled Application: "Serial Port Clocking" on page 47 Note: When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 47. 60 DS851F2 CS42L56 6.6.2 Clock Ratio Configures the appropriate internal MCLK divide ratio for LRCK and SCLK. RATIO[4:0] MCLK/LRCK Ratio MCLK/SCLK Ratio 01000 128 2 01001 125 2 01011 136 2 01100 192 3 01101 187.5 3 10000 256 4 10001 250 4 10011 272 4 10100 384 6 10101 375 6 11000 512 8 11001 500 8 11011 544 8 11100 750 12 11101 768 12 Application: "Serial Port Clocking" on page 47 Notes: 1. Register settings not shown in the table are reserved. Use Table 3. "Serial Port Clock Ratio Settings" beginning on page 47 for determining the register settings based on the system master clock (MCLK), bit clock (SCLK) and frame clock (LRCK) frequencies. 6.7 Serial Format (Address 07h) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved DIF Reserved Reserved Reserved 6.7.1 CODEC Digital Interface Format Configures the digital interface format for data on SDOUT and SDIN. DIF CODEC Interface Format 0 IS 1 Left Justified Application: DS851F2 61 CS42L56 6.8 Class H Control (Address 08h) 7 6 5 4 3 2 1 0 ADPTPWR1 ADPTPWR0 Reserved Reserved CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 6.8.1 Adaptive Power Adjustment Configures how the power to the headphone and line amplifiers adapts to the output signal level. 6.8.2 ADPTPWR[1:0] Power Supply 00 Adapted to volume setting; Voltage level is determined by the sum of the relevant volume settings 01 Fixed - Headphone and Line Amp supply = VCP/2 10 Fixed - Headphone and Line Amp supply = VCP 11 Adapted to Signal; Voltage level is dynamically determined by the output signal Application: "Class H Amplifier" on page 39 Charge Pump Frequency Sets the charge pump frequency on FLYN and FLYP. CHGFREQ[3:0] N 0000 0 ... 0101 5 ... 1111 15 Formula: f MCLK Frequency = -------------------------4 N + 2 ; where fMCLK is the frequency of the MCLK signal after the MCLKDIV2 circuit. Notes: 1. The output THD+N performance improves at higher frequencies; power consumption increases at higher frequencies. 6.9 Misc. Control (Address 09h) 7 6 5 4 3 2 1 0 DIGMUX Reserved Reserved ANLGSFT ANLGZC DIGSFT Reserved FREEZE 6.9.1 Digital MUX Selects the signal source for the ADC serial port. DIGMUX 62 SDOUT Signal Source 0 ADC 1 DSP Mix DS851F2 CS42L56 6.9.2 Analog Soft Ramp Configures an incremental volume ramp from the current level to the new level at the specified rate. 6.9.3 ANLGSFT Volume Changes Affected Analog Volume Controls 0 Do not occur with a soft ramp 1 Occur with a soft ramp PGAx_VOL[5:0] ("PGAx Volume" on page 78) HPxMUTE ("Headphone Channel x Mute" on page 83) HPxVOL[6:0] ("Headphone Volume Control" on page 84) LINExMUTE ("Line Channel x Mute" on page 84) LINExVOL[6:0] ("Line Volume Control" on page 84) Ramp Rate: 1/8 dB every LRCK cycle Analog Zero Cross Configures when the signal level changes occur for the analog volume controls. ANLGZCx Volume Changes Affected Analog Volume Controls 0 Do not occur on a zero crossing 1 Occur on a zero crossing PGAx_VOL[5:0] ("PGAx Volume" on page 78) HPxMUTE ("Headphone Channel x Mute" on page 83) HPxVOL[6:0] ("Headphone Volume Control" on page 84) LINExMUTE ("Line Channel x Mute" on page 84) LINExVOL[6:0] ("Line Volume Control" on page 84) Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a timeout period between 1024 and 1536 sample periods (approximately 21.3 ms to 32 ms at 48 kHz sample rate). 6.9.4 Digital Soft Ramp Configures an incremental volume ramp from the current level to the new level at the specified rate. 6.9.5 DIGSFT Volume Changes Affected Digital Volume Controls 0 Do not occur with a soft ramp 1 Occur with a soft ramp ADCxMUTE ("ADC Mute" on page 76) ADCxATT[7:0] ("ADCx Volume" on page 78) AMIXxMUTE ("ADC Mixer Channel x Mute" on page 67) AMIXxVOL[6:0] ("ADC Mixer Channel x Volume" on page 67) PMIXxMUTE ("PCM Mixer Channel x Mute" on page 67) PMIXxVOL[6:0] ("PCM Mixer Channel x Volume" on page 68) MSTxMUTE ("Master Playback Mute" on page 67) MSTxVOL[7:0] ("Master Volume Control" on page 70) Ramp Rate: 1/8 dB every LRCK cycle Freeze Registers Configures a hold on all register settings. FREEZE Control Port Status 0 Register changes take effect immediately 1 Modifications may be made to all control port registers without the changes taking effect until after the FREEZE is disabled. Notes: 1. This bit should only be used to synchronize run-time controls, such as volume and mute, during normal operation. Using this bit before the relevant circuitry begins normal operation could cause the change to take effect immediately, ignoring the FREEZE bit. DS851F2 63 CS42L56 6.10 Status (Address 0Ah) (Read Only) Bits [6:0] in this register are "sticky". 1b means the associated error condition has occurred at least once since the register was last read. 0b means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets these bits to 0. Bit 7 is not "sticky" and will always indicate current status when the register is read. 7 6 5 4 3 2 1 0 HPDETECT SPCLKERR DSPBOVFL DSPAOVFL MIXBOVFL MIXAOVFL ADCBOVFL ADCAOVFL 6.10.1 HPDETECT Pin Status (Read Only) Indicates the status of the HPDETECT pin. HPDETECT Pin State 0 Low 1 High 6.10.2 Serial Port Clock Error (Read Only) Indicates the status of the MCLK to LRCK ratio. SPCLKERR Serial Port Clock Status: 0 MCLK/LRCK ratio is valid. 1 MCLK/LRCK ratio is not valid. Application: "Serial Port Clocking" on page 47 Note: nizes. On initial power up and application of clocks, this bit will report 1b as the serial port re-synchro- 6.10.3 DSP Engine Overflow (Read Only) Indicates the over-range status in the DSP data path. DSPxOVFL DSP Overflow Status: 0 No digital clipping has occurred in the data path after the DSP. 1 Digital clipping has occurred in the data path after the DSP. 6.10.4 MIXx Overflow (Read Only) Indicates the over-range status in the PCM mix data path. MIXxOVFL PCM Overflow Status: 0 No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP. 1 Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP. 6.10.5 ADCx Overflow (Read Only) Indicates the over-range status in the ADC signal path. 64 ADCxOVFL ADC Overflow Status: 0 No clipping has occurred anywhere in the ADC signal path. 1 Clipping has occurred in the ADC signal path. DS851F2 CS42L56 6.11 Playback Control (Address 0Bh) 7 6 5 4 3 2 1 0 PDN_DSP DEEMPH Reserved PLYBCKB=A INV_PCMB INV_PCMA Reserved Reserved 6.11.1 Power Down DSP Configures the power state of the DSP Engine. PDNDSP DSP Status DSP Engine Controls/Blocks 0 Powered Up 1 Powered Down AMIXxMUTE ("ADC Mixer Channel x Mute" on page 67) AMIXxVOL[6:0] ("ADC Mixer Channel x Volume" on page 67) PMIXxMUTE ("PCM Mixer Channel x Mute" on page 67) PMIXxVOL[6:0] ("PCM Mixer Channel x Volume" on page 68) Beep Generator, Tone Control, De-Emphasis 6.11.2 HP/Line De-Emphasis Configures a 15s/50s (when Fs = 44.1 kHz) digital de-emphasis filter response on the headphone and line outputs. DEEMPH 6.11.3 De-Emphasis Status 0 Disabled 1 Enabled Playback Channels B=A Configures independent or ganged volume and mute control of all playback channels. When enabled, the channel B settings are ignored and the channel A settings control channel A and channel B. PLYBCKB=A Single Volume Control for all Playback Channels 0 Disabled; Independent channel control. 1 Affected Volume Controls AMIXxMUTE ("ADC Mixer Channel x Mute" on page 67) AMIXxVOL[6:0] ("ADC Mixer Channel x Volume" on page 67) PMIXxMUTE ("PCM Mixer Channel x Mute" on page 67) PMIXxVOL[6:0] ("PCM Mixer Channel x Volume" on page 68) Enabled; Ganged channel control. Channel MSTxVOL[7:0] ("Master Volume Control" on page 70) A volume control controls channel B volume. HPxMUTE ("Headphone Channel x Mute" on page 83) HPxVOL[7:0] ("Headphone Volume Control" on page 84 LINExMUTE[7:0] ("Line Channel x Mute" on page 84) LINExVOL[7:0] ("Line Volume Control" on page 84) 6.11.4 Invert PCM Signal Polarity Configures the polarity of the digital input signal. DS851F2 INV_PCMx PCM Signal Polarity 0 Not Inverted 1 Inverted 65 CS42L56 6.12 DSP Mute Controls (Address 0Ch) 7 6 5 4 3 2 1 0 AMIXBMUTE AMIXAMUTE PMIXBMUTE PMIXAMUTE Reserved Reserved MSTBMUTE MSTAMUTE 6.12.1 ADC Mixer Channel x Mute Configures a digital mute on the ADC mix in the DSP Engine. AMIXxMUTE ADC Mixer Mute 0 Disabled 1 Enabled 6.12.2 PCM Mixer Channel x Mute Configures a digital mute on the PCM mix from the serial data input (SDIN) to the DSP Engine. PMIXxMUTE PCM Mixer Mute 0 Disabled 1 Enabled 6.12.3 Master Playback Mute Configures a digital mute on the master volume control for channel x. MSTxMUTE 6.13 Master Mute 0 Not muted. 1 Muted ADCx Mixer Volume: ADCA (Address 0Dh) & ADCB (Address 0Eh) 7 6 5 4 3 2 1 0 AMIXxVOL7 AMIXxVOL6 AMIXxVOL5 AMIXxVOL4 AMIXxVOL3 AMIXxVOL2 AMIXxVOL1 AMIXxVOL0 6.13.1 ADC Mixer Channel x Volume Sets the volume/gain of the ADC mix in the DSP Engine. 66 AMIXxVOL[7:0] Volume 0111 1111 +12 dB ... ... 0001 1000 +12 dB ... ... 0000 0001 +0.5 dB 0000 0000 0 dB 1111 1111 -0.5 dB ... ... 1000 1000 -60.0 dB 1000 0111 Mute ... ... 1000 0000 Mute Step Size: 0.5 dB DS851F2 CS42L56 6.14 PCMx Mixer Volume: PCMA (Address 0Fh) & PCMB (Address 10h) 7 6 5 4 3 2 1 0 PMIXxVOL7 PMIXxVOL6 PMIXxVOL5 PMIXxVOL4 PMIXxVOL3 PMIXxVOL2 PMIXxVOL1 PMIXxVOL0 6.14.1 PCM Mixer Channel x Volume Sets the volume/gain of the PCM mix from the serial data input (SDIN) to the DSP Engine. DS851F2 PMIXxVOL[7:0] Volume 0111 1111 +12 dB ... ... 0001 1000 +12 dB ... ... 0000 0001 +0.5 dB 0000 0000 0 dB 1111 1111 -0.5 dB ... ... 1000 1000 -60.0 dB 1000 0111 Mute ... ... 1000 0000 Mute Step Size: 0.5 dB 67 CS42L56 6.15 Analog Input Advisory Volume (Address 11h) 7 6 5 4 3 2 1 0 AINADV7 AINADV6 AINADV5 AINADV4 AINADV3 AINADV2 AINADV1 AINADV0 6.15.1 Analog Input Advisory Volume Defines the maximum analog input volume level used by the class H controller to determine the appropriate supply for the HP and Line amplifiers. 6.16 AINADV[7:0] Defined Input Volume 0001 1000 Reserved *** *** 0000 0001 Reserved 0000 0000 0 dB 1111 1111 -0.5 dB 1111 1110 -1.0 dB *** *** 0011 0100 -102 dB *** *** 0001 1001 -102 dB Step Size: 0.5 dB Digital Input Advisory Volume (Address 12h) 7 6 5 4 3 2 1 0 DINADV7 DINADV6 DINADV5 DINADV4 DINADV3 DINADV2 DINADV1 DINADV0 6.16.1 Digital Input Advisory Volume Defines the maximum digital input volume level used by the class H controller to determine the appropriate supply for the HP and Line amplifiers. DINADV[7:0] Defined Input Volume 0001 1000 Reserved *** *** 0000 0001 Reserved 0000 0000 0 dB 1111 1111 -0.5 dB 1111 1110 -1.0 dB *** *** 0011 0100 -102 dB *** *** 0001 1001 -102 dB Step Size: 0.5 dB Note: Between the headphone and line, the final output voltage from the charge pump is dictated by the highest required advisory volume. When any respective amplifier is powered down, the charge pump's voltage automatically adjusts to the appropriate level. 68 DS851F2 CS42L56 6.17 Master Volume Control: MSTA (Address 13h) & MSTB (Address 14h) 7 6 5 4 3 2 1 0 MSTxVOL7 MSTxVOL6 MSTxVOL5 MSTxVOL4 MSTxVOL3 MSTxVOL2 MSTxVOL1 MSTxVOL0 6.17.1 Master Volume Control Sets the volume of the signal out the DSP. MSTxVOL[7:0] 6.18 Master Volume 0001 1000 +12.0 dB *** *** 0000 0000 0 dB 1111 1111 -0.5 dB 1111 1110 -1.0 dB *** *** 0011 0100 -102 dB 0011 0011 Mute *** *** 0001 1001 Mute Step Size: 0.5 dB Beep Frequency & On Time (Address 15h) 7 6 5 4 3 2 1 0 FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0 6.18.1 Beep Frequency Sets the frequency of the beep signal. FREQ[3:0] Frequency (Fs = 12, 24, 48 or 96 kHz) Pitch 0000 260.87 Hz C4 0001 521.74 Hz C5 0010 585.37 Hz D5 0011 666.67 Hz E5 0100 705.88 Hz F5 0101 774.19 Hz G5 0110 888.89 Hz A5 0111 1000.00 Hz B5 1000 1043.48 Hz C6 1001 1200.00 Hz D6 1010 1333.33 Hz E6 1011 1411.76 Hz F6 1100 1600.00 Hz G6 1101 1714.29 Hz A6 1110 2000.00 Hz B6 1111 2181.82 Hz C7 Application: "Beep Generator" on page 45 Notes: 1. This setting must not change when BEEP is enabled. 2. Beep frequency will scale directly with sample rate, Fs. DS851F2 69 CS42L56 6.18.2 Beep On Time Sets the on duration of the beep signal. ONTIME[3:0] On Time (Fs = 12, 24 or 48 kHz) 0000 ~86 ms 0001 ~430 ms 0010 ~780 ms 0011 ~1.20 s 0100 ~1.50 s 0101 ~1.80 s 0110 ~2.20 s 0111 ~2.50 s 1000 ~2.80 s 1001 ~3.20 s 1010 ~3.50 s 1011 ~3.80 s 1100 ~4.20 s 1101 ~4.50 s 1110 ~4.80 s 1111 ~5.20 s Application: "Beep Generator" on page 45 Notes: 1. This setting must not change when BEEP is enabled. 2. Beep on time will scale inversely with sample rate, Fs. 6.19 Beep Volume & Off Time (Address 16h) 7 6 5 4 3 2 1 0 OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0 6.19.1 Beep Off Time Sets the off duration of the beep signal. OFFTIME[2:0] Off Time (Fs = 12, 24 or 48 kHz) 000 ~1.23 s 001 ~2.58 s 010 ~3.90 s 011 ~5.20 s 100 ~6.60 s 101 ~8.05 s 110 ~9.35 s 111 ~10.80 s Application: "Beep Generator" on page 45 Notes: 1. This setting must not change when BEEP and/or REPEAT is enabled. 2. Beep off time will scale inversely with sample rate, Fs. 70 DS851F2 CS42L56 6.19.2 Beep Volume Sets the volume of the beep signal. 6.20 BPVOL[4:0] Gain 00110 +6.0 dB *** *** 00000 0 dB 11111 -2 dB 11110 -4 dB *** *** 00111 -50 dB Step Size: 2 dB Application: "Beep Generator" on page 45 Beep & Tone Configuration (Address 17h) 7 6 5 4 3 2 1 0 BEEP1 BEEP0 Reserved TREBCF1 TREBCF0 BASSCF1 BASSCF0 TCEN 6.20.1 Beep Configuration Configures a beep mixed with the HP and Line output. BEEP[1:0] Beep Occurrence 00 Off 01 Single 10 Multiple 11 Continuous Application: "Beep Generator" on page 45 Notes: 1. When used in analog pass through mode, the output alternates between the signal from the PGA and the beep signal. The beep signal does not mix with the analog signal from the PGA. 2. Re-engaging the beep before it has completed its initial cycle may cause the beep signal to remain ON for the maximum ONTIME duration. 6.20.2 Treble Corner Frequency Sets the corner frequency for the treble shelving filter. DS851F2 TREBCF[1:0] Treble Corner Frequency Setting 00 5 kHz 01 7 kHz 10 10 kHz 11 15 kHz 71 CS42L56 6.20.3 Bass Corner Frequency Sets the corner frequency for the bass shelving filter. BASSCF[1:0] Bass Corner Frequency Setting 00 50 Hz 01 100 Hz 10 200 Hz 11 250 Hz 6.20.4 Tone Control Enable Configures the treble and bass activation. 6.21 TCEN Bass and Treble Control 0 Disabled 1 Enabled Tone Control (Address 18h) 7 6 5 4 3 2 1 0 TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0 6.21.1 Treble Gain Sets the gain of the treble shelving filter. TREB[3:0] Gain Setting 0000 +12.0 dB *** *** 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB *** *** 1111 -10.5 dB Step Size: 1.5 dB 6.21.2 Bass Gain Sets the gain of the bass shelving filter. 72 BASS[3:0] Gain Setting 0000 +12.0 dB *** *** 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB *** *** 1111 -10.5 dB Step Size: 1.5 dB DS851F2 CS42L56 6.22 ADC & PCM Channel Mixer (Address 19h) 7 6 5 4 3 2 1 0 PCMBSWP1 PCMBSWP0 PCMASWP1 PCMASWP0 ADCBSWP1 ADCBSWP0 ADCASWP1 ADCASWP0 6.22.1 PCM Mix Channel Swap Configures a mix/swap of the PCM Mix to the headphone/line outputs. PCMxSWP[1:0] PCM Mix to HP/LINEOUTA PCM Mix to HP/LINEOUTB 00 Left Right (Left + Right)/2 (Left + Right)/2 Right Left 01 10 11 6.22.2 ADC Mix Channel Swap Configures a mix/swap of the ADC Mix to the headphone/line outputs. ADCxSWP[1:0] ADC Mix to HP/LINEOUTA Channel ADC Mix to HP/LINEOUTB Channel 00 Left Right (Left + Right)/2 (Left + Right)/2 Right Left 01 10 11 6.23 AIN Reference Configuration, ADC MUX (Address 1Ah) 7 6 5 4 3 2 1 0 AIN2B_REF AIN2A_REF AIN1B_REF AIN1A_REF ADCBMUX1 ADCBMUX0 ADCAMUX1 ADCAMUX0 6.23.1 Analog Input 2 x Reference Configuration Configures the analog input 2 x reference. AIN2x_REF Analog Input Configuration 0 AIN2x is configured as a single-ended input, referenced to the internal ADC common-mode voltage. If both AIN2 channels are configured as single-ended, AIN2REF/AIN3B can be used as an additional single-ended input, referenced to the internal ADC common-mode voltage. 1 AIN2x is configured as a pseudo-differential input, referenced to AIN2REF/AIN3B. 6.23.2 Analog Input 1 x Reference Configuration Configures the analog input 1 x reference. AIN1x_REF Analog Input Configuration 0 AIN1x is configured as a single-ended input, referenced to the internal ADC common-mode voltage. If both AIN1 channels are configured as single-ended, AIN1REF/AIN3A can be used as an additional single-ended input, referenced to the internal ADC common-mode voltage. 1 AIN1x is configured as a pseudo-differential input, referenced to AIN1REF/AIN3A. DS851F2 73 CS42L56 6.23.3 ADC x Input Select Selects the specified analog input signal into ADCx. ADCxMUX[1:0] Selected Input to ADCx 00 PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 77) to select an input channel. 01 AIN1x; PGA is bypassed. 10 AIN2x; PGA is bypassed. 11 AIN3x; PGA is bypassed. Note: Pseudo-differential inputs are not available when the PGA is bypassed. Use the AINx_REF bits (Analog Input 1 x Reference Configuration and "Analog Input 1 x Reference Configuration" on page 74) to properly configure the input channel. 6.24 HPF Control (Address 1Bh) 7 6 5 4 3 2 1 0 HPFB HPFRZB HPFA HPFRZA HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0 6.24.1 ADCx High-Pass Filter Configures the internal high-pass filter after ADCx. HPFx High Pass Filter Status 0 Disabled 1 Enabled 6.24.2 ADCx High-Pass Filter Freeze Configures the high pass filter's digital DC subtraction and/or calibration after ADCx. HPFRZx High Pass Filter Digital Subtraction 0 Continuous DC Subtraction 1 Frozen DC Subtraction 6.24.3 HPF x Corner Frequency Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF). HPFx_CF[1:0] 74 HPF Corner Frequency Setting (Fs=48 kHz) 00 1.8 Hz 01 119 Hz 10 236 Hz 11 464 Hz DS851F2 CS42L56 6.25 Misc. ADC Control (Address 1Ch) 7 6 5 4 3 2 1 0 ADCB=A PGAB=A DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADCBMUTE ADCAMUTE 6.25.1 ADC Channel B=A Configures independent or ganged volume and mute control of the ADC. When enabled, the channel B settings are ignored and the channel A settings control channel A and channel B. ADCB=A Single Volume Control 0 Disabled; Independent channel control. Affected Volume Controls 1 Enabled; Ganged channel control. Channel A volume control controls channel B volume. ADCxMUTE ("ADC Mute" on page 76) ADCxVOL[6:0] ("ADCx Volume" on page 78) 6.25.2 PGA Channel B=A Configures independent or ganged volume control of the PGA. When enabled, the channel B settings are ignored and the channel A settings control channel A and channel B. Affected register bits include PGAxVOL[5:0]. PGAB=A Single Volume Control Affected Volume Controls 0 Disabled; Independent channel control. 1 Enabled; Ganged channel control. Channel A volume control controls channel B volume. PGAxVOL[5:0] ("PGAx Volume" on page 78) 6.25.3 Digital Sum Configures a mix/swap of ADCA and ADCB. DIGSUM[1:0] Serial Output Signal Left Channel Right Channel 00 ADCA ADCB 01 (ADCA + ADCB)/2 (ADCA + ADCB)/2 10 (ADCA - ADCB)/2 (ADCA - ADCB)/2 11 ADCB ADCA 6.25.4 Invert ADC Signal Polarity Configures the polarity of the ADC signal. INV_ADCx ADC Signal Polarity 0 Not Inverted 1 Inverted 6.25.5 ADC Mute Configures a digital mute on ADC channel x. ADCxMUTE DS851F2 ADC Mute 0 Not muted. 1 Muted 75 CS42L56 6.26 Gain & Bias Control (Address 1Dh) 7 6 5 4 3 2 1 0 PREAMPB1 PREAMPB0 PREAMPA1 PREAMPA0 BOOSTB BOOSTA BIAS_LVL1 BIAS_LVL0 6.26.1 PGA x Preamplifier Gain Configures the gain of the PGA x preamp. PREAMPx[1:0] PGA x Preamp Gain 00 0 dB 01 +10 dB 10 +20 dB 11 Reserved 6.26.2 Boostx Configures a +20 dB digital boost on ADC channel x. BOOSTx +20 dB Boost 0 No boost applied 1 +20 dB digital boost applied 6.26.3 Microphone Bias Output Level Configures the voltage level of the microphone bias output. 6.27 BIAS_LVL[1:0] MIC Bias Output Level 00 0.9xVA 01 0.8xVA 10 0.7xVA 11 0.6xVA PGA x MUX, Volume: PGA A (Address 1Eh) & PGA B (Address 1Fh) 7 6 5 4 3 2 1 0 PGAxMUX1 PGAxMUX0 PGAxVOL5 PGAxVOL4 PGAxVOL3 PGAxVOL2 PGAxVOL1 PGAxVOL0 6.27.1 PGA x Input Select Selects the specified analog input signal into PGA channel x. PGAxMUX[1:0] Selected Input to PGAx 00 AIN1x. 01 AIN2x. 10 AIN3x. 11 Reserved Note: For pseudo-differential inputs, the CODEC automatically chooses the respective pseudo-ground (AIN1REF or AIN2REF) for each input selection. Use the AINx_REF bits (Analog Input 1 x Reference Configuration and "Analog Input 1 x Reference Configuration" on page 74) to properly configure the input channel. 76 DS851F2 CS42L56 6.27.2 PGAx Volume Sets the volume/gain of the Programmable Gain Amplifier (PGA). PGAxVOL[5:0] Volume 01 1111 +12 dB ... ... 01 1000 +12 dB ... ... 00 0001 +0.5 dB 00 0000 0 dB 11 1111 -0.5 dB ... ... 11 0100 -6.0 dB ... ... 10 0000 -6.0 dB Step Size: 0.5 dB Notes: 1. Refer to Figure 37 and Figure 38 on page 89 for differential and integral nonlinearity (DNL and INL). 6.28 ADCx Attenuator Control: ADCAATT (Address 20h) & ADCBATT (Address 21h) 7 6 5 4 3 2 1 0 ADCxATT7 ADCxATT6 ADCxATT5 ADCxATT4 ADCxATT3 ADCxATT2 ADCxATT1 ADCxATT0 6.28.1 ADCx Volume Sets the volume of the ADC signal. DS851F2 ADCxATT[7:0] Volume 0111 1111 0 dB ... ... 0000 0000 0 dB 1111 1111 -1.0 dB 1111 1110 -2.0 dB ... ... 1010 0000 -96.0 dB 1001 1111 Mute ... ... 1000 0000 Mute Step Size: 1.0 dB 77 CS42L56 6.29 ALC Enable & Attack Rate (Address 22h) 7 6 5 4 3 2 1 0 ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0 6.29.1 ALCx Configures the automatic level controller (ALC). ALC ALC Status 0 Disabled 1 Enabled Application: "Automatic Level Control (ALC)" on page 35 Notes: 1. The ALC should only be configured while the power down bit ("Power Down" on page 59) is enabled. 2. The ALC is not available in passthrough mode. 6.29.2 ALC Attack Rate Sets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0] threshold ("ALC Maximum Threshold" on page 80). ALCARATE[5:0] Attack Time 00 0000 Fastest Attack *** *** 11 1111 Slowest Attack Application: "Automatic Level Control (ALC)" on page 35 Note: The ALC attack rate is user-selectable but is also a function of the sampling frequency, Fs, the ANLGZCx ("Analog Zero Cross" on page 64) and the DIGSFT ("Digital Soft Ramp" on page 64) setting unless the respective disable bit ("ALCx Soft Ramp Disable" on page 82 or "ALCx Zero Cross Disable" on page 82) is enabled. 6.30 ALC Release Rate (Address 23h) 7 6 5 4 3 2 1 0 ALC_ALL Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0 6.30.1 ALC Limit All Channels Sets how channels are attenuated when the ALC is enabled. ALC_ALL ALC action: 0 Apply the necessary attenuation on a specific channel only when the signal amplitudes on that specific channel rises above ALCMAX[2:0]. Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below ALCMIN[2:0]. 1 Apply the necessary attenuation on BOTH channels when the signal amplitudes on any ONE channel rises above ALCMAX[2:0]. Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below ALCMIN[2:0]. Application: "Automatic Level Control (ALC)" on page 35 Note: 78 This function should only be used when the ALC for both channels is enabled. DS851F2 CS42L56 6.30.2 ALC Release Rate Sets the rate at which the ALC releases the analog and/or digital attenuation from levels below the MIN[2:0] threshold ("Limiter Cushion Threshold" on page 85) and returns the signal level to the PGAxVOL[5:0] ("PGAx Volume" on page 78) and ADCxVOL[7:0] ("ADCx Volume" on page 78) setting. ALCRRATE[5:0] Release Time 00 0000 Fastest Release *** *** 11 1111 Slowest Release Application: "Automatic Level Control (ALC)" on page 35 Notes: 1. The ALC release rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 64) and ANLGZCx ("Analog Zero Cross" on page 64) setting. 2. It is recommended that the Release Rate setting be slower than the Attack Rate. 6.31 ALC Threshold (Address 24h) 7 6 5 4 3 2 1 0 ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALCMIN0 Reserved Reserved 6.31.1 ALC Maximum Threshold Sets the maximum level, below full scale, at which to limit and attenuate the input signal at the attack rate (ALCARATE - "ALC Attack Rate" on page 79). MAX[2:0] DS851F2 Threshold Setting 000 0 dB 001 -3 dB 010 -6 dB 011 -9 dB 100 -12 dB 101 -18 dB 110 -24 dB 111 -30 dB Application: "Automatic Level Control (ALC)" on page 35 79 CS42L56 6.31.2 ALC Minimum Threshold Sets the minimum level at which to disengage the ALC's attenuation or amplify the input signal at the release rate (ALCRRATE - "ALC Release Rate" on page 80) until levels lie between the ALCMAX and ALCMIN thresholds. ALCMIN[2:0] 0 dB 001 -3 dB 010 -6 dB 011 -9 dB 100 -12 dB 101 -18 dB 110 -24 dB 111 -30 dB Application: "Automatic Level Control (ALC)" on page 35 Note: 6.32 Threshold Setting 000 This setting is usually set slightly below the ALCMAX threshold. Noise Gate Control (Address 25h) 7 6 5 4 3 2 1 0 NGALL NG NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0 6.32.1 Noise Gate All Channels Sets which channels are attenuated when clipping on any single channel occurs. NGALL Noise Gate triggered by: 0 Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for ONLY that channel. 1 Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to take effect. 6.32.2 Noise Gate Enable Configures the noise gate. 80 NG Noise Gate Status 0 Disabled 1 Enabled DS851F2 CS42L56 6.32.3 Noise Gate Threshold and Boost THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings. THRESH[2:0] Minimum Setting (NG_BOOST = 0b) 000 -64 dB Minimum Setting (NG_BOOST = 1b) -34 dB 001 -67 dB -36 dB 010 -70 dB -40 dB 011 -73 dB -43 dB 100 -76 dB -46 dB 101 -82 dB -52 dB 110 Reserved -58 dB 111 Reserved -64 dB 6.32.4 Noise Gate Delay Timing Sets the delay time before the noise gate attacks. NGDELAY[1:0] Delay Setting 00 50 ms 01 100 ms 10 150 ms 11 200 ms Note: The Noise Gate attack rate is a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 64) setting. 6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 26h) 7 6 5 4 3 2 1 0 ALCASRDIS ALCAZCDIS ALCBSRDIS ALCBZCDIS LIMSRDIS Reserved Reserved Reserved 6.33.1 ALCx Soft Ramp Disable Configures an override of the analog soft ramp setting. ALCxSRDIS ALC Soft Ramp Disable 0 OFF; ALC Attack Rate is dictated by the DIGSFT ("Digital Soft Ramp" on page 64) setting 1 ON; ALC volume changes take effect in one step, regardless of the DIGSFT setting. 6.33.2 ALCx Zero Cross Disable Configures an override of the analog zero cross setting. ALCxZCDIS ALC Zero Cross Disable 0 OFF; ALC Attack Rate is dictated by the ANLGZC ("Analog Zero Cross" on page 64) setting 1 ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting. 6.33.3 Limiter Soft Ramp Disable Configures an override of the digital soft ramp setting. LIMSRDIS DS851F2 Limiter Soft Ramp Disable 0 OFF; Limiter Attack Rate is dictated by the DIGSFT ("Digital Soft Ramp" on page 64) setting 1 ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting. 81 CS42L56 6.34 Automute, Line & HP MUX (Address 27h) 7 6 5 4 3 2 1 0 AMUTE Reserved Reserved Reserved LINEBMUX LINEAMUX HPBMUX HPAMUX 6.34.1 Auto Mute Configures the state of the auto mute feature. When enabled, the analog outputs will mute after 4096 consecutive zeros or ones from SDIN. AMUTE Auto Mute Configuration 0 Auto Mute Disabled 1 Auto Mute Enabled. The analog outputs will mute after 4096 consecutive words of all zeros or ones from SDIN. 6.34.2 Line Input Select Selects the specified analog input signal into line amplifier x. LINExMUX Selected Input to Line Amplifier Ch. x 0 DACx 1 PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 77) to select an input channel. Note: The PGA path must not be selected while the Line Amplifier is powered down. 6.34.3 Headphone Input Select Selects the specified analog input signal into headphone amplifier x. HPxMUX DACx 1 PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 77) to select an input channel. Note: 6.35 Selected Input to HP Amplifier Ch. x 0 The PGA path must not be selected while the Headphone Amplifier is powered down. Headphone Volume Control: HPA (Address 28h) & HPB (Address 29h) 7 6 5 4 3 2 1 0 HPxMUTE HPxVOL6 HPxVOL5 HPxVOL4 HPxVOL3 HPxVOL2 HPxVOL1 HPxVOL0 6.35.1 Headphone Channel x Mute Configures an analog mute on the headphone amplifier. HPxMUTE 82 HP Amp Mute 0 Disabled 1 Enabled DS851F2 CS42L56 6.35.2 Headphone Volume Control Sets the volume of the signal out of the headphone amplifier. HPxVOL[6:0] Heaphone Volume 0111111 +12 dB ... ... 0001100 +12 dB ... ... 0000001 +1.0 dB 0000000 0 dB 1111111 -1.0 dB ... ... 1000100 -60.0 dB (Nominal Level (Note 1)) 1000011 Mute ... ... 1000000 Mute (Note 2) Step Size: 1.0 dB Notes: 1. The step size may deviate from 1.0 dB. Refer to Figure 39 and Figure 40 on page 89. 2. See section "Analog Output Attenuation Characteristics" on page 26 for actual Mute Attenuation. 6.36 Line Volume Control: LINEA (Address 2Ah) & LINEB (Address 2Bh) 7 6 5 4 3 2 1 0 LINExMUTE LINExVOL6 LINExVOL5 LINExVOL4 LINExVOL3 LINExVOL2 LINExVOL1 LINExVOL0 6.36.1 Line Channel x Mute Configures an analog mute on the line amplifier. LINExMUTE HP Amp Mute 0 Disabled 1 Enabled 6.36.2 Line Volume Control Sets the volume of the signal out of the line amplifier. DS851F2 LINExVOL[6:0] Line Volume 0111111 +12 dB ... ... 0001100 +12 dB ... ... 0000001 +1.0 dB 0000000 0 dB 1111111 -1.0 dB ... ... 1000100 -60.0 dB (Nominal Level (Note 1)) 1000011 Mute (Note 2) ... ... Step Size: 1.0 dB 83 CS42L56 Notes: 1. The step size may deviate from 1.0 dB. Refer to Figure 39 on page 89 and Figure 40 on page 89. 2. See section "Analog Output Attenuation Characteristics" on page 26 for actual Mute Attenuation. 6.37 Limiter Min/Max Thresholds (Address 2Ch) 7 6 5 4 3 2 1 0 LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 Reserved Reserved 6.37.1 Limiter Maximum Threshold Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate (LIMARATE - "Limiter Release Rate" on page 86). LMAX[2:0] Threshold Setting 000 0 dB 001 -3 dB 010 -6 dB 011 -9 dB 100 -12 dB 101 -18 dB 110 -24 dB 111 -30 dB Application: "Limiter" on page 46 Note: Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. 6.37.2 Limiter Cushion Threshold Sets the minimum level at which to disengage the Limiter's attenuation at the release rate (LIMRRATE "Limiter Release Rate" on page 86) until levels lie between the LMAX and CUSH thresholds. CUSH[2:0] Threshold Setting 000 0 dB 001 -3 dB 010 -6 dB 011 -9 dB 100 -12 dB 101 -18 dB 110 -24 dB 111 -30 dB Application: "Limiter" on page 46 Note: 84 This setting is usually set slightly below the LMAX threshold. DS851F2 CS42L56 6.38 Limiter Control, Release Rate (Address 2Dh) 7 6 5 4 3 2 1 0 LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0 6.38.1 Peak Detect and Limiter Configures the peak detect and limiter circuitry. LIMIT Limiter Status 0 Disabled 1 Enabled Application: "Limiter" on page 46 Note: The Limiter should only be configured while the power down bit ("Power Down" on page 59) is enabled. 6.38.2 Peak Signal Limit All Channels Sets how channels are attenuated when the limiter is enabled. LIMIT_ALL Limiter action: 0 Apply the necessary attenuation on a specific channel only when the signal amplitudes on that specific channel rises above LMAX. Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below CUSH. 1 Apply the necessary attenuation on BOTH channels when the signal amplitudes on any ONE channel rises above LMAX. Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH. Application: "Limiter" on page 46 6.38.3 Limiter Release Rate Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] threshold ("Limiter Cushion Threshold" on page 85) and returns the analog output level to the MSTxVOL[7:0] ("Master Volume Control" on page 70) setting. LIMRRATE[5:0] Release Time 00 0000 Fastest Release *** *** 11 1111 Slowest Release Application: "Limiter" on page 46 Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 64) setting unless the disable bit ("Limiter Soft Ramp Disable" on page 82) is enabled. DS851F2 85 CS42L56 6.39 Limiter Attack Rate (Address 2Eh) 7 6 5 4 3 2 1 0 Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0 6.39.1 Limiter Attack Rate Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold ("Limiter Maximum Threshold" on page 85). LIMARATE[5:0] Attack Time 00 0000 Fastest Attack *** *** 11 1111 Slowest Attack Application: "Limiter" on page 46 Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 64) setting unless the disable bit ("Limiter Soft Ramp Disable" on page 82) is enabled. 86 DS851F2 CS42L56 7. PCB LAYOUT CONSIDERATIONS 7.1 Power Supply As with any high-resolution converter, the CS42L56 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 11 shows the recommended power arrangements, with VA and VCP connected to clean supplies. VLDO, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VLDO may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VLDO. 7.2 Grounding Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L56 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS42L56 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+, VQ, +VHPFILT and -VHPFILT capacitors must be positioned to minimize the electrical path from each respective pin to AGND. The CDB42L56 evaluation board demonstrates the optimum layout and power supply arrangements. 7.3 QFN Thermal Pad The CS42L56 comes in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CDB42L56 evaluation board demonstrates the optimum thermal pad and via configuration. DS851F2 87 CS42L56 8. ANALOG VOLUME NON-LINEARITY (DNL & INL) 12 0.52 Actual Output Volume, dB 10 Actual Step Size, dB 0.5 0.48 0.46 0.44 0.42 -6 -5 -4 -3 -2 0.4 -1 0 1 2 3 4 5 PGA Volume Setting 6 7 8 9 4 2 0 -2 -4 -6 -8 0 1 2 3 4 5 6 PGA Volume Setting 0.6 0.4 0.2 -40 -30 -20 -10 10 11 12 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 0 +10 HP/Line Volume Setting Figure 39. HP/Line Step Size vs. Volume Setting 88 9 0 0 -50 8 10 Actual Output Volume, dB 0.8 -60 7 Figure 38. PGA Output Volume vs. Volume Setting 1 Actual Step Size, dB 6 -6 -5 -4 -3 -2 -1 10 11 Figure 37. PGA Step Size vs. Volume Setting 8 +20 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0 10 20 H P / L in e V o l u m e S e t t i n g Figure 40. HP/Line Output Volume vs. Volume Setting DS851F2 CS42L56 9. ADC & DAC DIGITAL FILTERS 0 0.25 -10 0.2 -20 0.1 -30 0.05 -40 Magnitude (dB) Magnitude (dB) 0.15 0 -0.05 -50 -60 -0.1 -70 -0.15 -80 -0.2 -90 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) 0.35 0.4 0.45 -100 0.5 Figure 41. ADC Frequency Response 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) 0.7 0.8 0.9 1 Figure 42. ADC Stopband Rejection 0 0 -1 -10 -2 -20 -3 -30 -4 Magnitude (dB) Magnitude (dB) 0 -40 -50 -5 -6 -60 -7 -70 -8 -80 -9 -90 -100 0.4 0.45 0.5 0.55 0.6 Frequency (normalized to Fs) -10 0.45 0.65 Figure 43. ADC Transition Band 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 0.55 Figure 44. ADC Transition Band Detail 0 0.03 -10 0.02 -20 -30 0 Magnitude (dB) Magnitude (dB) 0.01 -0.01 -40 -50 -60 -0.02 -70 -0.03 -80 -0.04 -90 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 frequency (Normalized to Fs) 0.35 0.4 0.45 0 0 0 -10 -10 -20 -20 -30 -40 0.4 0.5 0.6 frequency (Normalized to Fs) 0.7 0.8 0.9 0.53 0.54 1 -40 -50 -60 -60 0.42 0.44 0.46 0.48 0.5 0.52 0.54 frequency (Normalized to Fs) 0.56 0.58 Figure 47. DAC Transition Band DS851F2 0.3 -30 -50 0.4 0.2 Figure 46. DAC Stopband Magnitude (dB) Magnitude (dB) Figure 45. DAC Frequency Response 0.1 0.6 0.45 0.46 0.47 0.48 0.49 0.5 0.51 frequency (Normalized to Fs) 0.52 Figure 48. DAC Transition Band (Detail) 89 CS42L56 10.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dB signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 dBFS and -20 dBFS for the analog input and 0 dB and -20 dB for the analog output as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. HP to ADC Isolation A measure of crosstalk between the headphone amplifier and the ADC inputs. Measured for each channel at the ADC's output with no signal to the input and a full-scale signal applied to the headphone amplifier with a 16 or 10 k load. Units in decibels. Output Offset Voltage Describes the DC offset voltage present at the amplifier's output. When measuring the offset out the line amplifier, the line amplifier is ON while the headphone amplifier is OFF; when measuring the offset out the headphone amplifier, the headphone amplifier is ON while the line amplifier is OFF. AC Load Resistance and Capacitance RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. 90 DS851F2 CS42L56 11.PACKAGE DIMENSIONS (Unless otherwise specified, linear tolerance is 0.05 mm, and angular tolerance is 2 deg.) 40L QFN (5 X 5 mm BODY) PACKAGE DRAWING D b 2.00 REF e PIN #1 CORNER 2.00 REF PIN #1 IDENTIFIER 0.500.10 LASER MARKING E2 E A1 L D2 A Dim MIN A A1 b e D E D2 E2 L 0.01575 0.00000 0.00591 0.13583 0.13583 0.01181 INCHES NOM 0.01772 0.00787 0.01575 BSC 0.19685 BSC 0.19685 BSC 0.13780 0.13780 0.01378 MAX MIN 0.01969 0.00197 0.00984 0.40 0.00 0.15 0.13976 0.13976 0.01575 3.45 3.45 0.30 MILLIMETERS NOM 0.45 0.20 0.40 BSC 5.00 BSC 5.00 BSC 3.50 3.50 0.35 NOTE MAX 0.50 0.05 0.25 3.55 3.55 0.40 1,2 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Controlling dimensions are in millimeters. 2. Dimensioning and tolerances per ASME Y 14.5M-1994. 3. Dimension lead width applies to the plated terminal and is measured 0.25 mm and 0.30 mm from the terminal tip. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance DS851F2 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA JA - 68 28 - C/Watt C/Watt 91 CS42L56 12.ORDERING INFORMATION Product CS42L56 Description Ultralow Power, Stereo Codec with Class H Headphone Amp Package Pb-Free 40L-QFN YES - - Grade Temp Range Container Order # Rail CDB42L56 CS42L56 Evaluation Board Commercial -40C to +85C - - CS42L56-CNZ Tape & Reel CS42L56-CNZR - CDB42L56 13.REFERENCES 1. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com 14.REVISION HISTORY Release F1 F2 Changes Final Release. Updated "ADC Digital Filter Characteristics" section on page 18. Updated dither specified in Note 15 on page 20. Updated "Combined DAC Interpolation & On-Chip Analog FIlter Response" section on page 22. Updated Figure 14. "Stereo Pseudo-Differential Input" on page 33. Updated the Class H section, "Adapt to Volume Mode (setting 00)" on page 40. Updated Section 4.11 "Recommended DAC to HP or Line Power Sequence" on page 50. Updated Section 4.12 "Recommended PGA to HP or Line Power Sequence (Analog Passthrough)" on page 52. Updated the first paragraph in "Register Quick Reference" on page 56 and "Register Description" on page 58 to allow data sheet-specified control-writes to reserved registers. Removed IC address heading row from "Register Quick Reference" on page 56. Added Note 1 in "Freeze Registers" on page 64. Corrected BEEP volume settings to reflect level relative to DAC's full scale in "Beep Volume" on page 72 Updated "PGA x Preamplifier Gain" section on page 77. Corrected the E2 scale in the package drawing in "Package Dimensions" on page 92. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola. 92 DS851F2 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic: CS42L56-CNZR