800 mA Ultralow Noise, High PSRR, RF Linear Regulator ADM7151 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADM7151-04 VIN = 6.2V CIN 10F VIN VOUT EN REF VOUT = 5.0V COUT 10F ON VBYP OFF CBYP 1F CREF 1F BYP R1 VOUT = 1.5V x (R1 + R2)/R2 REF_SENSE VREG CREG 10F VREG R2 1k < R2 < 200k GND 11480-001 Input voltage range: 4.5 V to 16 V Maximum output current: 800 mA Adjustable output from 1.5 V to 5.1 V Low noise 1.0 V rms total integrated noise from 100 Hz to 100 kHz 1.6 V rms total integrated noise from 10 Hz to 100 kHz Noise spectral density: 1.7 nVHz from 10 kHz to 1 MHz Power supply rejection ratio (PSRR) at 400 mA load >90 dB from 1 kHz to 100 kHz, VOUT = 5 V >60 dB at 1 MHz, VOUT = 5 V Dropout voltage: 0.6 V at VOUT = 5 V, 800 mA load Initial voltage accuracy: 1% Voltage accuracy over line, load and temperature: 2% Quiescent current (IGND): 4.3 mA at no load Low shutdown current: 0.1 A Stable with a 10 F ceramic output capacitor 8-lead LFCSP package and 8-lead SOIC package Figure 1. ADM7151-04 with VOUT = 5 V APPLICATIONS Regulated power noise sensitive applications RF mixers, phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), and PLLs with integrated VCOs Clock distribution circuits Ultrasound and other imaging applications High speed RF transceivers High speed, 16-bit or greater ADCs Communications and infrastructure Cable digital-to-analog converter (DAC) drivers The ADM7151 is available in two models that optimize power dissipation and PSRR performance as a function of input and output voltage. See Table 6 and Table 7 for selection guides. The ADM7151 regulator output noise is 1.0 V rms from 100 Hz to 100 kHz, and the noise spectral density is 1.7 nV/Hz from 10 kHz to 1 MHz. The ADM7151 is available in 8-lead, 3 mm x 3 mm LFCSP and 8-lead SOIC packages, making it not only a very compact solution, Rev. A 100k CBYP CBYP CBYP CBYP 10k = 1F = 10F = 100F = 1mF 1k 100 10 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 11480-002 The ADM7151 is a low dropout (LDO) linear regulator that operates from 4.5 V to 16 V and provides up to 800 mA of output current. Using an advanced proprietary architecture, it provides high power supply rejection (>90 dB from 1 kHz to 1 MHz), ultralow noise (1.7 nVHz from 10 kHz to 1 MHz), and excellent line and load transient response with a 10 F ceramic output capacitor. The output voltage can be set to any voltage between 1.5 V and 5.1 V with two resistors. but also providing excellent thermal performance for applications requiring up to 800 mA of output current in a small, low profile footprint. NOISE SPECTRAL DENSITY (nV/Hz) GENERAL DESCRIPTION Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various CBYP Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADM7151 Data Sheet TABLE OF CONTENTS Features........................................................................................... 1 Theory of Operation.................................................................... 15 Applications ................................................................................... 1 Applications Information............................................................ 16 Typical Application Circuit........................................................... 1 Model Selection ....................................................................... 16 General Description ...................................................................... 1 Capacitor Selection.................................................................. 16 Revision History ............................................................................ 2 Enable (EN) and Undervoltage Lockout (UVLO) ................ 18 Specifications ................................................................................. 3 Start-Up Time .......................................................................... 19 Input and Output Capacitor, Recommended Specifications.. 4 REF, BYP, and VREG Pins....................................................... 19 Absolute Maximum Ratings ......................................................... 5 Current-Limit and Thermal Overload Protection ................ 19 Thermal Data............................................................................. 5 Thermal Considerations ......................................................... 19 Thermal Resistance ................................................................... 5 Printed Circuit Board Layout Considerations....................... 22 ESD Caution............................................................................... 5 Outline Dimensions .................................................................... 23 Pin Configurations and Function Descriptions .......................... 6 Ordering Guide........................................................................ 24 Typical Performance Characteristics............................................ 7 REVISION HISTORY 4/15--Rev. 0 to Rev. A Change to Figure 4..........................................................................6 Change to Figure 39......................................................................12 9/13--Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADM7151 SPECIFICATIONS VIN = 4.5 V, VOUT = 1.5 V, VREF = VREF_SENSE (unity gain), VEN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 F, CREF = CBYP = 1 F. TA = 25C for typical specifications. TJ = -40C to +125C for minimum/maximum specifications, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND SHUTDOWN CURRENT OUTPUT NOISE IIN-SD OUTNOISE NOISE SPECTRAL DENSITY POWER SUPPLY REJECTION RATIO ADM7151-04 NSD PSRR ADM7151-02 VOUT VOLTAGE ACCURACY Voltage Accuracy VOUT REGULATION Line Regulation Load Regulation1 CURRENT-LIMIT THRESHOLD VREF Current Limit Threshold VOUT Current Limit Threshold2 DROPOUT VOLTAGE3 PULL-DOWN RESISTANCE VOUT Pull-Down Resistance VREG Pull-Down Resistance VREF Pull-Down Resistance VBYP Pull-Down Resistance START-UP TIME4 VOUT Start-Up Time VREG Start-Up Time VREF Start-Up Time THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis UNDERVOLTAGE THRESHOLDS Input Voltage Rising Input Voltage Falling Hysteresis VOUT VOUT/VIN VOUT/IOUT ILIMIT Test Conditions/Comments Min 4.5 Typ IOUT = 0 A IOUT = 800 mA VEN = GND 10 Hz to 100 kHz, independent of output voltage 100 Hz to 100 kHz, independent of output voltage 10 kHz to 1 MHz, independent of output voltage 4.3 8.6 0.1 1.6 1.0 1.7 1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 800 mA 1 MHz, VIN = 6.2 V, VOUT = 5 V at 800 mA 1 kHz to 100 kHz, VIN = 6.2 V, VOUT = 5 V at 400 mA 1 MHz, VIN = 6.2 V, VOUT = 5 V at 400 mA 1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 800 mA 1 MHz, VIN = 5.2 V, VOUT = 4 V at 800 mA 1 kHz to 100 kHz, VIN = 5.2 V, VOUT = 4 V at 400 mA 1 MHz, VIN = 5.2 V, VOUT = 4 V at 400 mA VOUT = VREF IOUT = 10 mA 1 mA < IOUT < 800 mA, over line, load and temperature 84 53 94 67 91 50 94 58 VIN = 4.5 V to 16 V IOUT = 1 mA to 800 mA -1 -2 VDROPOUT IOUT = 400 mA, VOUT = 5 V IOUT = 800 mA, VOUT = 5 V VOUT-PULL VREG-PULL VREF-PULL VBYP-PULL VEN = 0 V, VOUT = 1 V VEN = 0 V, VREG = 1 V VEN = 0 V, VREF = 1 V VEN = 0 V, VBYP = 1 V VOUT = 5 V tSTART-UP tREG-START-UP tREF-START-UP TSSD TSSD-HYS TJ rising UVLORISE UVLOFALL UVLOHYS TJ = -40C to +125C TJ = -40C to +125C dB dB dB dB dB dB dB dB % % 0.5 +0.01 1.0 %/V %/A 20 1.3 0.30 0.60 1.6 0.60 1.20 mA A V V 600 34 800 500 k 2.8 1.0 1.8 ms ms ms 155 15 C C 4.49 3.85 240 Rev. A | Page 3 of 24 Unit V mA mA A V rms V rms nV/Hz +1 +2 -0.01 1.0 Max 16 7.0 12 3 V V mV ADM7151 Parameter VREG 5 UNDERVOLTAGE THRESHOLDS VREG Rise VREG Fall Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Logic Hysteresis EN Input Leakage Current Data Sheet Symbol Test Conditions/Comments Min VREGUVLORISE VREGUVLOFALL VREGUVLOHYS TJ = -40C to +125C TJ = -40C to +125C 2.55 Typ Max Unit 3.1 V V mV 210 4.5 V VIN 16 V ENHIGH ENLOW ENHYS IEN-LKG 3.2 0.8 VIN = 5 V VEN = VIN or GND 225 0.1 1.0 V V mV A Based on an end-point calculation using 1 mA and 800 mA loads. See Figure 6 and Figure 13 for typical load regulation performance for loads less than 1 mA. Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V. 3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for output voltages above 4.5 V. 4 Start-up time is defined as the time between the rising edge of V EN to V OUT, V REG, or V REF being at 90% of its nominal value. 5 The output voltage is turned off until the V REG UVLO rise threshold is crossed. The V REG output is turned off until the input voltage UVLO rising threshold is crossed. 1 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter CAPACITANCE Minimum Input1 Minimum Regulator1 Minimum Output1 Minimum Bypass Minimum Reference CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) CREG , COUT, CIN , CREF CBYP 1 Symbol CIN CREG COUT CBYP CREF RESR Test Conditions/Comments TA = -40C to +125C Min Typ Max 7.0 7.0 7.0 0.1 0.7 Unit F F F F F TA = -40C to +125C 0.001 0.001 0.2 2.0 The minimum input, regulator, and output capacitance must be greater than 7.0 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. A | Page 4 of 24 Data Sheet ADM7151 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VREG to GND VOUT to GND VOUT to BYP EN to GND BYP to GND REF to GND REF_SENSE to GND Storage Temperature Range Junction Temperature Operating Ambient Temperature Range Soldering Conditions Rating -0.3 V to +18 V -0.3 V to VIN, or +6 V (whichever is less) -0.3 V to VREG, or +6 V (whichever is less) 0.3 V -0.3 V to18 V -0.3 V to VREG, or +6 V (whichever is less) -0.3 V to VREG, or +6 V (whichever is less) -0.3 V to +6 V -65C to +150C 150C -40C to +125C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADM7151 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (JA). Junction to ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 in. x 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. JB is the junction to board thermal characterization parameter with units of C/W. JB of the package is based on modeling and the calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance (JB). Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) See JESD51-8 and JESD51-12 for more detailed information about JB. THERMAL RESISTANCE JA, JC, and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 8-Lead LFCSP 8-Lead SOIC ESD CAUTION Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD x JA) Rev. A | Page 5 of 24 JA 36.7 36.9 JC 23.5 27.1 JB 13.3 18.6 Unit C/W C/W ADM7151 Data Sheet VREG 1 8 VIN VOUT 2 7 EN GND 4 TOP VIEW (Not to Scale) VOUT 2 BYP 3 6 REF GND 4 5 REF_SENSE NOTES 1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE PROPER OPERATION. ADM7151 TOP VIEW (Not to Scale) 8 VIN 7 EN 6 REF 5 REF_SENSE NOTES 1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE. EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE. CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE PROPER OPERATION. 11480-003 BYP 3 ADM7151 VREG 1 11480-004 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 8-Lead SOIC Pin Configuration Figure 3. 8-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic VREG 2 3 4 5 6 VOUT BYP GND REF_SENSE REF 7 EN 8 EP VIN EP Description Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 F or greater capacitor. Do not connect a load to ground. Regulated Output Voltage. Bypass VOUT to GND with a 10 F or greater capacitor. Low Noise Bypass Capacitor. Connect a 1 F capacitor to GND to reduce noise. Do not connect a load to ground. Ground Connection. External Resistor Divider Used to Set the Output Voltage. VOUT = VREF x (R1 + R2)/R2, where VREF = 1.5 V. Low Noise Reference Voltage Output. Bypass REF to GND with a 1 F capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to ground. Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Regulator Input Supply. Bypass VIN to GND with a 10 F or greater capacitor. Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. Rev. A | Page 6 of 24 Data Sheet ADM7151 TYPICAL PERFORMANCE CHARACTERISTICS VIN = VOUT + 1.2 V or VIN = 4.5 V, whichever is greater, EN = VIN, IOUT = 10 mA, CIN = COUT = CREG = 10 F, CREF = CBYP = 1 F, TA = 25C, unless otherwise noted. 4.04 10 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 8 VOUT (V) 4.01 4.00 3.99 3.98 7 6 5 4 3 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 2 3.97 1 -40 -5 25 85 0 11480-005 3.96 125 JUNCTION TEMPERATURE (C) Figure 5. Output Voltage (VOUT) vs. Junction Temperature (TJ ), ADM7151-02, VOUT = 4 V -5 -40 125 85 25 11480-008 4.02 9 GROUND CURRENT (mA) 4.03 JUNCTION TEMPERATURE (C) Figure 8. Ground Current vs. Junction Temperature (TJ ), ADM7151-02, VOUT = 4 V 4.04 10 4.03 9 8 GROUND CURRENT (mA) 4.02 VOUT (V) 4.01 4.00 3.99 3.98 7 6 5 4 3 2 3.97 1 10 100 1000 ILOAD (mA) 0 11480-006 3.96 Figure 6. Output Voltage (VOUT) vs. Load Current (I LOAD ), ADM7151-02, VOUT = 4 V 1 1000 ILOAD (mA) Figure 9. Ground Current vs. Load Current (I LOAD ), ADM7151-02, VOUT = 4 V 4.04 10 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 8 4.01 4.00 3.99 3.98 7 6 5 4 3 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 2 3.97 1 5 6 7 8 9 10 11 VIN (V) 12 13 14 15 16 0 11480-007 3.96 Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN), ADM7151-02, VOUT = 4 V 5 6 7 8 9 10 11 VIN (V) 12 13 14 15 16 11480-010 4.02 9 GROUND CURRENT (mA) 4.03 VOUT (V) 100 10 11480-009 1 Figure 10. Ground Current vs. Input Voltage (VIN), ADM7151-02, VOUT = 4 V Rev. A | Page 7 of 24 ADM7151 10 SHUTDOWN CURRENT (A) 1 Data Sheet 5.00 VIN = 6.2V VIN = 6.5V VIN = 7.0V VIN = 10V VIN = 16V 4.99 4.98 4.97 4.95 4.94 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 4.93 0.001 4.92 4.91 -5 25 85 125 4.90 TEMPERATURE (C) Figure 11. Shutdown Current vs. Temperature at Various Input Voltages 6 9 4.98 8 GROUND CURRENT (mA) 4.99 VOUT (V) 4.97 4.96 4.95 4.94 4.91 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA -5 25 85 125 JUNCTION TEMPERATURE (C) Figure 12. Output Voltage (VOUT) vs. Junction Temperature (TJ ), ADM7151-04, VOUT = 5 V 4 3 -40 9 4.98 8 4.94 4.93 6 5 4 3 1 10 100 ILOAD (mA) 1000 11480-013 2 4.91 1 125 7 4.92 4.90 85 25 Figure 15. Ground Current vs. Junction Temperature (TJ ), ADM7151-04, VOUT = 5 V 4.99 4.95 -5 JUNCTION TEMPERATURE (C) 10 4.96 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 0 GROUND CURRENT (mA) VOUT (V) 5 5.00 4.97 16 6 1 11480-012 -40 14 7 2 4.90 12 Figure 14. Output Voltage (VOUT) vs. Input Voltage (VIN), ADM7151-04, VOUT = 5 V 10 4.92 10 VIN (V) 5.00 4.93 8 11480-015 -40 11480-011 0.0001 Figure 13. Output Voltage (VOUT) vs. Load Current (I LOAD ), ADM7151-04, VOUT = 5 V Rev. A | Page 8 of 24 0 1 10 100 1000 ILOAD (mA) Figure 16. Ground Current vs. Load Current (I LOAD ), ADM7151-04, VOUT = 5 V 11480-016 0.01 4.96 11480-014 VOUT (V) 0.1 Data Sheet ADM7151 12 10 9 10 6 5 4 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 3 2 1 0 6 8 8 6 4 2 10 12 14 16 0 4.6 VIN (V) Figure 17. Ground Current vs. Input Voltage (VIN), ADM7151-04, VOUT = 5 V 4.8 5.0 5.2 5.4 5.6 5.8 6.0 VIN (V) Figure 20. Ground Current vs. Input Voltage (VIN) in Dropout, ADM7151-04, VOUT = 5 V 0 700 LOAD = 800mA LOAD = 400mA LOAD = 200mA LOAD = 100mA LOAD = 10mA -10 600 -20 -30 500 -40 PSRR (dB) DROPOUT VOLTAGE (mA) IGND = 5mA IGND = 10mA IGND = 100mA IGND = 200mA IGND = 400mA IGND = 800mA 11480-020 GROUND CURRENT (A) 7 11480-017 GROUND CURRENT (mA) 8 400 300 -50 -60 -70 -80 200 -90 -100 100 10 100 1000 ILOAD (mA) -120 11480-018 1 Figure 18. Dropout Voltage vs. Load Current (I LOAD ), ADM7151-04, VOUT = 5 V 1 1k 10k 100k 1M 10M Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-02, VOUT = 4 V 0 LOAD = 800mA LOAD = 400mA LOAD = 200mA LOAD = 100mA LOAD = 10mA -10 5.0 -20 -30 4.8 PSRR (dB) -40 4.6 VDROPOUT VDROPOUT VDROPOUT VDROPOUT VDROPOUT VDROPOUT 4.2 4.8 5.0 5.2 5.4 VIN (V) 5.6 -60 -70 -80 = 5mA = 10mA = 100mA = 200mA = 400mA = 800mA 5.8 -50 -90 -100 -110 6.0 -120 Figure 19. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, ADM7151-04, VOUT = 5 V 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 10M 11480-022 4.4 11480-019 VOUT (V) 100 FREQUENCY (Hz) 5.2 4.0 4.6 10 11480-021 -110 0 Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-04, VOUT = 5 V Rev. A | Page 9 of 24 ADM7151 0 Data Sheet 600mV 700mV 800mV 900mV -10 -20 0 1.0V 1.1V 1.2V 1.3V 1.4V -30 -20 -40 100kHz 1MHz 10MHz -40 -50 PSRR (dB) PSRR (dB) 10Hz 100Hz 1kHz 10kHz -60 -70 -80 -60 -80 -90 -100 -100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) -120 0.6 11480-023 -120 Figure 23. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Headroom Voltages, ADM7151-02, VOUT = 4 V, 400 mA Load 600mV 700mV 800mV 900mV -20 1.0 1.1 1.2 1.3 1.4 0 -20 -40 -40 -60 -70 -80 -60 -80 -90 -100 -100 -110 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various Headroom Voltages, ADM7151-04, VOUT = 5 V, 400 mA Load 0 -120 0.7 11480-024 -120 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 HEADROOM (V) 1.6 Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-02, VOUT = 4 V, 800 mA Load 0 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz -20 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 11480-027 -50 PSRR (dB) PSRR (dB) 0.9 Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-02, VOUT = 4 V, 400 mA Load 1.0V 1.1V 1.2V 1.4V 1.6V 1.8V -30 0.8 HEADROOM (V) 0 -10 0.7 11480-026 -110 -20 -40 -60 -60 -80 -80 -100 -100 0.6 0.7 0.8 0.9 1.0 1.1 HEADROOM (V) 1.2 1.3 1.4 1.5 -140 0.3 11480-025 -120 0.5 -120 Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-02, VOUT = 4 V, 100 mA Load 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 0.5 0.7 0.9 1.1 HEADROOM (V) 1.3 1.5 11480-028 PSRR (dB) PSRR (dB) -40 Figure 28. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-04, VOUT = 5 V, 100 mA Load Rev. A | Page 10 of 24 Data Sheet ADM7151 0 10Hz 100Hz 1kHz -20 2.0 10kHz 100kHz 1MHz 10MHz 1.6 NOISE (Vrms) -60 -80 100Hz TO 100kHz 0.8 0.4 -100 0.8 1.0 1.2 1.4 1.6 1.8 HEADROOM (V) Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-04, VOUT = 5 V, 400 mA Load 0 10Hz 100Hz 1kHz -20 0 10 11480-029 -120 0.6 1.2 100 1000 LOAD CURRENT (mA) 11480-032 PSRR (dB) -40 Figure 32. RMS Output Noise vs. Load Current (I LOAD ), 100 Hz to 100 kHz, ADM7151-04, VOUT = 5 V 2.0 10kHz 100kHz 1MHz 10MHz 1.6 10Hz TO 100kHz NOISE (Vrms) -60 -80 0.8 0.4 -100 0.9 1.1 1.3 1.5 0 10 11480-030 -120 0.7 1.2 1.7 HEADROOM (V) Figure 30. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage, ADM7151-04, VOUT = 5 V, 800 mA Load 100 1000 LOAD CURRENT (mA) 11480-033 PSRR (dB) -40 Figure 33. RMS Output Noise vs. Load Current (I LOAD ), 10 Hz to 100 kHz, ADM7151-02, VOUT = 4 V 2.0 2.0 1.6 1.6 NOISE (Vrms) 1.2 0.8 0.4 100Hz TO 100kHz 0.8 0.4 100 LOAD CURRENT (mA) 1000 0 10 11480-031 0 10 1.2 Figure 31. RMS Output Noise vs. Load Current (I LOAD ), 10 Hz to 100 kHz, ADM7151-04, VOUT = 5 V 100 LOAD CURRENT (mA) 1000 11480-034 NOISE (Vrms) 10Hz TO 100kHz Figure 34. RMS Output Noise vs. Load Current (I LOAD ), 100 Hz to 100 kHz, ADM7151-02, VOUT = 4 V Rev. A | Page 11 of 24 ADM7151 Data Sheet 100k 10k 100k 1M 10M FREQUENCY (Hz) Figure 35. Output Noise Spectral Density, 1 kHz to 10 MHz, ILOAD = 10 mA 10 100 1k 10k NOISE SPECTRAL DENSITY (nV/Hz) 10k 1k 100 10 1 10 100 1k 10k 100k 1M = 1F = 4.7F = 10F = 22F = 47F = 100F = 470F 1k 100 10 1 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 39. Output Noise Spectral Density vs. at Different CBYP, Load Current = 10 mA T LOAD = 800mA LOAD = 400mA LOAD = 200mA LOAD = 100mA LOAD = 10mA 100 CBYP CBYP CBYP CBYP CBYP CBYP CBYP 10k Figure 36. Output Noise Spectral Density, 0.1 Hz to 10 kHz, ILOAD = 10 mA 1k 100k Figure 38. Output Noise Spectral Density at Different Load Currents, 0.1 Hz to 1 MHz 100k FREQUENCY (Hz) 1 10 2 0.1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 37. Output Noise Spectral Density at Different Load Currents, 10 Hz to 10 MHz CH1 500mA BW CH2 20mV BW M20s A CH1 T 10.40% 200mA Figure 40. Load Transient Response, ILOAD = 1 mA to 800 mA, VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT Rev. A | Page 12 of 24 11480-040 1 11480-037 NOISE SPECTRAL DENSITY (nV/Hz) 1 FREQUENCY (Hz) 11480-036 NOISE SPECTRAL DENSITY (nV/Hz) 10 1 0.1 100k 1 0.1 100 11480-039 0.1 1k 1k 11480-038 NOISE SPECTRAL DENSITY (nV/Hz) 1 LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 400mA LOAD = 800mA 10k 11480-035 NOISE SPECTRAL DENSITY (nV/Hz) 10 Data Sheet ADM7151 T T 1 1 2 200mA CH1 1.0V BW CH2 2.0mV BW M10s A CH1 T 10.0% 1.14V 11480-044 CH1 500mA BW CH2 10mV BW M4s A CH1 T 11.0% 11480-041 2 Figure 44. Line Transient Response, 2 V Input Step, ILOAD = 800 mA, VOUT = 1.8 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT Figure 41. Load Transient Response, ILOAD = 10 mA to 800 mA, VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT T T 1 1 2 460mA CH1 1.0V BW CH2 2.0mV BW M10s A CH3 T 10.0% 1.14V 11480-045 CH1 200mA BW CH2 10mV BW M2s A CH1 T 11.0% 11480-042 2 Figure 45. Line Transient Response, 2 V Input Step, ILOAD = 800 mA, VOUT = 3.3 V, VIN = 4.5 V, CH1 = VIN, CH2 = VOUT Figure 42. Load Transient Response, ILOAD = 100 mA to 600 mA, VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT T T 1 1 2 50.0mA CH1 1.0V BW CH2 2.0mV BW M10s A CH3 T 10.0% 1.14V 11480-046 CH1 50.0mA BW CH2 2.0mV BW M4s A CH1 T 10.0% 11480-043 2 Figure 46. Line Transient Response, 2 V Input Step, ILOAD = 800 mA, VOUT = 5 V, VIN = 6.2 V, CH1 = VIN, CH2 = VOUT Figure 43. Load Transient Response, ILOAD = 1 mA to 100 mA, VOUT = 5 V, VIN = 6.2 V, CH1 = IOUT, CH2 = VOUT Rev. A | Page 13 of 24 ADM7151 Data Sheet 5.5 5.0 4.5 4.0 3.0 2.5 2.0 1.5 1.0 VEN VREG VREF VOUT 0.5 0 -0.5 0 1 2 3 4 5 6 7 8 9 TIME (ms) 10 11480-047 VOLTS 3.5 Figure 47. VOUT, VREF, VREG Start-Up Times After VEN Rising, VOUT = 3.3 V, VIN = 5 V Rev. A | Page 14 of 24 Data Sheet ADM7151 THEORY OF OPERATION ADM7151-04 VIN = 6.2V CIN 10F VBYP OFF CBYP 1F CREG 10F VOUT BYP REFERENCE REF_SENSE OTA E/A SHUTDOWN EN COUT 10F CREF 1F BYP VREG R1 VOUT = 1.5V x (R1 + R2)/R2 R2 1k < R2 < 200k GND Figure 49. Typical Adjustable Output Voltage Application Schematic GND REF REF VOUT = 5.0V Figure 48. Adjustable Output Voltage Internal Block Diagram Internally, the ADM7151 consists of a reference, an error amplifier, a feedback voltage divider, and a P-channel MOSFET pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The R2 value must be greater than 1 k to prevent excessive loading of the reference voltage appearing on the REF pin. To minimize errors in the output voltage caused by the REF_SENSE pin input current, the R2 value must be less than 200 k. For example, when R1 and R2 each equal 200 k, the output voltage is 3.0 V. The output voltage error introduced by the REF_SENSE pin input current is 10 mV or 0.33%, assuming a maximum REF_SENSE pin input current of 100 nA at 125C. The ADM7151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. VIN 18V VREG 6V REF REF_SENSE 6V BYP 6V OUT By heavily filtering the reference voltage, the ADM7151 is able to achieve 1.7 nV/Hz output typical from 10 kHz to 1 MHz. Because the error amplifier is always in unity gain, the output noise is independent of the output voltage. To maintain very high PSRR over a wide frequency range, the ADM7151 architecture uses an internal active ripple filter. This stage isolates the low output noise LDO from noise on VIN. The result is that the ADM7151 PSRR is significantly higher over a wider frequency range than any single stage LDO. EN 18V 6V 6V 6V 6V 6V GND 18V 11480-050 SHORT CIRCUIT, THERMAL PROTECT 11480-048 VREG EN REF_SENSE VREG VIN VOUT ON Optimized for use with 10 F ceramic capacitors, the ADM7151 provides excellent transient performance. ACTIVE RIPPLE FILTER VIN 11480-049 The ADM7151 is an adjustable, ultralow noise, high power supply rejection ratio (PSRR) linear regulator targeting radio frequency (RF) applications. The input voltage range is 4.5 V to 16 V, and it can deliver up to 800 mA of output current. Typical shutdown current consumption is 0.1 A at room temperature. Figure 50. Simplified ESD Protection Block Diagram The ESD protection devices are shown in the block diagram as Zener diodes (see Figure 50). The ADM7151 output voltage can be adjusted between 1.5 V and 5.1 V and is available in two models that optimize the input voltage and output voltage ranges to keep power dissipation as low as possible without compromising PSRR performance. The output voltage is determined by an external voltage divider according to the following equation: VOUT = 1.5 V x (1 + R1/R2) Rev. A | Page 15 of 24 ADM7151 Data Sheet APPLICATIONS INFORMATION MODEL SELECTION Input and VREG Capacitor The ADM7151 is available in two models to allow the user to select the best combination of power dissipation and PSRR performance for a given application. Connecting a 10 F capacitor from VIN to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered. CAPACITOR SELECTION To maintain the best possible stability and PSRR performance, connect a 10 F capacitor from VREG to GND. When more than 10 F of output capacitance is required, increase the input and VREG capacitors to match it. Output Capacitor The ADM7151 is designed for operation with ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 10 F capacitance with an ESR of 0.2 or less is recommended to ensure the stability of the ADM7151. Output capacitance also affects transient response to changes in load current. Using a larger value of output capacitance improves the transient response of the ADM7151 to large changes in load current. Figure 51 shows the transient responses for an output capacitance value of 10 F. REF Capacitor The REF capacitor is necessary to stabilize the reference amplifier. Connect a capacitor of at least 1 F between REF and GND. T 1 CH1 500mA BW CH2 10mV B W M4s A CH1 T 11.0% 200mA 11480-051 2 Figure 51. Output Transient Response, VOUT = 5 V, COUT = 10 F Table 6. Model Selection Guide for PSRR Model ADM7151-02 ADM7151-04 VOUT Range (V) 1.5 to 4.0 1.5 to 5.1 PSRR (dB) at 800 mA, 1.2 V Headroom 10 kHz 100 kHz 1 MHz 91 91 50 84 84 53 PSRR (dB) at 400 mA, 1 V Headroom 10 kHz 100 kHz 1 MHz 94 94 58 94 94 67 Table 7. Model Selection Guide for Input Voltage Model ADM7151-02 ADM7151-04 1 VOUT Range (V) 1.5 to 4.0 1.5 to 5.1 Minimum VIN at 800 mA Load VOUT < 3.3 V VOUT < 5 V VOUT 3.3 V VOUT 5 V 4.5 V N/A1 VOUT + 1.2 V N/A1 1 1 N/A 6.2 V N/A VOUT + 1.2 V N/A = not applicable. Rev. A | Page 16 of 24 Minimum VIN at 400 mA Load VOUT < 3.3 V VOUT < 5 V VOUT 3.3 V VOUT 5 V 4.5 V N/A1 VOUT + 1.0 V N/A1 1 1 N/A 6V N/A VOUT + 1.0 V Data Sheet ADM7151 BYP Capacitor The BYP capacitor is necessary to filter the reference buffer. A 1 F capacitor is typically connected between BYP and GND. Capacitors as small as 0.1 F can be used; however, the output noise voltage of the LDO increases as a result. In addition, the BYP capacitor can be increased to reduce the noise below 1 kHz at the expense of increasing the start-up time of the LDO. Very large values of CBYP significantly reduce the noise below 10 Hz. Tantalum capacitors are recommended for capacitors larger than about 33 F. A 1 F ceramic capacitor in parallel with the larger tantalum capacitor is required to retain good noise performance at higher frequencies. CBYP CBYP CBYP CBYP CBYP CBYP CBYP CBYP 10k 1k = 1F = 4.7F = 10F = 22F = 47F = 100F = 470F = 1mF Figure 54 depicts the capacitance vs. dc bias voltage of a 1206, 10 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 12 10 CAPACITANCE (F) 100 8 6 4 2 10 0 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 52. Noise Spectral Density vs. Frequency, CBYP = 1 F to 1 mF NOISE SPECTRAL DENSITY (nV/Hz) 10k 1Hz 10Hz 100Hz 400Hz 3Hz 30Hz 300Hz 1kHz 2 4 6 8 10 DC BIAS VOLTAGE (V) 11480-052 1 0.1 Figure 54. Capacitance vs. DC Bias Voltage Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) 1k 11480-054 NOISE SPECTRAL DENSITY (nV/Hz) 100k X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V are recommended. However, Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. 100 In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 9.72 F at 5 V, as shown in Figure 54. 10 1 10 100 11480-053 1 1000 CBYP (F) Figure 53. Noise Spectral Density vs. CBYP for Different Frequencies Capacitor Properties Any good quality ceramic capacitors can be used with the ADM7151 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. Substituting these values in Equation 1 yields CEFF = 9.72 F x (1 - 0.15) x (1 - 0.1) = 7.44 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADM7151, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. A | Page 17 of 24 ADM7151 Data Sheet ENABLE (EN) AND UNDERVOLTAGE LOCKOUT (UVLO) 2.4 EN FALL THRESHOLD (V) 2.2 The ADM7151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 55, when a rising voltage on EN crosses the upper threshold, VOUT turns on. When a falling voltage on EN crosses the lower threshold, VOUT turns off. The hysteresis varies as a function of the input voltage. For example, the EN hysteresis is approximately 200 mV with an input voltage of 4.5 V. 3.5 2.0 1.8 -40C 1.6 +25C 1.0 6 8 10 2.5 12 14 16 VIN (V) Figure 57. Typical EN Fall Threshold vs. Input Voltage (VIN) for Various Temperatures 2.0 VOUT_EN_FALL The ADM7151 also incorporates an internal undervoltage lockout circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. The upper and lower thresholds are internally fixed with approximately 300 mV of hysteresis. 1.5 VOUT_EN_RISE 1.0 1.1 1.2 1.3 1.4 1.5 1.6 VEN (V) 3.5 11480-055 0.5 0 1.0 11480-057 1.2 3.0 VOUT (V) +125C 1.4 3.0 Figure 55. Typical VOUT Response to EN Pin Operation, VOUT = 3.3 V, VIN = 5 V 2.5 3.2 VOUT_VIN_FALL VOUT (V) 3.0 1.5 2.6 VOUT_VIN_RISE 1.0 -40C 2.4 +125C 2.2 0.5 +25C 2.0 0 4.0 1.8 4.1 4.2 4.3 4.4 VIN (V) 4.5 11480-058 EN RISE THRESHOLD (V) 2.8 2.0 Figure 58. Typical UVLO Hysteresis, VOUT = 3.3 V 1.4 6 8 10 12 VIN (V) 14 16 11480-056 1.6 Figure 56. Typical EN Rise Threshold vs. Input Voltage (VIN) for Various Temperatures Figure 58 shows the typical hysteresis of the UVLO function. This hysteresis prevents on/off oscillations that can occur due to noise on the input voltage as it passes through the threshold points. Rev. A | Page 18 of 24 Data Sheet ADM7151 START-UP TIME The ADM7151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for a 5 V output is approximately 3 ms from the time the EN active threshold is crossed to when the output reaches 90% of its final value. The rise time of the output voltage (10% to 90%) is approximately 0.0012 x CBYP seconds where CBYP is in microfarads. 6 ENABLE CBYP = 1F CBYP = 4.7F CBYP = 10F 5 VOUT (V) 4 3 2 0 0 0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 TIME (Seconds) 11480-059 1 Figure 59. Typical Start-Up Behavior with CBYP = 1 F to 10 F 6 5 Thermal overload protection is included, which limits the junction temperature to a maximum of 155C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 155C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 140C, the output is turned on again, and output current is restored to its operating value. Consider the case where a hard short from VOUT to GND occurs. At first, the ADM7151 current limits, so that only 1.3 A is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 155C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140C, the output turns on and conducts 1.3 A into the short, again causing the junction temperature to rise above 155C. This thermal oscillation between 140C and 155C causes a current oscillation between 1.3 A and 0 mA that continues as long as the short remains at the output. Current-limit and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 150C. THERMAL CONSIDERATIONS In applications with low input to output voltage differential, the ADM7151 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package can become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 150C. 4 VOUT (V) output load reaches 1.3 A (typical). When the output load exceeds 1.3 A, the output voltage is reduced to maintain a constant current limit. 3 2 1 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 TIME (Seconds) 11480-060 ENABLE CBYP = 10F CBYP = 47F CBYP = 330F Figure 60. Typical Start-Up Behavior with CBYP = 10 F to 330 F REF, BYP, AND VREG PINS REF, BYP, and VREG are internally generated voltages that require external bypass capacitors for proper operation. Do not, under any circumstances, connect any loads to these pins because doing so compromises the noise and PSRR performance of the ADM7151. Using larger values of CBYP, CREF, and CREG is acceptable but can increase the start-up time, as described in the Start-Up Time section. CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADM7151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADM7151 is designed to current limit when the When the junction temperature exceeds 155C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 140C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADM7151 must not exceed 150C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pin and exposed pad to the PCB. Rev. A | Page 19 of 24 ADM7151 Data Sheet Table 8 shows typical JA values of the 8-lead SOIC and 8-lead LFCSP packages for various PCB copper sizes. Table 9 shows the typical JB values of the 8-lead SOIC and 8-lead LFCSP. Figure 61 to Figure 66 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of PCB copper. 155 145 Table 8. Typical JA Values 115 105 95 85 75 65 55 Device soldered to minimum size pin traces. 35 25 JB (C/W) 15.1 17.9 0 TOTAL POWER DISSIPATION (W) Figure 61. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, TA = 25C The junction temperature of the ADM7151 is calculated from the following equation: where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (3) where: VIN and VOUT are thinput and output voltages, respectively. ILOAD is the load current. IGND is the groune d current. 150 130 120 110 100 90 80 6400mm 2 500mm 2 25mm 2 TJ MAX 70 60 50 Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: 0 The heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADM7151. Adding thermal planes under the package also improves thermal performance. However, as listed in Table 8, a point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance. 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Figure 62. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, TA = 50C (4) As shown in Equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 150C. 0.2 TOTAL POWER DISSIPATION (W) 155 145 JUNCTION TEMPERATURE (C) TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} 140 11480-062 (2) 160 JUNCTION TEMPERATURE (C) TJ = TA + (PD x JA) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 11480-061 6400mm 2 500mm 2 25mm 2 TJ MAX 45 Table 9. Typical JB Values Package 8-Lead LFCSP 8-Lead SOIC 125 135 125 115 105 95 85 6400mm 2 500mm 2 25mm 2 TJ MAX 75 65 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 TOTAL POWER DISSIPATION (W) Figure 63. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, TA = 85C Rev. A | Page 20 of 24 11480-063 1 JUNCTION TEMPERATURE (C) Copper Size (mm2) 251 100 500 1000 6400 135 JA (C/W) 8-Lead LFCSP 8-Lead SOIC 165.1 165 125.8 126.4 68.1 69.8 56.4 57.8 42.1 43.6 Data Sheet ADM7151 Thermal Characterization Parameter (JB) When the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise (see Figure 67 and Figure 68). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: 155 145 125 115 102 95 85 75 TJ = TB + (PD x JB) 65 The typical value of JB is 15.1C/W for the 8-lead LFCSP package and 17.9C/W for the 8-lead SOIC package. 6400mm 2 500mm 2 25mm 2 TJ MAX 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 TOTAL POWER DISSIPATION (W) 160 Figure 64. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 25C 160 140 130 120 110 120 100 80 60 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 40 20 100 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 90 TOTAL POWER DISSIPATION (W) 80 Figure 67. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP 6400mm 2 500mm 2 25mm 2 TJ MAX 60 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TOTAL POWER DISSIPATION (W) 160 140 JUNCTION TEMPERATURE (C) 70 11480-065 JUNCTION TEMPERATURE (C) 150 Figure 65. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 50C 155 145 135 125 115 120 100 80 60 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 40 20 105 0 0 95 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 TOTAL POWER DISSIPATION (W) 85 6400mm 2 75 500mm 2 25mm 2 TJ MAX 65 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TOTAL POWER DISSIPATION (W) Figure 68. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC 11480-066 JUNCTION TEMPERATURE (C) 140 11480-067 35 JUNCTION TEMPERATURE (C) 45 (5) Figure 66. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, TA = 85C Rev. A | Page 21 of 24 11480-068 55 11480-064 JUNCTION TEMPERATURE (C) 135 ADM7151 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS 11480-070 Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Place the bypass capacitors for VREG, VREF, and VBYP close to the respective pins and GND. Use of an 0805, 0603, or 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited. 11480-069 Figure 70. Example 8-Lead SOIC PCB Layout Figure 69. Example 8-Lead LFCSP PCB Layout Rev. A | Page 22 of 24 Data Sheet ADM7151 OUTLINE DIMENSIONS 2.44 2.34 2.24 3.10 3.00 SQ 2.90 0.50 BSC 8 5 PIN 1 INDEX AREA 1.70 1.60 1.50 EXPOSED PAD 0.50 0.40 0.30 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 11-28-2012-C 0.80 0.75 0.70 SEATING PLANE 0.20 MIN PIN 1 INDICATOR (R 0.15) 1 4 TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-229-WEED Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-8-11) Dimensions shown in millimeters 5.00 4.90 4.80 3.098 0.356 5 1 4 6.20 6.00 5.80 4.00 3.90 3.80 2.41 0.457 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 SEATING PLANE 0.51 0.31 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 8 0 45 0.25 0.17 1.04 REF 1.27 0.40 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters Rev. A | Page 23 of 24 06-03-2011-B 8 ADM7151 Data Sheet ORDERING GUIDE Model1 ADM7151ACPZ-02-R2 ADM7151ACPZ-02-R7 ADM7151ARDZ-02 ADM7151ARDZ-02-R7 ADM7151ACPZ-04-R2 ADM7151ACPZ-04-R7 ADM7151ARDZ-04 ADM7151ARDZ-04-R7 ADM7151CP-02-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage Range(V) 1.5 to 4.0 1.5 to 4.0 1.5 to 4.0 1.5 to 4.0 1.5 to 5.1 1.5 to 5.1 1.5 to 5.1 1.5 to 5.1 1.5 to 4.0 Z = RoHS Compliant Part. (c)2013-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11480-0-4/15(A) Rev. A | Page 24 of 24 Package Description 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP Evaluation Board Package Option CP-8-11 CP-8-11 RD-8-2 RD-8-2 CP-8-11 CP-8-11 RD-8-2 RD-8-2 Branding LNN LNN LNP LNP Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADM7151ARDZ-02 ADM7151ACPZ-04-R7 ADM7151ARDZ-04 ADM7151CP-02-EVALZ ADM7151ARDZ-02-R7 ADM7151ACPZ-02-R7 ADM7151ARDZ-04-R7