MC10EL51DR2 - ON Semiconductor

 Semiconductor Components Industries, LLC, 2000

October, 2000 – Rev. 3 1Publication Order Number:

MC10EL51/D

MC10EL51, MC100EL51

5VECL Differential Clock D

FlipFlop

The MC10EL/100EL51 is a differential clock D flip-flop with reset.

The device is functionally similar to the E151 device with higher

performance capabilities. With propagation delays and output

transition times significantly faster than the E151 the EL51 is ideally

suited for those applications which require the ultimate in AC

performance.

The reset input is an asynchronous, level triggered signal. Data

enters the master portion of the flip-flop when the clock is LOW and is

transferred to the slave, and thus the outputs, upon a positive transition

of the clock. The differential clock inputs of the EL51 allow the device

to be used as a negative edge triggered flip-flop.

The differential input employs clamp circuitry to maintain stability

under open input (pulled down to VEE) conditions.

The 100 Series contains temperature compensation.

•475 ps Propagation Delay

•2.8 GHz Toggle Frequency

•ESD Protection: > 1 KV HBM, > 100 V MM

•PECL Mode Operating Range: VCC= 4.2 V to 5.7 V

with VEE= 0 V

•NECL Mode Operating Range: VCC= 0 V

with VEE= –4.2 V to –5.7 V

•Internal Input Pulldown Resistors on D, R, and CLK

•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

•Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

•Flammability Rating: UL–94 code V–0 @ 1/8”,

Oxygen Index 28 to 34

•Transistor Count = 73 devices

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Device Package Shipping

ORDERING INFORMATION

MC10EL51D SO–8 98 Units/Rail

MC10EL51DR2 SO–8 2500 Tape & Reel

MC100EL51D SO–8 98 Units/Rail

MC100EL51DR2 SO–8 2500 Tape & Reel

MC10EL51DT TSSOP–8 98 Units/Rail

MC10EL51DTR2 TSSOP–8 2500 Tape & Reel

MC100EL51DT TSSOP–8 98 Units/Rail

MC100EL51DTR2 TSSOP–8 2500 Tape & Reel

L = Wafer Lot

Y = Year

W = Work Week

*For additional information, see Application Note

AND8002/D

H = MC10

K = MC100

A = Assembly Location

SO–8

D SUFFIX

CASE 751

MARKING

DIAGRAMS*

TSSOP–8

DT SUFFIX

CASE 948R

ALYW

KEL51

HEL51

ALYW

HL51

ALYW

KL51

MC10EL51, MC100EL51

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VEE

VCC

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

QCLK

CLK

DRTRUTH TABLE

CLK*

Q**

Z = LOW to HIGH Transition

PIN FUNCTION

R ECL Reset Input

D ECL Data Input

CLK, CLK ECL Clock Inputs

Q, Q ECL Data Outputs

VCC Positive Supply

VEE Negative Supply

PIN DESCRIPTION

* Pin will default low when left open.

**Pin will default low when inputs are left open.

MAXIMUM RATINGS (Note 1.)

Symbol Parameter Condition 1 Condition 2 Rating Units

VCC PECL Mode Power Supply VEE = 0 V 8 V

VEE NECL Mode Power Supply VCC = 0 V –8 V

VIPECL Mode Input Voltage VEE = 0 V VI  VCC 6 V

C ode u o age

NECL Mode Input Voltage

EE 0

VCC = 0 V

ICC

VI  VEE

–6 V

Iout Output Current Continuous

Surge 50

100 mA

TA Operating Temperature Range –40 to +85 °C

Tstg Storage Temperature Range –65 to +150 °C

θJA Thermal Resistance (Junction to Ambient) 0 LFPM

500 LFPM 8 SOIC

8 SOIC 190

130 °C/W

°C/W

θJC Thermal Resistance (Junction to Case) std bd 8 SOIC 41 to 44 °C/W

θJA Thermal Resistance (Junction to Ambient) 0 LFPM

500 LFPM 8 TSSOP

8 TSSOP 185

140 °C/W

°C/W

θJC Thermal Resistance (Junction to Case) std bd 8 TSSOP 41 to 44 ± 5% °C/W

Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C

1. Maximum Ratings are those values beyond which device damage may occur.

MC10EL51, MC100EL51

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10EL SERIES PECL DC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V (Note 1.)

–40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 24 29 24 29 24 29 mA

VOH Output HIGH Voltage (Note 2.) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV

VOL Output LOW Voltage (Note 2.) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV

VIH Input HIGH Voltage (Single Ended) 3770 4110 3870 4190 3940 4280 mV

VIL Input LOW Voltage (Single Ended) 3050 3500 3050 3520 3050 3555 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 3.) 2.5 4.6 2.5 4.6 2.5 4.6 V

IIH Input HIGH Current 150 150 150 µA

IIL Input LOW Current 0.5 0.5 0.3 µA

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / –0.5 V.

2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. Th e VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmi n and 1 V.

10EL SERIES NECL DC CHARACTERISTICS VCC= 0.0 V; VEE= –5.0 V (Note 1.)

–40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 24 29 24 29 24 29 mA

VOH Output HIGH Voltage (Note 2.) –1080 –990 –890 –980 –895 –810 –910 –815 –720 mV

VOL Output LOW Voltage (Note 2.) –1950 –1800 –1650 –1950 –1790 –1630 –1950 –1773 –1595 mV

VIH Input HIGH Voltage (Single Ended) –1230 –890 –1130 –810 –1060 –720 mV

VIL Input LOW Voltage (Single Ended) –1950 –1500 –1950 –1480 –1950 –1445 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 3.) –2.5 –0.4 –2.5 –0.4 –2.5 –0.4 V

IIH Input HIGH Current 150 150 150 µA

IIL Input LOW Current 0.5 0.5 0.3 µA

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / –0.5 V.

2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. Th e VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmi n and 1 V.

MC10EL51, MC100EL51

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100EL SERIES PECL DC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V (Note 1.)

–40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 24 29 24 29 30 36 mA

VOH Output HIGH Voltage (Note 2.) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV

VOL Output LOW Voltage (Note 2.) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV

VIH Input HIGH Voltage (Single Ended) 3835 4120 3835 4120 3835 4120 mV

VIL Input LOW Voltage (Single Ended) 3190 3525 3190 3525 3190 3525 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 3.) 2.5 4.6 2.5 4.6 2.5 4.6 V

IIH Input HIGH Current 150 150 150 µA

IIL Input LOW Current 0.5 0.5 0.5 µA

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / –0.5 V.

2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. Th e VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmi n and 1 V.

100EL SERIES NECL DC CHARACTERISTICS VCC= 0.0 V; VEE= –5.0 V (Note 1.)

–40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 24 29 24 29 30 36 mA

VOH Output HIGH Voltage (Note 2.) –1085 –1005 –880 –1025 –955 –880 –1025 –955 –880 mV

VOL Output LOW Voltage (Note 2.) –1830 –1695 –1555 –1810 –1705 –1620 –1810 –1705 –1620 mV

VIH Input HIGH Voltage (Single Ended) –1165 –880 –1165 –880 –1165 –880 mV

VIL Input LOW Voltage (Single Ended) –1810 –1475 –1810 –1475 –1810 –1475 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 3.) –2.5 –0.4 –2.5 –0.4 –2.5 –0.4 V

IIH Input HIGH Current 150 150 150 µA

IIL Input LOW Current 0.5 0.5 0.5 µA

NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The

circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / –0.5 V.

2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts.

3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. Th e VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmi n and 1 V.

MC10EL51, MC100EL51

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AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –5.0 V (Note 1.)

–40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

fmax Maximum Toggle Frequency 1.8 2.8 2.2 2.8 2.2 2.8 GHz

tPLH

tPHL Propagation Delay

to Output CLK

R325

305 465

455 605

605 385

355 475

465 565

565 440

410 530

510 620

620

tSSetup Time 150 0 150 0 150 0 ps

tHHold Time 250 100 250 100 250 100 ps

tRR Reset Recovery 400 200 400 200 400 200 ps

tPW Minimum Pulse Width CLK, Reset 400 400 400 ps

VPP Input Swing (Note 2.) 150 1000 150 1000 150 1000 mV

tJITTER Cycle–to–Cycle Jitter TBD TBD TBD ps

tfOutput Rise/Fall Times Q

(20% – 80%) 100 225 350 100 225 350 100 225 350 ps

1. 10 Series: VEE can vary +0.25 V / –0.5 V.

100 Series: VEE can vary +0.8 V / –0.5 V.

2. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.

VTT =VCC – 2.0 V

Figure 1. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 – Termination of ECL Logic Devices.)



Driver

Device Receiver

Device

50 

VTT

Resource Reference of Application Notes

AN1404 –ECLinPS Circuit Performance at Non–Standard VIH Levels

AN1405 –ECL Clock Distribution Techniques

AN1406 –Designing with PECL (ECL at +5.0 V)

AN1503 –ECLinPS I/O SPICE Modeling Kit

AN1504 –Metastability and the ECLinPS Family

AN1560 –Low Voltage ECLinPS SPICE Modeling Kit

AN1568 –Interfacing Between LVDS and ECL

AN1596 –ECLinPS Lite Translator ELT Family SPICE I/O Model Kit

AN1650 –Using Wire–OR Ties in ECLinPS Designs

AN1672 –The ECL Translator Guide

AND8001 –Odd Number Counters Design

AND8002 –Marking and Date Codes

AND8020 –Termination of ECL Logic Devices

MC10EL51, MC100EL51

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PACKAGE DIMENSIONS

SO–8

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751–07

ISSUE V

SEATING

PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

–X–

–Y–

0.25 (0.010)

–Z–

0.25 (0.010) Z SXS



TSSOP–8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT

EXCEED 0.25 (0.010) PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE -W-.

 

SEATING

PLANE

PIN 1 14

DETAIL E

2X L/2

–U–

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

MC10EL51, MC100EL51

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Notes

MC10EL51, MC100EL51

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

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For additional information, please contact your local

Sales Representative.

MC10EL51/D

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