843441 FemtoClock(R) SAS/SATA Clock Generator Data Sheet 843441-150 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The 843441 is a low jitter, high performance clock generator. The 843441 is designed for use in applications using the SAS and SATA interconnect. The 843441 uses an external, 25MHz, parallel resonant crystal to generate four selectable output frequencies: 75MHz, 100MHz, 150MHz, and 300MHz. This silicon based approach provides excellent frequency stability and reliability. The 843441 features down and center spread spectrum (SSC) clocking techniques. Additional Ordering Information Part/Order Number 843441AG 843441AM-75 843441AM-100 843441AM-150 843441AM-300 Package Output Frequency (MHz) 75, 100, 150, 300 75 100 150 300 16 TSSOP 8 SOIC 8 SOIC 8 SOIC 8 SOIC * * * * * * Designed for use in SAS, SAS-2, and SATA systems * External fundamental crystal frequency ensures high reliability and low aging * Selectable output frequencies: 75MHz, 100MHz, 150MHz, 300MHz * * * * * * * Output frequency is tunable with external capacitors Center (0.33%) Spread Spectrum Clocking (SSC) Down (-0.30% or -0.60%) SSC Better frequency stability than SAW oscillators One differential 3.3V LVPECL output Crystal oscillator interface designed for 25MHz (CL = 18pF) frequency RMS phase jitter: 1.33ps (typical) 3.3V operating supply 0C to 70C ambient operating temperature Industrial temperature available upon request Available in lead-free (RoHS 6) package 843441-150 Functional replacement part use 8T49N242i Pin Assignments Block Diagrams XTAL_IN 25MHz XTAL OSC FemtoClock Q nQ PLL XTAL_OUT SSC_SEL(1:0) SSC Output Control Logic Pulldown:Pulldown 8 - Lead SOIC F_SEL(1:0) Pullup : Pulldown nPLL_SEL Pulldown 843441 8-Lead SOIC, 150 Mil 3.90mm x 4.90mm x 1.375mm package body M Package Top View VEE XTAL_IN 25MHz XTAL OSC FemtoClock PLL XTAL_OUT SSC_SEL(1:0) Pulldown: Pulldown 0 1 00 = 75MHz 01 = 100MHz 10 = 150MHz (default) 11 = 300MHz SSC Output Control Logic 16- Lead TSSOP (c)2016 Integrated Device Technology, Inc 1 Q nQ XTAL_OUT XTAL_IN SSC_SEL0 nc nc nc SSC_SEL1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 F_SEL1 VEE nPLL_SEL nQ Q VCC F_SEL0 VCC 843441 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View June 30, 2016 843441 Data Sheet Table 1A. Pin Descriptions (SOIC Package) Number Name 1, 2 XTAL_OUT, XTAL_IN Type Description Input Pullup 3, 4 SSC_SEL0, SSC_SEL1 Input Pulldown Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. 5 VCC Power Power supply pin. 6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels. 8 VEE Power Negative supply pin. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 1B. Pin Descriptions (TSSOP Package) Number Name 1, 15 VEE Power Type Description 2, 3 XTAL_OUT, XTAL_IN Input Pullup 4, 8 SSC_SEL0, SSC_SEL1 Input Pulldown 5, 6, 7 nc Unused 9, 11 VCC Power 10 F_SEL0 Input 12, 13 Q, nQ Output 14 nPLL_SEL Input Pulldown 16 F_SEL1 Input Pullup Negative supply pins. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels. No connect pins. Power supply pins. Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. Differential clock outputs. LVPECL interface levels. PLL Bypass pin. LVCMOS/LVTTL interface levels. Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels. NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 k RPULLUP Input Pullup Resistor 51 k (c)2016 Integrated Device Technology, Inc Test Conditions 2 Minimum Typical Maximum Units June 30, 2016 843441 Data Sheet Function Tables Table 3A. SSC_SEL[1:0] Function Table Inputs SSC_SEL1 SSC_SEL0 Mode 0 (default) 0 (default) SSC Off 0 1 0.60% Down-spread 1 0 0.30% Down-spread 1 1 0.33% Center-spread Table 3B. F_SEL[1:0] Function Table Inputs F_SEL1 F_SEL0 Output Frequency (MHz) 0 0 75 0 1 100 1 (default) 0 (default) 150 1 1 300 Table 3B applicable only for 16 Lead TSSOP package. (c)2016 Integrated Device Technology, Inc 3 June 30, 2016 843441 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI, (LVCMOS) XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 16 Lead TSSOP 8 Lead SOIC 81.2C/W (0 mps) 96.0C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 66 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current IIL Input Low Current F_SEL1 VCC = VIN = 3.465V 5 A SSC_SEL[0:1], F_SEL0, nPLL_SEL VCC = VIN = 3.465V 150 A F_SEL1 VCC = 3.465V, VIN = 0V -150 A SSC_SEL[0:1], F_SEL0, nPLL_SEL VCC = 3.465V, VIN = 0V -5 A Table 4C. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.6 0.9 V NOTE 1: Output termination with 50 to VCC - 2V. (c)2016 Integrated Device Technology, Inc 4 June 30, 2016 843441 Data Sheet AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C Symbol fOUT tjit(O) tjit(per) tjit(cc) Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Period Jitter, RMS; NOTE 2, 3 Cycle-to-Cycle Jitter: NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units F_SEL(1:0) = 00 75 MHz F_SEL(1:0) = 01 100 MHz F_SEL(1:0) = 10 150 MHz F_SEL(1:0) = 11 300 MHz 75MHz, Integration Range: 12kHz - 20 MHz 1.33 ps 100MHz, Integration Range: 12kHz - 20MHz 1.39 ps 150MHz, Integration Range: 12kHz - 20MHz 1.36 ps 300MHz, Integration Range: 12kHz - 20MHz 1.37 ps 75MHz, SSC Off 4.15 ps 100MHz, SSC Off 4.05 ps 150MHz, SSC Off 4.15 ps 300MHz, SSC Off 4.25 ps 75MHz, SSC Off 31 ps 100MHz, SSC Off 31 ps 150MHz, SSC Off 31 ps 300MHz, SSC Off 31 ps 200 700 ps 45 55 % 20% to 80% NOTE: Using a 25MHz, 18pF quartz crystal. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to the Phase Noise plots. NOTE 2: Refer to Application Section for peak-to-peak jitter calculations. NOTE 3: Tested per JEDEC 65B. (c)2016 Integrated Device Technology, Inc 5 June 30, 2016 843441 Data Sheet Typical Phase Noise at 100MHz Noise Power dBc Hz 100MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.39ps (typical) Offset Frequency (Hz) NOTE: Measured on Aeroflex PN9000 (c)2016 Integrated Device Technology, Inc 6 June 30, 2016 843441 Data Sheet Parameter Measurement Information 2V VCC Qx SCOPE nQx VEE -1.3V 0.165V 3.3V LVPECL Output Load AC Test Circuit RMS Phase Jitter nQ nQ Q Q Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period VOH VREF nQ Q VOL tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles t jit (pk-pk) Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) 10,000 cycles RMS Period Jitter, Peak-to-Peak Cycle-to-Cycle Jitter (c)2016 Integrated Device Technology, Inc 7 June 30, 2016 843441 Data Sheet Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Control Pins All control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, VCC matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 (c)2016 Integrated Device Technology, Inc 8 June 30, 2016 843441 Data Sheet Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 2A. 3.3V LVPECL Output Termination (c)2016 Integrated Device Technology, Inc R2 84 Figure 2B. 3.3V LVPECL Output Termination 9 June 30, 2016 843441 Data Sheet Schematic Example Figure 3 shows an example of 843441 application schematic. In this example, the device is operated at VCC = 3.3V. An 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will required adjusting C1 and C2. the opposite side. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 843441 provides separate power supplies to isolate noise from coupling into the internal PLL. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1F capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. U1 3.3V XTAL_OUT XTAL_IN SSC_SEL0 SSC_SEL1 1 2 3 4 5 6 7 8 VEE XTAL_OUT XTAL_IN SSC_SEL0 nc nc nc SSC_SEL1 F_SEL1 VEE nPLL_SEL nQ Q VCC F_SEL0 VCC F_SEL1 16 15 14 13 12 11 10 9 R1 133 nPLL_SEL R2 133 Zo = 50 Ohm Q + F_SEL0 nQ C3 Zo = 50 Ohm 0.1uF - X1 25MHz F p 8 1 C2 27pF BLM18BB221SN1 C1 27pF VCC C4 0.1uF Set Logic Input to '1' RU1 1K RD1 Not Install 2 C6 0.1uF Zo = 50 Ohm + RU2 Not Install To Logic Input pins R4 82.5 LVPECL Termination Set Logic Input to '0' VCC R3 82.5 Ferrite Bead 10uF Logic Control Input Examples VCC 1 C5 3.3V Zo = 50 Ohm - To Logic Input pins R5 50 R6 50 RD2 1K Optional Y-Termination R7 50 Figure 3. 843441 Schematic Example (c)2016 Integrated Device Technology, Inc 10 June 30, 2016 843441 Data Sheet Peak-to-Peak Jitter Calculations BER requirement. Because a standard deviation is the variation from the mean of the data set, it is important to always calculate the peak-to-peak jitter using the typical RMS value. A standard deviation of a statistical population or data set is the square root of its variance. A standard deviation is used to calculate the probability of an anomaly or to predict a failure. Many times, the term "root mean square" (RMS) is used synonymously for standard deviation. This is accurate when referring to the square root of the mean squared deviation of a signal from a given baseline and the data set contains a Gaussian distribution with no deterministic components. A low standard deviation indicates that the data set tends to be close to the mean with little variation. A large standard deviation indicates that the data set is spread out and has a large variation from the mean. The table shows the BER with its appropriate RMS Multiplier. Once the BER is chosen, the peak to peak jitter can be calculated by simply multiplying the RMS multiplier with the typical RMS datasheet specification. For example, if a 10-12 BER is required, multiply 14.260 times the typical jitter specification. Jitter (peak-to-peak) = RMS Multiplier x RMS (typical) This calculation is not specific to one type of Jitter classification. It can be used to calculate BER on various types of RMS jitter. It is important that the user understands their jitter requirement to ensure they are calculating the correct BER for their jitter requirement. A standard deviation is required when calculating peak-to-peak jitter. Since true peak-to-peak jitter is random and unbounded, it is important to always associate a bit error ratio (BER) when specifying a peak-to-peak jitter limit. Without it, the specification is meaningless. Given that a BER is application specific, many frequency timing devices specify jitter as an RMS. This allows the peak-to-peak jitter to be calculated for the specific application and BER RMS Multiplier 10-3 6.582 10-4 7.782 -5 10 8.834 10-6 9.784 -7 10 10.654 10-8 11.462 10-9 12.218 -10 10 12.934 10-11 13.614 10-12 14.260 -13 10 14.882 10-14 15.478 -15 16.028 10 (c)2016 Integrated Device Technology, Inc 11 June 30, 2016 843441 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 843441. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 843441 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.69mW * Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 30mW = 258.69mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96C/W per Table 6B below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.259W * 96C/W = 94.864C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2C/W 73.9C/W 70.2C/W 0 200 500 96C/W 87C/W 82C/W Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards (c)2016 Integrated Device Technology, Inc 12 June 30, 2016 843441 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW (c)2016 Integrated Device Technology, Inc 13 June 30, 2016 843441 Data Sheet Reliability Information Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 81.2C/W 73.9C/W 70.2C/W 0 200 500 96C/W 87C/W 82C/W Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC JA vs. Air Flow Linear Feet per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for 843441 is: 6303 (c)2016 Integrated Device Technology, Inc 14 June 30, 2016 843441 Data Sheet Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP Package Outline - M Suffix for 8 Lead SOIC Table 8B. Package Dimensions for 8 Lead SOIC Table 8A. Package Dimensions for 16 Lead TSSOP All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MS-012 Reference Document: JEDEC Publication 95, MO-153 (c)2016 Integrated Device Technology, Inc 15 June 30, 2016 843441 Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number 843441AGLF 843441AGLFT 843441AM-75LF 843441AM-75LFT 843441AM-100LF 843441AM-100LFT 843441AM-150LF 843441AM-150LFT 843441AM-300LF 843441AM-300LFT Marking 843441AL 843441AL 3441A75L 3441A75L 441A100L 441A100L 441A150L 441A150L 441A300L 441A300L (c)2016 Integrated Device Technology, Inc Package 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC 16 Shipping Packaging Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C June 30, 2016 843441 Data Sheet Revision History Sheet Rev Table Page A T3A 3 SSC_SEL Function Table - updated Mode column. 5/18/11 T9 16 Ordering Information - Removed quantity in tape and reel. Deleted LF note below table. Removed ICS from part number where needed. Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer 6/30/16 A Description of Change (c)2016 Integrated Device Technology, Inc Date 17 June 30, 2016 843441 Data Sheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com/go/support www.IDT.com www.IDT.com/go/sales DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. (c)2016 Integrated Device Technology, Inc 18 June 30, 2016