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P-Series Linear Photodiode Array Imagers
14µm, single output, 512, 1024, 2048 elements
Description
In the P-series linear imager,
PerkinElmer has combined the best
features of high-sensitivity photodiode
array detection and high-speed charge-
coupled scanning to offer an uncom-
promising solution to the increasing
demands of advanced imaging
applications
These high performance imagers
feature low noise, high sensitivity,
impressive charge storage capacity,
and lag-free dynamic imaging in a
convenient single-output architecture.
The 14µm square contiguous pixels in
these imagers reproduce images with
minimum information loss and artifact
generation, while their unique photo-
diode structure provides excellent blue
response extending below 250nm and
into the ultraviolet.
The two-phase CCD readout register
requires only 5 volts for clocking yet
achieves excellent charge transfer
efficiency. Additional electrodes provide
independent control of exposure and
antiblooming. Finally, the high-sensitivity
readout amplifier provides a large output
signal to relax noise requirements on the
camera electronics that follow.
Available in standard array lengths of 512,
1024, and 2048 elements with either glass
or UV-enhanced fused silica windows,
these versatile imagers are widely used in
high-speed document reading, web
inspection, mail sorting, production mea-
surement and gauging, position sensing,
spectroscopy, and other industrial and
scientific applications requiring peak
imager performance.
Features
Extended spectral range--200 to
1000 nm
40 MHz pixel readout rate with line
rates to 70 kHz
>2500:1 dynamic range
5-volt clocking
14µm square pixels with 100% fill factor
Ultra low image lag
Electronic exposure and antiblooming
controls
Note: While the P-Series imagers have been
designed to resist electrostatic discharge
(ESD), they can be damaged from such dis-
charges. Always observe proper ESD precau-
tions when handling and storing this imager.
DATASHEET
Imaging
CCD
DSP-101 01I - 8/2004W Page 1
Description (cont.)
P-series imagers combine high-performance
photodiodes with high speed CCD readout
registers and a high-sensitivity readout
amplifier. Refer to Figure 1 for construction
details.
Light Detection Area
The light detection area in P-series imagers is
a linear array of contiguous pinned photo-
diodes on 14 µm centers. These photodiodes
are constructed using PerkinElmer's advanced
photodiode design that extends short-wave-
length sensitivity into the deep UV below 250
nm, while preserving 100% fill factor and de-
livering extremely low image lag. This unique
design also avoids polysilicon layers in the
light detection area that reduces the quantum
efficiency of most CCD imagers. The P-
series imagers are supplied with glass windows
for general visible use, or fused silica windows
for use in the UV below 250nm. On a custom
basis, P-series imagers can be supplied with-
out an affixed window. See Figures 2a and 2b
for sensitivity and window transmission curves.
For lowest lag, all P-series imagers feature
pinned photodiodes. Pinning, which requires
a special semiconductor process step, provides
a uniform internal voltage reference for the
charge stored in every photodiode. This stable
reference assures that every photodiode is
fully discharges after every scan.
Photodiodes covered with light sheilds included
at one or both ends of the imager provide a dark
current reference for clamping. These are sep-
arated from the active photodiodes by two un-
shielded transition pixels that assure uniform
response out to the last active photodiode.
Figure 2a. Spectral Sensitivity Curve
100
90
80
70
60
50
40
30
20
10
0
250 350 450 550 650 750 850 950 1050
100
90
80
70
60
50
40
30
20
10
0
Wavelength (nm)
Responsivity (V/mJ/cm )
2
QE (%)
QE (right scale)
Responsivity (Left Scale)
Figure 2b. Window Transmission Curve
Wavelength (nm)
Transmission (%)
100
90
80
70
60
50
40
30
20
10
0
150 450
350250 550 950
850
750
650 1050
Fused Silica
Glass
Linear Photodiode Array
Imagers
www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 2
Figure 1. Imager Functional Diagram
{
Output
Amp
2-Phase Buried Channel CCD Shift Register
Transfer Gate
Antiblooming/Exposure Control Gate
D1 . . . . . . . . . . . . . . . . . . . .D10 T1 T2 1 23. . . . . . . . . D11 . . . . . . . . . . . . . . . . . . . .D20
NT3 T4
N-1
N = 512 for the RL0512
N = 1024 for the RL1024P
N = 2048 for the RL2048P
3
10
2
N
2
10
Isolation stages
Dark pixels (D1...D10)
Transition pixels (T1, T2)
(Light shield ends between D10 and T1)
Active Pixels (1...N)
Transition pixels (T3, T4)
(Light shield ends between T4 and D11)
Dark pixels (D11...D20) (not used in RL0512)
3 CCD Isolation Stages
Figure 4. Readout Timing Waveforms
ØRG
t1t2
t6
t4t5
Ø2
Ø1
Linear Photodiode Array
Imagers
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Light Detection Area (cont)
Due to the potential for light leakage, the two
dark pixels nearest the transition pixels should
not be used as a dark reference.
Horizontal Shift Registers
Charge packets collected in the photodiodes
as light is received are converted to a serialized
output stream through a buried channel, two-
phase CCD shift register that provides high
charge transfer efficiency at shift frequencies
up to 40 MHz. The PerkinElmer 5-volt CCD
process used in this design enables low-power,
high-speed operation with inexpensive, readily-
available driver devices.
The transfer gate (ØTG) controls the movement
of charge packets from the photodiodes to the
CCD shift register. During charge integration,
the voltage controlling the ØTG is held in its
low state to isolate the photodiodes from the
shift register. When transfer of charge to the
shift register is desired, ØTG is switched to its
high state to create a transfer channel between
the photodiodes and the shift register. The
charge transfer sequence, detailed in Figure 4,
proceeds as follows:
After readout of a particular image line (n), the
shift register is empty of charge and ready to
accept new charge packets from the photo-
diode representing image line n+1. To begin
the transfer sequence, the horizontal clock
pulses (ØH1 and ØH2) are stopped with ØH1
held in its high state, and ØH2 in its low state.
ØTG is then switched high to start the transfer
of charge to the shift register. Once the ØTG
reaches its high state, the photo gate voltage
PG) is set to high to complete the transfer.
It is recommended that the photo gate voltage
be held in the high state for at least 0.1 µs to
ensure complete transfer. After this interval,
the photo gate voltage is returned to its low
state, and when this is completed, the transfer
gate is also returned to its low state. The
details of the transfer timing are shown in
Figure 3 with ranges and tolerances in Table 1.
After transfer, the charge is transported along
the shift register by the alternate action of two
horizontal phase voltages ØH1 and ØH2. While
the two-phase CCD shift register architecture
allows relaxed timing tolerances over those
required in three or four-phase, optimum charge
transfer efficiency (CTE) and lowest power
dissipation is obtained when the overlap of the
two-phase CCD clocks occurs around the 50%
transition level. Additionally, the phase diff-
erence between signals ØH1 and ØH2 should
be maintained near 180o and the duty cycle
should be set near to 50% to prevent loss of
full well charge storage capacity and charge
transfer efficiency.
.
DSP-101 01I - 8/2004W Page 3
Notes:
1. Transition and dark pixels
2. Active Pixels
Figure 3. Transfer Timing Diagram
Ø
TG
Ø
1
V
Out
t
2
t
3
t
5
t
6
Note 1 Note 2
t
6
Ø
PG
t
1
t
7
Ø
AB
t
4
t
8
Item Sym Min Typ Max
Delay of ØTG falling edge from
ØPG falling edge
t15 ns 20 ns -
Delay of ØTG rising edge from
end of ØH1 and ØH2 clocks t20 ns 10 ns -
Delay of ØAB rising edge from
ØPG falling edge t35 ns 5 ns -
ØTG pulse width t4100 ns 500 ns -
ØPG pulse width t5100 ns 400 ns -
Rise/fall time t610 ns 20 ns -
Integration time t70 ns --
ØAB pulse width t8750 ns1
--
Table 1. Transfer Timing Requirements
Note 1: 750ns is the typical time to fully reset the photodiode
Readout timing details are shown in Figure
4 with ranges and tolerances in Table 2.
Timing Requirements
In high-speed applications, fast waveform
transitions allow maximum settling time of
the output signal. However, it is generally
advisable to use the slowest rise and fall
times consistent with required video per-
formance because fast edges tend to intro-
duce more transition noise into the video
waveform. When the highest speeds are
required, careful smoothing of the waveform
transitions may improve the balance be-
tween speed and video quality.
Output Amplifier
Charge emerging from the last stage of the
shift register is converted to a voltage signal
by a charge integrator and video amplifier.
The integrator, a capacitor created by a
floating diffusion, is initially set to a DC ref-
erence voltage (VRD) by setting the reset
transistor voltage (ØRG) to its high state. To
read out the charge, ØRG is pulsed low turning
the reset transistor off and isolating the inte-
grator from VRD. The next time ØH1 goes low,
the charge packet is transferred to the inte-
grator, where it generates a voltage propor-
tional to the packet size. The reset transistor
voltage, ØRG, must reach its low state prior
to the high-to-low transition of ØH1. An
apparent clipping of the video signal will result
if this condition is not satisfied. Figure 4
details the clock waveform requirements
and overlap tolerances.
The video amplifier buffers the signal from the
integrator for output from the imager. Care
must be taken to keep the load on this
amplifier within its ability to drive highly reactive
or low impedance loads. The half power
bandwidth into an external load of 10 pF is
150 MHz. It is recommended that the output
video signal be buffered with a wide bandwidth
follower or other appropriate amplifier to
provide a large Zin to the output amplifier.
Keep the external amplifier close to the output
pins to minimize stray inductive and capacitive
coupling of the output signal that can harm
signal quality.
Item Sym Min Typ Max
ØH1, ØH2 clock period t125 ns - -
ØH1, ØH2 rise/fall time t2- 5 ns -
ØRG rise/fall time t4- 5 ns -
ØRG clock - high duration t55 ns - -
Delay of ØH1 high -low
transition from ØRG low
t60 ns - -
Table 2. Readout Timing Requirements
Pixel count 512 elements (RL0512P)
1024 elements (RL1024P)
2048 elements (RL2048P)
Pixel size 14 µm x 14 µm
Exposure control yes
Horizontal clocking 2Ø (5V clock amplitude)
Number of outputs 1
Dynamic range
1>2500:1
Readout noise (rms)
amplifier 18 electrons
reset transistor 45 electrons
total noise without CDS 50 electrons
Saturation exposure 227 nJ/cm2
Noise equivalent exposure 8.1 pJ/cm2
Amplifier sensitivity 6.6 µV/electron
Saturation output voltage 1100 mV
Saturation charge capacity 167,000 electrons
Charge Transfer Efficiency >0.99995
Peak responsivity 41V/µJ/cm2
PRNU ±5%
Dead pixels 0
Lag 1.5%
Spectral Response Range 200 nm to 1000 nm
Data Range 40 MHz
Table 3. Imager Performance (typical)
Linear Photodiode Array
Imagers
www.perkinelmer.com/ccd
Notes:
1. Defined as Qsat/rms noise (total)
2. For illumination at 750 nm
Note: The cross over point for ØH1 and ØH2 clock transitions should occur within the 10 - 90% level of the
clock amplitude.
Horizontal Shift Registers (cont.)
DSP-101 01I - 8/2004W Page 4
An exposure control feature in the P-series
imagers supports variable charge accumula-
tion time in the photodiode. When the anti-
blooming gate voltage (ØAB) is set to its high
state, charge is drained from the pixel storage
gate to the exposure control drain. During
normal charge collection in the photodiode,
ØAB is set to its low state. Due to the timing
requirements of the exposure control mode,
charge is always accumulated at the end of
the period just before the charge is trans-
ferred to the readout register. Figure 3 in-
cludes the timing requirements for exposure
control with the antiblooming gate. The
exposure control timing shown will act on the
charge packets that emerge as video data on
the next readout cycle.
Imager Performance
In P-series imagers each element performs
its own function admirably while integrating
smoothly with the other elements on the
team. The photodiodes efficiently transform
light to charge, the readout registers accu-
rately transport the charge to the amplifier,
and the amplifier delivers a clean, robust
signal for use in image processing electronics.
While the actual performance of these imagers
depends strongly on the details of the elect-
ronics and timing the camera provides, their
straight-forward implementation requirements
facilitate optimum designs.
Operating Conditions
For optimum performance and longest life,
carefully follow the operational requirements
of these imagers. Provide stable voltage
sources free of noise and variation, and
clean waveforms with controlled edges.
Protect the imager from electrostatic discharge
(ESD) and excessive voltages and temper-
atures. Do not violate the limits on output
register speed or reduce timing margins below
the minimums.
Imager Configuration
All P-series imagers are constructed using
ceramic packages and optically-flat windows.
Imager die are secured to precision lead frames
by thermal silver-filled epoxy. Packages are
baked before sealing to eliminate moisture,
and tested for seal integrity.
Signal Function State Voltage Tolerance
ØH1, ØH2 Horizontal Clocks High 5 +5%
Low 0
ØTG Transfer Gate High 8 ±10%
Low 0
ØPG Photo Gate High 8
Low -4
+5%
+5%
ØAB Antiblooming Gate High 4
±5%
±5%
Low -4
VOG Output Gate 3 ±5%
ØRG Reset Gate High 8 ±10%
Low 0
VDD Amplifier Voltage Supply 12 ±5%
VRD Amplifier Reset Drain 9.5 ±5%
VSS / LS Amplifier Return/Light Shield 0
Table 4. Operating Voltages
Min Max Unit
Temperature
Storage -25 +85 ° C
Operating -25 +55 ° C
Voltage (with respect to GND)
Pins 3, 4, 17- 19 -0.3 +18 V
Pins 2, 10, 20 -0.3 +18 V
Pins 1, 11 -0.3 + 0 V
Pins 15, 16 -4.3 +18 V
Table 5. Absolute Maximum Ratings (Above Which Useful Life May Be Impaired)
Linear Photodiode Diode
Arrays
www.perkinelmer.com/ccd
Exposure Control and Antiblooming
Precautionary Note: The CCD output pin (pin #2) must never be shorted to either Vss or VDD
while power is applied to the device. Catastrophic device failure will result!
DSP-101 01I - 8/2004W Page 5
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Capacitance (pF) (typ)
Pin Sym Function Pixels 2048 1024 512
Amplifier return 50 30 20
Signal output 75 45 30
3ØH2 CCD horizontal phase 2 320 150 70
4
1
2
ØH1
VSS
VOut
CCD horizontal phase 1 350 190 90
5N/C No connection
6N/C No connection
7N/C No connection
8N/C No connection
9N/C No connection
10 VDD Amplifier drain supply
11 LS Light shield
12 N/C No connection
13 N/C No connection
14 N/C No connection
15 ØAB Antiblooming gate 70 35 20
16 ØPG Photo gate 100 50 25
17 ØTG Transfer gate 90 50 25
18 VOG Output gate 8 8 8
19 ØRG Reset gate 7 2 2
20 VRD Reset drain
Table 6. Pinout Description and Capacitance Values
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
V
SS
V
Out
N/C
N/C
N/C
V
RD
Ø
PG
Ø
AB
N/C
N/C
N/C
LS
V
DD
Ø
RG
N/C
Ø
H2
Ø
H1
V
OG
Ø
TG
Figure 5. Pinout Configuration
Linear Photodiode Array
Imagers
DSP-101 01I - 8/2004W Page 6
Figure 6. Outline Drawings
A
B
0.300
(7.62)
Pixel 1
Sensing Area 14 mm
(at stand off)
0.395 ± 0.008
(10.03 ± 0.20)
0.100 ± 0.005
(2.54 ± 0.13)
0.900 ± 0.005
(22.86 ± 0.13)
0.018 ± 0.002
(0.46 ± 0.05)
0.080 ± 0.009
(2.032 ± 0.23)
0.020 ± 0.002
(0.508 ± 0.05)
0.020 ± 0.002
(0.508 ± 0.05)
0.400 ± 0.010
(10.16 ± 0.25)
0.170
(4.32)
0.020 ± 0.002
(0.50 ± 0.05)
0.205 ± 0.0075
(5.21 ± 0.19)
0.450 ± 0.0075
(11.43 ± 0.19)
* Measurements in inches (millimeters)
* Maximum angular error is ±15 milliradians
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Linear Photodiode Array
Imagers
Device Inches mm Inches mm
RL0512P 0.284 7.224 1.500 ±0.15 38.1 ± 0.381
RL1024P 0.566 14.392 1.500 ±0.15 38.1 ± 0.381
RL2048P 1.131 28.728 1.500 ±0.15 38.1 ± 0.381
Notes: Includes active and transition pixels
Table 7. Package Dimensions and Tolerances
Active Pixels
Window 512 1024 2048
Glass RL0512PAG-021 RL1024PAG-021 RL2048PAG-021
Fused Silica RL0512PAQ-021 RL1024PAQ-021 RL2048PAQ-021
Table 8. Stock Part Numbers
Ordering Information
The RL0512P, RL1024P, and RL2048P
are available with either glass or fused
silica windows. On special orders,
PerkinElmer can supply anti-reflectance
coated windows or windowless packages.
Imagers are packed in electrostatic-
resistant bozes and identified by lot
numbers for tracking.
DSP-101 01I - 8/2004W Page 7
AB
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For more information, email us at
ccd@perkinelmer.com, or visit our
website at www.perkinelmer.com/ccd
All values are nominal; specifications
are subject to change without notice.
© 2004. PerkinElmer Inc. All rights reserved. PerkinElmer, the PerkinElmer logo and stylied 'P' are trademarks of PerkinElmer Inc. DSP-101.01I- 8/2004W
Linear Photodiode Arrays
Imagers
Page 8
Table 9. Sales Offices
United States PerkinElmer Optoelectronics
2175 Mission College Blvd
Santa Clara, CA 95054
Toll Free: 800-775-OPTO (6786)
Phone: +1-408-565-0830
Fax: +1-408-565-0703
Europe PerkinElmer Optoelectronics GmbH
Wenzel-Jaksch-Str. 31
D65199 Wiesbaden, Germany
Phone: +49-611-492-570
Fax: +49-611-492-165
Japan PerkinElmer Japan Co. Ltd.
Yokohama Nishiguti KN Bldg.
2-8-4 Kitasaiwai, Nishi-ku
Yokohoama-shi, 220-0004 Japan
Phone: +81-45-314-9022
Fax: +81-45-314-9023
Singapore 47 Ayer Rajah Crescent #06-12
Singapore 139947
Phone: +65-770-4925
Fax: +65-777-1008