CCD P-Series Linear Photodiode Array Imagers 14m, single output, 512, 1024, 2048 elements Features Description In the P-series linear imager, PerkinElmer has combined the best features of high-sensitivity photodiode array detection and high-speed chargecoupled scanning to offer an uncompromising solution to the increasing demands of advanced imaging applications These high performance imagers feature low noise, high sensitivity, impressive charge storage capacity, and lag-free dynamic imaging in a convenient single-output architecture. The 14m square contiguous pixels in these imagers reproduce images with minimum information loss and artifact generation, while their unique photodiode structure provides excellent blue response extending below 250nm and into the ultraviolet. D A T A S H E E T Imaging The two-phase CCD readout register requires only 5 volts for clocking yet achieves excellent charge transfer efficiency. Additional electrodes provide independent control of exposure and antiblooming. Finally, the high-sensitivity readout amplifier provides a large output signal to relax noise requirements on the camera electronics that follow. Available in standard array lengths of 512, 1024, and 2048 elements with either glass or UV-enhanced fused silica windows, these versatile imagers are widely used in high-speed document reading, web inspection, mail sorting, production measurement and gauging, position sensing, spectroscopy, and other industrial and scientific applications requiring peak imager performance. * Extended spectral range--200 to 1000 nm * 40 MHz pixel readout rate with line rates to 70 kHz * >2500:1 dynamic range * 5-volt clocking * 14m square pixels with 100% fill factor * Ultra low image lag * Electronic exposure and antiblooming controls Note: While the P-Series imagers have been designed to resist electrostatic discharge (ESD), they can be damaged from such discharges. Always observe proper ESD precautions when handling and storing this imager. www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 1 Linear Photodiode Array Imagers Description (cont.) P-series imagers combine high-performance photodiodes with high speed CCD readout registers and a high-sensitivity readout amplifier. Refer to Figure 1 for construction details. Figure 2a. Spectral Sensitivity Curve 100 100 90 90 Responsivity (V/mJ/cm 2 ) The light detection area in P-series imagers is a linear array of contiguous pinned photodiodes on 14 m centers. These photodiodes are constructed using PerkinElmer's advanced photodiode design that extends short-wavelength sensitivity into the deep UV below 250 nm, while preserving 100% fill factor and delivering extremely low image lag. This unique design also avoids polysilicon layers in the light detection area that reduces the quantum efficiency of most CCD imagers. The Pseries imagers are supplied with glass windows for general visible use, or fused silica windows for use in the UV below 250nm. On a custom basis, P-series imagers can be supplied without an affixed window. See Figures 2a and 2b for sensitivity and window transmission curves. 80 QE (right scale) 70 70 60 60 50 50 40 40 30 30 20 QE (%) 80 Light Detection Area 20 Responsivity (Left Scale) 10 10 0 0 250 350 450 650 550 750 950 850 1050 Wavelength (nm) Figure 2b. Window Transmission Curve 100 Fused Silica 90 80 Transmission (%) For lowest lag, all P-series imagers feature pinned photodiodes. Pinning, which requires a special semiconductor process step, provides a uniform internal voltage reference for the charge stored in every photodiode. This stable reference assures that every photodiode is fully discharges after every scan. Photodiodes covered with light sheilds included at one or both ends of the imager provide a dark current reference for clamping. These are separated from the active photodiodes by two unshielded transition pixels that assure uniform response out to the last active photodiode. 70 60 50 Glass 40 30 20 10 0 150 250 350 450 550 650 750 850 950 1050 Wavelength (nm) Figure 1. Imager Functional Diagram N = 512 for the RL0512 N = 1024 for the RL1024P N = 2048 for the RL2048P 3 10 2 N 2 10 Antiblooming/Exposure Control Gate Isolation stages Dark pixels (D1...D10) Transition pixels (T1, T2) D1 . . . . . . . . . . . . . . . . . . . .D10 T1 T2 1 2 3 . . . . . . . . . (Light shield ends between D10 and T1) Active Pixels (1...N) Transition pixels (T3, T4) (Light shield ends between T4 and D11) Dark pixels (D11...D20) (not used in RL0512) Transfer Gate N-1 N T3 T4 D11 . . . . . . . . . . . . . . . . . . . .D20 Output 2-Phase Buried Channel CCD Shift Register { Amp 3 CCD Isolation Stages www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 2 Linear Photodiode Array Imagers Figure 3. Transfer Timing Diagram Light Detection Area (cont) t6 t1 Due to the potential for light leakage, the two dark pixels nearest the transition pixels should not be used as a dark reference. OPG t5 t3 t2 Horizontal Shift Registers OTG Charge packets collected in the photodiodes as light is received are converted to a serialized output stream through a buried channel, twophase CCD shift register that provides high charge transfer efficiency at shift frequencies up to 40 MHz. The PerkinElmer 5-volt CCD process used in this design enables low-power, high-speed operation with inexpensive, readilyavailable driver devices. . The transfer gate (OTG) controls the movement of charge packets from the photodiodes to the CCD shift register. During charge integration, the voltage controlling the OTG is held in its low state to isolate the photodiodes from the shift register. When transfer of charge to the shift register is desired, OTG is switched to its high state to create a transfer channel between the photodiodes and the shift register. The charge transfer sequence, detailed in Figure 4, proceeds as follows: After readout of a particular image line (n), the shift register is empty of charge and ready to accept new charge packets from the photodiode representing image line n+1. To begin the transfer sequence, the horizontal clock pulses (OH1 and OH2) are stopped with OH1 held in its high state, and OH2 in its low state. OTG is then switched high to start the transfer of charge to the shift register. Once the OTG reaches its high state, the photo gate voltage (OPG) is set to high to complete the transfer. It is recommended that the photo gate voltage be held in the high state for at least 0.1 s to ensure complete transfer. After this interval, the photo gate voltage is returned to its low state, and when this is completed, the transfer gate is also returned to its low state. The details of the transfer timing are shown in Figure 3 with ranges and tolerances in Table 1. t6 t4 t8 OAB t7 O1 VOut Note 1 Note 2 Notes: 1. Transition and dark pixels 2. Active Pixels Table 1. Transfer Timing Requirements Item Sym Min Typ Max Delay of OTG falling edge from OPG falling edge t1 5 ns 20 ns - Delay of OTG rising edge from end of OH1 and OH2 clocks t2 0 ns 10 ns - Delay of OAB rising edge from OPG falling edge t3 5 ns 5 ns - OTG pulse width t4 100 ns 500 ns - OPG pulse width t5 100 ns 400 ns - Rise/fall time t6 10 ns 20 ns - Integration time t7 0 ns - - OAB pulse width t8 - 750 ns 1 - Note 1: 750ns is the typical time to fully reset the photodiode After transfer, the charge is transported along the shift register by the alternate action of two horizontal phase voltages OH1 and OH2. While the two-phase CCD shift register architecture allows relaxed timing tolerances over those required in three or four-phase, optimum charge transfer efficiency (CTE) and lowest power dissipation is obtained when the overlap of the two-phase CCD clocks occurs around the 50% transition level. Additionally, the phase difference between signals OH1 and OH2 should be maintained near 180o and the duty cycle should be set near to 50% to prevent loss of full well charge storage capacity and charge transfer efficiency. Figure 4. Readout Timing Waveforms t1 t2 O1 O2 t6 t4 t5 ORG www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 3 Linear Photodiode Array Imagers Horizontal Shift Registers (cont.) Table 2. Readout Timing Requirements Readout timing details are shown in Figure 4 with ranges and tolerances in Table 2. Item Timing Requirements In high-speed applications, fast waveform transitions allow maximum settling time of the output signal. However, it is generally advisable to use the slowest rise and fall times consistent with required video performance because fast edges tend to introduce more transition noise into the video waveform. When the highest speeds are required, careful smoothing of the waveform transitions may improve the balance between speed and video quality. Sym Min Typ Max t1 t2 t4 t5 t6 25 ns 5 ns 0 ns 5 ns 5 ns - - OH1, OH2 clock period OH1, OH2 rise/fall time ORG rise/fall time ORG clock - high duration Delay of OH1 high -low transition from ORG low Note: The cross over point for OH1 and OH2 clock transitions should occur within the 10 - 90% level of the clock amplitude. Table 3. Imager Performance (typical) Pixel count Output Amplifier Charge emerging from the last stage of the shift register is converted to a voltage signal by a charge integrator and video amplifier. The integrator, a capacitor created by a floating diffusion, is initially set to a DC reference voltage (VRD) by setting the reset transistor voltage (ORG) to its high state. To read out the charge, ORG is pulsed low turning the reset transistor off and isolating the integrator from VRD. The next time OH1 goes low, the charge packet is transferred to the integrator, where it generates a voltage proportional to the packet size. The reset transistor voltage, ORG, must reach its low state prior to the high-to-low transition of OH1. An apparent clipping of the video signal will result if this condition is not satisfied. Figure 4 details the clock waveform requirements and overlap tolerances. The video amplifier buffers the signal from the integrator for output from the imager. Care must be taken to keep the load on this amplifier within its ability to drive highly reactive or low impedance loads. The half power bandwidth into an external load of 10 pF is 150 MHz. It is recommended that the output video signal be buffered with a wide bandwidth follower or other appropriate amplifier to provide a large Zin to the output amplifier. Keep the external amplifier close to the output pins to minimize stray inductive and capacitive coupling of the output signal that can harm signal quality. 512 elements (RL0512P) 1024 elements (RL1024P) 2048 elements (RL2048P) Pixel size 14 m x 14 m Exposure control yes Horizontal clocking 2O (5V clock amplitude) Number of outputs 1 Dynamic range >2500:1 1 Readout noise (rms) amplifier 18 electrons reset transistor 45 electrons total noise without CDS 50 electrons Saturation exposure 2 27 nJ/cm2 Noise equivalent exposure 8.1 pJ/cm2 Amplifier sensitivity 6.6 V/electron Saturation output voltage 1100 mV Saturation charge capacity 167,000 electrons Charge Transfer Efficiency >0.99995 Peak responsivity 41V/J/cm2 PRNU 5% Dead pixels 0 Lag 1.5% Spectral Response Range 200 nm to 1000 nm Data Range 40 MHz Notes: 1. Defined as Qsat/rms noise (total) 2. For illumination at 750 nm www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 4 Linear Photodiode Diode Arrays Exposure Control and Antiblooming Table 4. Operating Voltages An exposure control feature in the P-series imagers supports variable charge accumulation time in the photodiode. When the antiblooming gate voltage (OAB) is set to its high state, charge is drained from the pixel storage gate to the exposure control drain. During normal charge collection in the photodiode, OAB is set to its low state. Due to the timing requirements of the exposure control mode, charge is always accumulated at the end of the period just before the charge is transferred to the readout register. Figure 3 includes the timing requirements for exposure control with the antiblooming gate. The exposure control timing shown will act on the charge packets that emerge as video data on the next readout cycle. Imager Performance In P-series imagers each element performs its own function admirably while integrating smoothly with the other elements on the team. The photodiodes efficiently transform light to charge, the readout registers accurately transport the charge to the amplifier, and the amplifier delivers a clean, robust signal for use in image processing electronics. While the actual performance of these imagers depends strongly on the details of the electronics and timing the camera provides, their straight-forward implementation requirements facilitate optimum designs. Operating Conditions For optimum performance and longest life, carefully follow the operational requirements of these imagers. Provide stable voltage sources free of noise and variation, and clean waveforms with controlled edges. Protect the imager from electrostatic discharge (ESD) and excessive voltages and temperatures. Do not violate the limits on output register speed or reduce timing margins below the minimums. Signal Function OH1, OH2 Horizontal Clocks State High Low Voltage 5 0 Tolerance +5% OTG Transfer Gate High Low 8 0 10% OPG Photo Gate High Low 8 -4 +5% 5% OAB Antiblooming Gate High Low 4 -4 +5% 5% VOG Output Gate 3 5% ORG Reset Gate 8 0 10% VDD Amplifier Voltage Supply 12 5% VRD Amplifier Reset Drain 9.5 5% VSS / LS High Low Amplifier Return/Light Shield 0 Table 5. Absolute Maximum Ratings (Above Which Useful Life May Be Impaired) Min Max Unit Temperature Storage Operating -25 -25 +85 +55 C C Voltage (with respect to GND) Pins 3, 4, 17- 19 Pins 2, 10, 20 Pins 1, 11 Pins 15, 16 -0.3 -0.3 -0.3 -4.3 +18 +18 +0 +18 V V V V Precautionary Note: The CCD output pin (pin #2) must never be shorted to either Vss or VDD while power is applied to the device. Catastrophic device failure will result! Imager Configuration All P-series imagers are constructed using ceramic packages and optically-flat windows. Imager die are secured to precision lead frames by thermal silver-filled epoxy. Packages are baked before sealing to eliminate moisture, and tested for seal integrity. www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 5 Linear Photodiode Array Imagers Table 6. Pinout Description and Capacitance Values Capacitance (pF) (typ) Pin 1 Sym VSS Function Amplifier return 2 VOut Signal output Pixels 2048 50 1024 30 512 20 75 45 30 3 OH2 CCD horizontal phase 2 320 150 70 4 OH1 CCD horizontal phase 1 350 190 90 5 N/C No connection 6 N/C No connection 7 N/C No connection 8 N/C No connection 9 N/C No connection 10 VDD Amplifier drain supply 70 35 20 11 LS Light shield 12 N/C No connection 13 N/C No connection 14 N/C No connection 15 OAB Antiblooming gate 16 OPG Photo gate 17 OTG Transfer gate 18 VOG 19 ORG 20 VRD Reset drain 100 50 25 90 50 25 Output gate 8 8 8 Reset gate 7 2 2 Figure 5. Pinout Configuration VSS 1 20 VRD VOut 2 19 O RG OH2 3 18 VOG OH1 4 17 O TG N/C 5 16 O PG N/C 6 15 O AB N/C 7 14 N/C N/C 8 13 N/C N/C 9 12 N/C VDD 10 11 LS www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 6 Linear Photodiode Array Imagers Figure 6. Outline Drawings * Measurements in inches (millimeters) A Pixel 1 * Maximum angular error is 15 milliradians 0.205 0.0075 (5.21 0.19) * Sensing Area 14mm 0.395 0.008 (10.03 0.20) 0.020 0.002 (0.508 0.05) 0.020 0.002 (0.508 0.05) 0.450 0.0075 (11.43 0.19) 0.080 0.009 (2.032 0.23) 0.020 0.002 (0.50 0.05) B 0.300 0.018 0.002 (7.62) (0.46 0.05) 0.100 0.005 (2.54 0.13) Ordering Information The RL0512P, RL1024P, and RL2048P are available with either glass or fused silica windows. On special orders, PerkinElmer can supply anti-reflectance coated windows or windowless packages. Imagers are packed in electrostaticresistant bozes and identified by lot numbers for tracking. 0.400 0.010 (10.16 0.25) 0.170 (4.32) 0.900 0.005 (22.86 0.13) (at stand off) Table 7. Package Dimensions and Tolerances A Device RL0512P RL1024P RL2048P Inches 0.284 0.566 1.131 B mm 7.224 14.392 28.728 Inches 1.500 0.15 1.500 0.15 1.500 0.15 mm 38.1 0.381 38.1 0.381 38.1 0.381 Notes: Includes active and transition pixels Table 8. Stock Part Numbers Active Pixels Window Glass Fused Silica 512 1024 2048 RL0512PAG-021 RL0512PAQ-021 RL1024PAG-021 RL1024PAQ-021 RL2048PAG-021 RL2048PAQ-021 www.perkinelmer.com/ccd DSP-101 01I - 8/2004W Page 7 Linear Photodiode Arrays Imagers Table 9. Sales Offices For more information, email us at ccd@perkinelmer.com, or visit our website at www.perkinelmer.com/ccd United States PerkinElmer Optoelectronics 2175 Mission College Blvd Santa Clara, CA 95054 Toll Free: 800-775-OPTO (6786) Phone: +1-408-565-0830 Fax: +1-408-565-0703 Europe PerkinElmer Optoelectronics GmbH Wenzel-Jaksch-Str. 31 D65199 Wiesbaden, Germany Phone: +49-611-492-570 Fax: +49-611-492-165 Japan PerkinElmer Japan Co. Ltd. Yokohama Nishiguti KN Bldg. 2-8-4 Kitasaiwai, Nishi-ku Yokohoama-shi, 220-0004 Japan Phone: +81-45-314-9022 Fax: +81-45-314-9023 Singapore 47 Ayer Rajah Crescent #06-12 Singapore 139947 Phone: +65-770-4925 Fax: +65-777-1008 All values are nominal; specifications are subject to change without notice. (c) 2004. PerkinElmer Inc. All rights reserved. PerkinElmer, the PerkinElmer logo and stylied 'P' are trademarks of PerkinElmer Inc. www.perkinelmer.com/ccd DSP-101.01I- 8/2004W Page 8