DATASHEET ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER Description Features The ICS672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90 intervals. Based on IDT's proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The ICS672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin. * Packaged in 16-pin SOIC * Available in Pb (lead) free package * Input clock range from 5 MHz to 150 MHz (depends on multiplier) * Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02) * Zero input-output delay * Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections * Four accurate (<250 ps) outputs with 0, 90, 180, and 270 phase shift from ICLK, and one FBCLK (0) * * * * * * * IDT manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world. Separate supply for output clocks from 2.5 V to 5 V Full CMOS outputs (TTL compatible) Tri-state mode for board-level testing Includes Power-down for power savings Advanced, low power, sub-micron CMOS process 3.3 V to 5 V operating voltage Industrial temperature version available NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram VDD GND 2 3 VDDIO IN CLK0 PLL Multiplier and Quadrature Generation FBIN CLK90 CLK180 CLK270 CLKFB S2:S0 3 Control Logic Power Down plus Tri-state External Feedback IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER 1 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Pin Assignment Output Clock Mode Select Table ICLK 1 16 FBIN CLK90 2 15 CLK180 3 CLK270 S2 S1 S0 Output Clocks FBCLK 0 0 0 Power-down + tri-state 14 CLK0 0 0 1 x1 4 13 VDD 0 1 0 x2 VDDIO 5 12 GND 0 1 1 x3 GND 6 11 1 0 0 x4 VDD 1 0 1 x5 GND 7 10 S2 1 1 0 x6 S0 8 9 S1 1 1 1 x0.5 Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 ICLK Input 2 CLK90 Output Clock output (90 delayed from CLK0). 3 CLK180 Output Clock output (180 delayed from CLK0). 4 CLK270 Output Clock output (270 delayed from CLK0). 5 VDDIO Power Supply voltage for input and output clocks. Must not exceed VDD. 6, 7, 12 GND Power Connect to ground. 8 S0 Input Select input 0. See table above. 9 S1 Input Select input 1. See table above. 10 S2 Input Select input 2. See table above. 11, 13 VDD Power Connect to 3.3 V or 5.0 V. 14 CLK0 Output Clock output phase aligned to ICLK. 15 FBCLK 16 FBIN Clock input. Output Feedback clock output (0 phase shift from CLK0). Input Feedback clock input. in normal operation, connect to FBCLK. IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER 2 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER External Components The ICS672-01/02 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 11 and 12, and VDD and GND on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series termination resistor of 33 may be used close to each clock output pin to reduce reflections. Operation and Applications The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock (ICLK). Phase shifts of 0 (CLK0), 90 (CLK90), 180 (CLK180), and 270 (CLK270) are provided, plus one feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by the table on page 2. Refer to the illustrations in Figure 1 and Figure 2. FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02. FBCLK has a 0 phase shift from ICLK. ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 1. Phase alignment of input and output clocks (x1 multiplier) ICLK CLK0, FBCLK CLK90 CLK180 CLK270 Figure 2. Phase alignment of input and output clocks (x2 multiplier) IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER 3 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS672-01/02. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD -0.5 V to 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Electrostatic Discharge (MIL-STD-883) 2000 V Ambient Operating Temperature (commercial) 0 to +70 C Ambient Operating Temperature (industrial, -02 only) -40 to +85 C Storage Temperature -65 to +150 C Junction Temperature 150 C Soldering Temperature 260 C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 C +3.13 +5.5 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD = VDDIO = 3.3 V, Ambient temperature 0 to +70 C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.13 5.50 V Operating Voltage VDDIO 2.375 VDD V Input High Voltage VIH ICLK only Input Low Voltage VIL ICLK only Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage, CMOS level VOH IOH = -8 mA Operating Supply Current IDD No Load, S1=1, S0=0, S2=0, Note 1 VDDIO/2+0.5 V VDDIO/2-0.5 2 V 0.8 IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER 2.4 V V 0.4 VDDIO-0.4 4 V V V 11 mA ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER Parameter ZERO DELAY BUFFER Symbol Conditions IDD No Load, S1=1, S0=0, S2=0, Notes 2, 6 22 mA No Load, S1=1, S0=0, S2=0, Notes 2, 7 66 mA 50 mA 7 pF Operating Supply Current Short Circuit Current IOS Each output Input Capacitance CIN OE, select pins Min. Typ. Max. Units AC Electrical Characteristics VDD = VDDIO = 3.3 V, Ambient Temperature 0 to +70 C, unless stated otherwise Parameter Input Clock Frequency Symbol fIN Conditions Min. Typ. Max. Units Note 3 5 150 MHz Output Clock Frequency ICS672-01 15 84 MHz Output Clock Frequency ICS672-02 15 135 MHz Output Rise Time tOR 0.8 to 2.0 V, no load, CL = 15 pF 1.0 ns Output Fall Time tOF 2.0 to 0.8 V, no load, CL = 15 pF 1.0 ns Output Clock Duty Cycle, VDDIO = 3.3 V tDC At VDDIO/2 55 % 45 50 Phased Outputs Accuracy Rising edges at VDDIO/2, Note 4 -250 250 ps Input to Output Skew ICLK to CLK0, Note 5 -300 300 ps Maximum Absolute Jitter Cycle to Cycle Jitter 15 pF loads 75 ps 150 ps Note 1: With ICLK = 20 MHz, FBCLK to FBIN, all outputs at 40 MHz. Note 2: With ICLK = 66.5 MHz, FBCLK to FBIN, all outputs at 133 MHz. Note 3: Value depends on multiplier. Must also meet output clock frequency. Note 4: With CLK0CLK270 equally loaded, and output frequency > 60 MHz. Note 5: Rising edge of ICLK compared with rising edge of CLk0, with FBCLK connected to FBIN, 15 pF load on CLK0, and CLK0 > 60 MHz. Note 6: Commercial grade. Note 7: Industrial grade. Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Typ. Max. Units JA Still air 120 C/W JA 1 m/s air flow 115 C/W JA 3 m/s air flow 105 C/W 58 C/W JC IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER Min. 5 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E Min A A1 B C D E e H h L H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER C 6 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 672M-01* 672M-01T* 672M-01LF 672M-01LFT 672M-02* 672M-02T* 672M-02LF 672M-02LFT 672M-02I* 672M-02IT* 672M-02ILF 672M-02ILFT ICS672M-01 ICS672M-01 ICS672M-01LF ICS672M-01LF ICS672M-02 ICS672M-02 ICS672M-02LF ICS672M-02LF ICS672M-02I ICS672M-02I 672M-02ILF 672M-02ILF Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 "LF" denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM QUADRACLOCK QUADRATURE DELAY BUFFER 7 ICS672-01/02 REV J 110409 ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERO DELAY BUFFER Innovate with IDT and accelerate your future networks. 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