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FEATURES
DESCRIPTION/ORDERING INFORMATION
or Y =
A + B
in positive logic.
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
RGY PACKAGE
(TOP VIEW)
1 14
7 8
2
3
4
5
6
13
12
11
10
9
4B
4A
4Y
3B
3A
1B
1Y
2A
2B
2Y
1A
3Y V
GND
CC
A
BY
SN74ALVC08QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I JULY 1997 REVISED OCTOBER 2004
Operates From 1.65 V to 3.6 VMax t
pd
of 2.9 ns at 3.3 V ± 24-mA Output Drive at 3.3 VLatch-Up Performance Exceeds 250 mA PerJESD 17ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
This quadruple 2-input positive-AND gate is designedfor 1.65-V to 3.6-V V
CC
operation.
The device performs the Boolean function Y = A · B
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN - RGY Tape and reel SN74ALVC08RGYR VA08Tube SN74ALVC08DSOIC - D ALVC08Tape and reel SN74ALVC08DR-40 °C to 85 °C
SOP - NS Tape and reel SN74ALVC08NSR ALVC08TSSOP - PW Tape and reel SN74ALVC08PWR VA08TVSOP - DGV Tape and reel SN74ALVC08DGVR VA08
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE(each gate)
INPUTS
OUTPUT
YA B
HHHL X LX L L
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I JULY 1997 REVISED OCTOBER 2004
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 VV
I
Input voltage range
(2)
-0.5 4.6 VV
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 -50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mAD package
(4)
86DGV package
(4)
127θ
JA
Package thermal impedance NS package
(4)
76 °C/WPW package
(4)
113RGY package
(5)
47T
stg
Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.(5) The package thermal impedance is calculated in accordance with JESD 51-5.
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 VV
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 3.6 VV
O
Output voltage 0 V
CC
VV
CC
= 1.65 V -4V
CC
= 2.3 V -12I
OH
High-level output current mAV
CC
= 2.7 V -12V
CC
= 3 V -24V
CC
= 1.65 V 4V
CC
= 2.3 V 12I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24t/ v Input transition rise or fall rate 5 ns/VT
A
Operating free-air temperature -40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVC08QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I JULY 1997 REVISED OCTOBER 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2I
OH
= -4 mA 1.65 V 1.2I
OH
= -6 mA 2.3 V 2V
OH
2.3 V 1.7 VI
OH
= -12 mA 2.7 V 2.23 V 2.4I
OH
= -24 mA 3 V 2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45I
OL
= 6 mA 2.3 V 0.4V
OL
V2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
V
I
= V
CC
or GND 3.6 V ±5µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 10 µAI
CC
One input at V
CC
- 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µAC
i
V
I
= V
CC
or GND 3.3 V 4.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 VFROM TO
±0.15 V ±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B Y 1.2 5.3 1 3.2 3 1.2 2.9 ns
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
C
pd
Power dissipation capacitance per gate C
L
= 0, f = 10 MHz 24 25 26 pF
3
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PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH − V
0 V
VI
0 V
0 V
tw
VIVI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VMVM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VMVM
tPLH
VLOAD
VLOAD/2
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUT
SN74ALVC08
QUADRUPLE 2-INPUT POSITIVE-AND GATE
SCES101I JULY 1997 REVISED OCTOBER 2004
Figure 1. Load Circuit and Voltage Waveforms
4
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74ALVC08D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74ALVC08RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74ALVC08RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 1
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ALVC08 :
Automotive: SN74ALVC08-Q1
Enhanced Product: SN74ALVC08-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALVC08DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74ALVC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ALVC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74ALVC08NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74ALVC08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74ALVC08RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVC08DGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74ALVC08DR SOIC D 14 2500 333.2 345.9 28.6
SN74ALVC08DR SOIC D 14 2500 367.0 367.0 38.0
SN74ALVC08NSR SO NS 14 2000 367.0 367.0 38.0
SN74ALVC08PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74ALVC08RGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194