REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Update drawing to current requirements. Editorial changes throughout. - gap 02-05-22
Raymond Monnin
B
Boilerplate update, part of 5 year review. ksr 08-09-05
Robert M. Heber
REV
SHEET
REV B B B B B B B B B
SHEET 15 16 17 18 19 20 21 22 23
REV STATUS REV B B B B B B B B B B B B B B
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Kenneth Rice
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Jeff Bowling
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Raymond Monnin
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
97-07-03
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
ELECTRICALLY ALTERABLE FLASH PROGRAMMABLE
LOGIC DEVICE, MONOLITHIC SILICON
AMSC N/A
REVISION LEVEL
B SIZE
A CAGE CODE
67268
5962-97599
SHEET
1 OF
23
DSCC FORM 2233
APR 97 5962-E517-08
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 - 97599 01 Q X C
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function Toggle Speed (Mhz)
01 7C375i 128 Macrocell CPLD 66
02 7C375i 128 Macrocell CPLD 83
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class Device requirements documentation
M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-
JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
X CMGA7-P160 160 Pin grid array
Y See figure 1 160 Quad flat package (with ring)
Z See figure 1 160 Quad flat package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 3
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/
Supply voltage range (VCC) ............................................. -2.0 V dc to +7.0 V dc
Programming supply voltage range (VPP) ........................ -2.0 V dc to +13.5 V dc 2/
DC input voltage range .................................................... -2.0 V dc to +7.0 V dc 2/
Maximum power dissipation ............................................ 2.5 W 3/
Lead temperature (soldering, 10 seconds) ...................... +260°C
Thermal resistance, junction-to-case (θJC):
Case outline X ............................................................... See MIL-STD-1835
Case outline Y and Z ..................................................... 7.2° C/W
Junction temperature (TJ) ................................................ +175°C 4/
Storage temperature range ............................................. -65°C to +150°C
Endurance ..................................................................... 25 erase/write cycles (minimum)
Data retention .................................................................. 10 years (minimum)
1.4 Recommended operating conditions. 5/
Case operating temperature range (TC) .......................... -55°C to +125°C
Supply voltage relative to ground (VCC) ........................... +4.5 V dc minimum to +5.5 V dc maximum
Ground voltage (GND) .................................................... 0 V dc
Input high voltage (VIH) .................................................... 2.0 V dc minimum
Input low voltage (VIL) ...................................................... 0.8 V dc maximum
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation.
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78 - IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
_______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Minimum dc input voltage is -0.5 V, which may overshoot to -2.0 V for periods less than 20 ns. Maximum dc voltage on
output pins is VCC + 0.5 V, which may overshoot to +7.0 V for periods less than 20 ns under load conditions.
3/ Must withstand the added PD due to short circuit test (e.g., IOS).
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ All voltage values in this drawing are with respect to VSS.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 4
DSCC FORM 2234
APR 97
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that may affect this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 42 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Limits
Test
Symbol
Conditions
4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Min
Max
Unit
High Level output voltage
VOH
VCC = 4.5 V, VIL = 0.8V
IOH = -2.0 mA, VIH = 2.0 V
2.4
V
Low level output voltage
VOL
VCC = 4.5 V, IOL = 12.0 mA
VIL = 0.8 V, VIH = 2.0 V
0.5
V
High level input voltage 1/
VIH
2.0
7.0
V
Low level input voltage 1/
VIL
-0.5
0.8
V
Input leakage current
IIX
VCC = 5.5 V, VIN = 0 V
and 5.5 V
-10
+10
µA
Output leakage current
IOZ
VCC = 5.5 V, VIN = output
disabled and 5.5 V
-50
+50
µA
Output short circuit current 2/ 3/
IOS
VCC = 5.5 V, VOUT = 0.5 V
-30
-160
mA
Power supply current 4/
ICC
VCC = 5.5 V, IOUT = 0 mA,
VIN = 0 V and 5.5 V
f = 1.0 MHz
250
mA
Input bus hold low sustained
current
IBHL
VCC = 4.5 V,VIL = 0.8 V
+75
µA
Input bus hold high sustained
current
IBHH
VCC = 4.5 V,VIH = 2.0 V
-75
µA
Input bus hold low sustained
overdrive current
IBHLO
VCC = 5.5 V
+500
µA
Input bus hold high sustained
overdrive current
IBHLO
VCC = 5.5 V
1, 2, 3
All
-500
µA
Input capacitance 2/
CIN
See 4.4.1e 4
All
8
pF
Output capacitance 2/
COUT
See 4.4.1e 4
All
5
15
pF
Functional test
See 4.4.1c 7, 8A, 8B
All
01
20
Input to combinatorial output
5/
tPD
See figures 4 and 5
(circuit A)
9, 10, 11
02
15
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions
4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Min
Max
Unit
01
22
Input to output through
transparent input or output
latches 5/ 6/
tPDL
02
18
ns
01
24
Input to output through
transparent input or output
latches 5/ 6/
tPDLL
See figures 4 and 5
(circuit A)
02
19
ns
01
24
Input to output enable see figure
3 test waveforms 5/ 6/
tEA
See figures 4 and 5
(circuit B)
02
19
ns
01
24
Input to output disable see figure
3 test waveforms 5/ 6/
tER
02
19
ns
01
5
Clock or latch enable input high
time 2/ 5/
tWH
02
4
ns
01
5
Clock or latch enable input low
time 2/ 5/
tWL
02
4
ns
01
4
Input register or latch set-up
time 5/
tIS
02
3
ns
01
4
Input register or latch hold time
5/
tIH
02
3
ns
01
24
Input register clock or latch
enable to combinatorial output
5/
tICO
02
19
ns
01
26
Input register clock or latch
enable to output through
transparent output latch 5/ 6/
tICOL
02
21
ns
01
10
Clock or latch enable to output
5/
tCO
02
8
ns
Register or latch data
hold time 5/
tH
See figures 4 and 5
(circuit A)
9, 10, 11
All
0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Limits
Test
Symbol
Conditions
4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Min
Max
Unit
01
10
Set-up time from input to clock
or latch enable 5/
tS
02
8
ns
01
20
Set-up time from input through
transparent latch to output register
clock or latch enable 5/ 6/
tSL
02
15
ns
01
24
Output clock or latch enable to
output delay (through memory
array) 5/ 6/
tCO2
02
19
ns
01
15
Output clock or latch enable to
output clock or latch enable
(through memory array) 5/ 6/
tSCS
02
12
ns
Hold time for input through
transparent latch from output
register clock or latch enable
5/ 6/
tHL
All
0
ns
01
66
Maximum frequency with
internal feedback in output
register mode (least of 1/tSCS,
1/(tS + tH), or 1/tCO) 2/ 5/
fMAX1
See figures 4 and 5
(circuit A)
02
83
01
100
Maximum frequency data path in
output register/latched mode
(lesser of 1/(tWL + tWH), 1/(tS + tH),
or 1/tCO) 2/ 5/
fMAX2
02
125
01
50
Maximum frequency with
external feedback (lesser of
1/(tCO + tS),or 1/(tWL + tWH) 2/ 5/
fMAX3
02
62.5
01
66.6
Maximum frequency in pipelined
mode (least of 1/(tCO + tIS),
1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),or
1/tSCS 2/ 5/
fMAX4
9,10,11
02
83.3
MHz
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Limits
Unit
Test
Symbol
Conditions
4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
Subgroups
Device
type
Min
Max
Output data stable from output
clock minus input register hold
time for device 2/ 5/ 7/
tOH-tIH
All
0
ns
01
15
Input register clock to output
register clock 6/
tICS
02
12
ns
01
20
Asynchronous preset width
2/ 5/ 6/
tPW
02
15
ns
01
22
Asynchronous preset recovery
time 2/ 5/ 6/
tPR
02
17
ns
01
26
Asynchronous preset to output
5/ 6/
tPO
02
21
ns
01
20
Asynchronous reset width 5/ 6/
tRW
02
15
ns
01
22
Asynchronous reset recovery
time 5/ 6/
tRR
02
17
ns
01
26
Asynchronous reset to output
5/ 6/
tRO
02
21
ns
Top controller frequency
fTAP
See figures 4 and 5
(circuit A)
9, 10, 11
All
500
KHz
1/ These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2/ Tested initially and after any design or process changes that affect this parameter.
3/ Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
4/ Measured with 16-bit counter programmed into each logic block.
5/ All AC parameters are measured with 16 outputs switching.
6/ May not be tested but shall be guaranteed to the limits specified in table I.
7/ This specification is intended to guarantee interface compatibility with the other members of the device family, contact
manufacturer for additional information.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 9
DSCC FORM 2234
APR 97
Case Y
Figure 1. Case outline.
STANDARD
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DSCC FORM 2234
APR 97
Case Z
Figure 1. Case outline - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 11
DSCC FORM 2234
APR 97
Case outline X
Device
type
All
Device
type
All
Device
type
All
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
D1
D2
D3
D4
D7
D8
D9
D12
D13
D14
D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/SMODE
I/O
I/O
I/O
I/O
I/O
GND
I/O/SDO
I/O
GND
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
GND
VCC
VCC
I/O
I/O
I/O
E1
E2
E3
E13
E14
E15
F1
F2
F3
F13
F14
F15
G1
G2
G3
G4
G12
G13
G14
G15
H1
H2
H3
H4
H12
H13
H14
H15
J1
J2
J3
J4
J12
J13
J14
J15
K1
K2
K3
K13
K14
K15
L1
L2
L3
L13
L14
L15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
CLK1/I
I/O
I/O
I/O
GND
CLK2/I
GND
GND
CLK0/I
GND
I/O
I/O
I/O
CLK3/I
VCC
VCC
CLK
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
M2
M3
M4
M7
M8
M9
M12
M13
M14
M15
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
I/O
I/O
I/O
VCC
VCC
GND
VCC
GND
I/O
I/O/SCLK
I/O
I/O
I/O/SDI
I/O
I/O
I/O
I/O
I/O
ISREN
I/O
GND
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-97599
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 12
DSCC FORM 2234
APR 97
Case outline Y and Z
Device
type
All
Device
type
All
Device
type
All
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
GND
I/O
I/O
I/O
I/O
I/O/SCLK
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK/I
VCC
GND
CLK/I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O/SMODE
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
I/O
I/O
I/O
I/O
I
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/SDO
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK2/I
VCC
GND
CLK3/I
I/O
I/O
I/O
I/O
I/O
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/SD1
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ISREN
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
FIGURE 2. Terminal connections - Continued.
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Truth table
Input pins
Output pins
I/CLK
I
I/O
X
X
Z
NOTES:
1. X = Don't care
2. Z = High impedance
FIGURE 3. Truth table (unprogrammed).
FIGURE 4. Output load circuits and test conditions.
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Test Waveforms Input pulses
FIGURE 4. Output load circuits and test conditions - Continued.
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FIGURE 5. Switching waveforms.
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FIGURE 5. Switching waveforms - Continued.
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FIGURE 5. Switching waveforms - Continued.
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FIGURE 5. Switching waveforms - Continued.
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MICROCIRCUIT DRAWING
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3.11 Processing CPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.11.1 Erasure of CPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics
specified in 4.6 herein.
3.11.2 Programmability of CPLDs. When specified, devices shall be programmed to the specified pattern using the
procedures and characteristics specified in 4.7 herein.
3.11.3 Verification of erasure or programmed CPLDs. When specified, devices shall be verified as either programmed (see
4.7 herein) to the specified pattern or erased (see 4.6 herein). As a minimum, verification shall consist of performing a functional
test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute
a device failure, and shall be removed from the lot.
3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitor. This
reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect
the reprogrammability of the device. The methods and procedures may be vendor specific, but shall be under document control
and shall be made available upon request.
3.13 Data Retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
be done for initial characterization and after any design or process changes which may affect data retention. The methods and
procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 her ein over the full military
temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of
the acquiring or preparing activity, along with the test data.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical
parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. Prior to burn-in, the devices shall be programmed (see 4.7 herein) with a checkerboard pattern or equivalent
(manufacturers at their option may employ an equivalent pattern provided it is topologically true alternating bit pattern).
The pattern shall be read before and after burn-in. Devices having bits not in the proper state after burn-in shall
constitute a device failure and shall be removed from the lot. The manufacturer as an option may use built-in test
circuitry by testing the entire lot to verify programmability and AC performance without programming the user array.
c. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015.
(2) TA = +125°C, minimum.
d. Interim and final electrical test parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
SIZE
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TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Subgroups
(in accordance with
MIL-STD-883,
TM 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Line
no.
Test requirements
Device
class M
Device
class Q
Device
class V
1
Interim electrical
parameters (see 4.2)
1, 7, 9
or
2, 8A, 10
2
Static burn-in
(method 1015)
Not
required
Not
required
Required
3
Same as line 1 1*, 7* Δ
4
Dynamic burn-in
(method 1015)
Required Required Required
5
Final electrical
parameters (see 4.2)
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
1*, 2, 3, 7*, 8A,
8B, 9, 10, 11
6
Group A test
requirements (see 4.4)
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
1, 2, 3, 4**, 7,
8A, 8B, 9, 10, 11
7
Group C end-point
electrical parameters
(see 4.4)
2, 3, 7,
8A, 8B
2, 3, 7,
8A, 8B
1, 2, 3, 7, 8A,
8B, 9, 10, 11 Δ
8
Group D end-point
electrical parameters
(see 4.4)
2, 3, 8A, 8B 2, 3, 8A, 8B 2, 3, 8A, 8B
9
Group E end-point
electrical parameters
(see 4.4)
1, 7, 9 1, 7, 9 1, 7, 9
1/ Blank spaces indicate tests are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7 and 8 functional tests shall verify the truth table.
4/ * indicates PDA applies to subgroup 1 and 7.
5/ ** see 4.4.1e.
6/ Δ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be computed
with reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d.
TABLE IIB. Delta limits at +25°C.
Device types
Parameter 1/ All
IOZ ± 10% of the specified
value in table I
IIX ± 10% of the specified
value in table I
1/ The above parameter shall be recorded before
and after the required burn-in and life tests
to determine the delta Δ.
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4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4). 4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.
c. For device class M, subgroups 7, 8A and 8B tests shall be sufficient to verify the truth table. For device classes Q and
V, subgroups 7, 8A and 8B shall include verifying the functionality of the device.
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JESD 78 may be used for reference.
e. Subgroup 4 (CIN and COUT measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1 MHz. Sample size is three devices with no failures, and all input and output
terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-
STD-883.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-
883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after life test perform final electrical parameter tests, subgroups 1, 7, and
9.
4.6 Erasure procedures. Erasure procedures shall be as specified by the device manufacturer and shall be made available
upon request.
4.7 Programming procedures. The programming procedures shall be as specified by the device manufacturer and shall be
made available upon request.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
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6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-09-05
Approved sources of supply for SMD 5962-97599 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated
revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at
http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit
drawing PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9759901QXC 0C7V7 CY7C375i-66GMB
5962-9759901QYC 3/ CY7C375i-66UMB
5962-9759901QZC 0C7V7 CY7C375i-66UMB
5962-9759902QXC 0C7V7 CY7C375i-83GMB
5962-9759902QYC 3/ CY7C375i-83UMB
5962-9759902QZC 0C7V7 CY7C375i-83UMB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Ct
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
