TDA7492E 79 W + 79 W dual BTL class-D audio amplifier Datasheet - production data * * * * * * PowerSSO-36 exposed pad up * * Features * * * * * Wide-range single-supply operation (7 - 26 V) Possible output configurations: - 2 x PBTL - 1 x Parallel BTL BTL output capabilities (VCC = 26 V): - 61 W + 61 W, 4 , THD 1% - 79 W + 79 W, 4 , THD 10% - 44 W + 44 W, 6 , THD 1% - 57 W + 57 W, 6 , THD 10% - 34 W + 34 W, 8 , THD 1% - 44 W + 44 W, 8 , THD 10% Parallel BTL output capabilities (VCC = 26 V): - 86 W, 3 , THD 1% - 110 W, 3 , THD 10% High efficiency February 2017 Four selectable, fixed-gain settings of nominally 20.8 dB, 26.8 dB, 30 dB and 32.8 dB Differential inputs minimize common-mode noise Standby, mute and play operating modes Short-circuit protection Output power limited by PLIMIT function Detection of shorted output pins during startup Thermal overload protection ECOPACK(R) environmentally friendly package Description The TDA7492E is a dual BTL class-D audio amplifier with single power supply designed for home audio applications. The device is housed in a 36-pin PowerSSO package with exposed pad up (EPU), and as a result of its high efficiency, a simple heatsink is required. Table 1: Device summary Order code Operating temp. range Package Packaging TDA7492ETR -40 to +85C PowerSSO-36 EPU Tape and reel DocID027638 Rev 1 This is information on a product in full production. 1/24 www.st.com Contents TDA7492E Contents 1 Device block diagram...................................................................... 5 2 Pin description ................................................................................ 6 3 4 2.1 Pinout ................................................................................................ 6 2.2 Pin list ............................................................................................... 7 Electrical specifications .................................................................. 8 3.1 Absolute maximum ratings ................................................................ 8 3.2 Thermal data ..................................................................................... 8 3.3 Electrical specifications ..................................................................... 9 3.4 Stereo BTL application .................................................................... 10 3.5 Parallel BTL (mono) application ...................................................... 10 Application information ................................................................ 11 4.1 Gain setting ..................................................................................... 11 4.2 Stereo and mono applications ......................................................... 11 4.3 Smart protections ............................................................................ 11 4.4 4.3.1 Overcurrent protection (OCP) .......................................................... 11 4.3.2 Thermal protection............................................................................ 12 4.3.3 Power limit ........................................................................................ 12 Mode selection ................................................................................ 13 5 Schematic diagram........................................................................ 15 6 Characterization curves ................................................................ 16 6.1 7 Package information ..................................................................... 20 7.1 8 2/24 Stereo configuration ........................................................................ 16 PowerSSO36 EPU package information ......................................... 20 Revision history ............................................................................ 23 DocID027638 Rev 1 TDA7492E List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description list ......................................................................................................................... 7 Table 3: Absolute maximum ratings ........................................................................................................... 8 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Electrical specifications ................................................................................................................. 9 Table 6: Stereo BTL application ............................................................................................................... 10 Table 7: Stereo BTL (mono) application ................................................................................................... 10 Table 8: Gain settings ............................................................................................................................... 11 Table 9: Overcurrent protection ................................................................................................................ 11 Table 10: Overcurrent protection (mute mode) ........................................................................................ 12 Table 11: Max effective voltage of PLIMIT pin vs. power supply and load............................................... 13 Table 12: Mode settings............................................................................................................................ 13 Table 13: PowerSSO-36 EPU package mechanical data ........................................................................ 22 Table 14: Document revision history ........................................................................................................ 23 DocID027638 Rev 1 3/24 List of figures TDA7492E List of figures Figure 1: Internal block diagram (showing one channel only) .................................................................... 5 Figure 2: Pin connections (top view, PCB view) ......................................................................................... 6 Figure 3: Mono BTL settings ..................................................................................................................... 11 Figure 4: Recommended power limit pin connections .............................................................................. 12 Figure 5: Standby and mute circuits ......................................................................................................... 14 Figure 6: Turn-on/off sequence for minimizing speaker "pop" .................................................................. 14 Figure 7: Application circuit ....................................................................................................................... 15 Figure 8: Output power vs. supply voltage ............................................................................................... 16 Figure 9: THD vs. Pout (Vs = 26 V, f = 1 kHz) .......................................................................................... 16 Figure 10: THD vs. Pout (Vs = 26 V, f = 100 Hz) ..................................................................................... 16 Figure 11: THD vs. Pout (Vs = 26 V, f = 6 kHz) ........................................................................................ 16 Figure 12: THD vs. frequency (Vs = 26 V, Po = 1 W)............................................................................... 17 Figure 13: Frequency response Vs = 26 V ............................................................................................... 17 Figure 14: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, not weighted) ............................................. 17 Figure 15: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, not weighted) ............................................. 17 Figure 16: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, A-weighted) ................................................ 18 Figure 17: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, A-weighted) ................................................ 18 Figure 18: Crosstalk Vs = 26 V ................................................................................................................. 18 Figure 19: FFT (0 dB) Vs = 26 V............................................................................................................... 18 Figure 20: FFT (-60 dB) Vs = 26 V ........................................................................................................... 19 Figure 21: PowerSSO-36 EPU package outline ....................................................................................... 21 4/24 DocID027638 Rev 1 TDA7492E Device block diagram Figure 1: "Internal block diagram (showing one channel only)" shows the block diagram of one of the two identical channels of the TDA7492E. Figure 1: Internal block diagram (showing one channel only) GAIN PLMT Gain Settings Power Limit - Gate Driver OUTP Gate Driver OUTN + + INP + - INN - + VREF + + - PWM logic level shift 1 Device block diagram - ROSC Oscillator SYNCLK Standby Mute/Play STANDBY MUTE Thermal,Undervoltage Overcurrent protections DIAG DocID027638 Rev 1 VDD,VSS Regulators VDDS VSS 5/24 Pin description TDA7492E 2 Pin description 2.1 Pinout Figure 2: Pin connections (top view, PCB view) SUB GN D 1 SVCC OUTPB 2 VR EF OUTPB 3 33 IN NB PGNDB 4 IN PB PGNDB 5 31 GAIN PV CCB 6 30 PLIMIT PV CCB 7 OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VD DS OUTNA 25 SYNCLK PV CCA 12 24 ROSC PV CCA 13 23 IN NA PGNDA 14 22 IN PA PGNDA 15 21 MUTE 20 STBY 19 VD DPW 36 VSS 35 34 32 29 6/24 SVR EP e xpo sed pa d u p Con ne ct to g ro un d DocID027638 Rev 1 11 OUTPA 16 OUTPA 17 PGN D 18 TDA7492E 2.2 Pin description Pin list Table 2: Pin description list Number Name Type Description 1 SUB_GND PWR 2, 3 OUTPB O 4, 5 PGNDB PWR Power stage ground for right channel 6, 7 PVCCB PWR Power supply for right channel 8, 9 OUTNB O Negative PWM output for right channel 10, 11 OUTNA O Negative PWM output for left channel 12, 13 PVCCA PWR Power supply for left channel 14, 15 PGNDA PWR Power stage ground for left channel 16, 17 OUTPA O Positive PWM output for left channel 18 PGND PWR 19 VDDPW O 3.3 V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3 V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 PLIMIT I Output voltage level setting 31 GAIN I Gain setting input 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR 36 VSS O 3.3 V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to GND Connect to the frame Positive PWM for right channel Power stage ground Signal ground Signal power supply DocID027638 Rev 1 7/24 Electrical specifications TDA7492E 3 Electrical specifications 3.1 Absolute maximum ratings Table 3: Absolute maximum ratings Symbol VCC 3.2 Parameter Value Unit DC supply voltage for pins PVCCA, PVCCB, SVCC 30 V VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN, MODE -0.3 to +4.6 V Top Operating temperature -40 to +85 C Tj Junction temperature -40 to +150 C Tstg Storage temperature -40 to +150 C Thermal data Table 4: Thermal data Symbol Rth j-case 8/24 Parameter Thermal resistance, junction-to-case DocID027638 Rev 1 Min. Typ. - 2.98 Max. Unit C/W TDA7492E 3.3 Electrical specifications Electrical specifications Unless otherwise stated, the results in Table 5: "Electrical specifications" below are given for the conditions: VCC = 26 V, RL= 6 , ROSC = 33 k, f = 1 kHz, GV = 20.8 dB and Tamb = 25 C. Table 5: Electrical specifications Symbol Parameter Condition Min. Typ. Max. Unit VCC Supply voltage for pins PVCCA, PVCCB, SVCC - 7 - 26 V Iq Total quiescent current Without LC, no load - 40 IqSTBY Quiescent current in standby - - 1 VOS Output offset voltage Vi = 0, Av = 20 dB, no load IOCP Overcurrent protection threshold RL = 0 Tj Junction temperature at thermal shutdown - Ri Input resistance Differential input RdsON Power transistor on-resistance High side Low side Closed-loop gain - 20 A mV 9 10 13 A 140 150 160 C 60 - k - 0.2 - - 0.2 - 20.8 - GAIN < 0.25*Vdd GV mA 0.25*Vdd < GAIN < 0.5*Vdd - 26.8 - 0.5*Vdd < GAIN < 0.75*Vdd - 30 - GAIN1>0.75*Vdd - 32.8 - dB GV Gain matching - - - 1 dB CT Crosstalk f = 1 kHz - 70 - dB SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 V, CSVR = 10 F - 60 - dB Tr, Tf Rise and fall times PWM signal 50% duty cycle - 24 40 ns fSW Switching frequency Internal oscillator with external Rosc = 33 k - 500 - kHz fSWR Output switching frequency range With internal oscillator by changing Rosc (1) 450 - 550 kHz VinH Digital input high (H) - 2.0 - - VinL Digital input low (L) - - 0.8 STBY < 0.5 V Mute = 'X' Function mode AMUTE Standby, Mute, Play Mute attenuation Standby STBY > 2.5 V Mute < 0.8 V Mute STBY > 2.5 V Mute > 2.5 V Play VMUTE = 1 V V 60 80 - dB Notes: (1)f 6 SW = 10 / [(12 * ROSC + 110) * 4] kHz, fSYNCLK = 2 * fSW (where ROSC is in k and fSW in kHz) with Rosc = 33 k. DocID027638 Rev 1 9/24 Electrical specifications 3.4 TDA7492E Stereo BTL application All specifications are for VCC = 22 V, Rosc = 33 k, f = 1 kHz, Tamb = 25 C, unless otherwise specified. Table 6: Stereo BTL application Symbol Po THD VN 3.5 Parameter Condition Min. Typ. Max. RL = 6 , THD = 10% - 41 - RL = 6 , THD = 1% - 32 - RL = 6 , THD = 10%, VCC = 26 V - 57 - RL = 6 , THD = 1%, VCC = 26 V - 44 - Total harmonic distortion Po = 1 W, fin = 1 kHz - 0.04 - % Total output noise Inputs shorted and connected to GND, A curve, GV = 20.8 dB - 150 - V Output power Unit W Parallel BTL (mono) application All specifications are for VCC = 22 V, Rosc = 33 k, f = 1 kHz, Tamb = 25 C, INPB, INNB connected to VDDS, unless otherwise specified. Table 7: Stereo BTL (mono) application Symbol Po THD VN 10/24 Parameter Condition Min. Typ. Max. RL = 3 , THD = 10% - 90 - RL = 3 , THD = 1% - 70 - RL = 3 , THD = 10%, Vcc = 26 V - 110 - RL = 3 , THD = 1%, VCC = 26V - 86 - Total harmonic distortion Po = 1 W, fin = 1 kHz - 0.04 - % Total output noise Inputs shorted and connected to GND, A curve, GV = 20.8 dB - 150 - V Output power DocID027638 Rev 1 Unit W TDA7492E Application information 4 Application information 4.1 Gain setting The four gain settings of the TDA7492E are set by GAIN (pin 31). Internally, gain is set by changing the feedback resistors of the amplifier. Table 8: Gain settings Voltage on GAIN pin Total gain VGAIN < 0.25*VDDS 20.8 dB GAIN pin connected to SGND 0.25*VDDS < VGAIN < 0.5*VDDS 26.8 dB External resistor divider <100 k 30 dB External resistor divider <100 k 0.5*VDDS < VGAIN < 0.75*VDDS VGAIN > 0.75*VDDS 4.2 Application recommendations 32.8 dB GAIN pin connected to VDDS Stereo and mono applications The TDA7492E can be used in stereo BTL or in mono BTL configuration. When the input pins, INPB and INNB of the right channel are directly shorted to VDDS (without input capacitors) the device is in mono configuration as shown in Figure 3: "Mono BTL settings". Figure 3: Mono BTL settings OUTPB INPA INNA OUTPA IC INPB INNB OUTNA LC Filter OUTNB 4.3 Smart protections 4.3.1 Overcurrent protection (OCP) If the overcurrent protection threshold is reached, the power stage will be shut down immediately. The device will recover automatically when the fault is removed. The overcurrent protection scheme is shown in Table 9: "Overcurrent protection". Two typical thresholds are as follows. Table 9: Overcurrent protection I (Shutdown) High side (A) 11.2 Low side (A) 10.0 DocID027638 Rev 1 11/24 Application information TDA7492E The thresholds in MUTE mode are reduced to about 1/2 and two typical thresholds are as follows. Table 10: Overcurrent protection (mute mode) I (Shutdown) 4.3.2 High side (A) 6.2 Low side (A) 5.9 Thermal protection When internal die temperature exceeds 140 C, the device enters into Mute by pulling the MUTE pin low first. When internal die temperature exceeds 150 C, the device directly shuts down the power stage. The TDA7492E automatically recovers when the temperature become lower than the threshold. 4.3.3 Power limit A built-in power limit is used to limit the output voltage level below the supply rail by limiting the duty cycle. The limit level is set through the voltage at PLIMIT (pin 30). The pin voltage is set by the following equation: (//400) = (//400 + ) Figure 4: Recommended power limit pin connections VDDS PLIMIT 400 k Rup Rdn Power Limiter It is recommended that external resistors are less than 40 k if a voltage divider is used as shown in Figure 4: "Recommended power limit pin connections". The relationship of the maximum duty cycle (Dmax) and the voltage at PLIMIT is: = 8.8 x 2 x x + 1 - x 2 x 2 Where VCC is the power supply voltage, VPLIMIT is the voltage applied at the PLIMIT pin, Rs is the series resistance including Rdson of power transistor, output filter resistance and bonding wire resistance. Rload is the load resistance. 12/24 DocID027638 Rev 1 TDA7492E Application information An example of maximum effective control voltage at PLIMIT vs. power supply and load resistance is shown in Table 11: "Max effective voltage of PLIMIT pin vs. power supply and load". Table 11: Max effective voltage of PLIMIT pin vs. power supply and load Power supply Rload 4.4 7V 13 V 24 V 4 0.71 V 1.32 V 2.44 V 6 0.74 V 1.37 V 2.53 V 8 0.75 V 1.39 V 2.57 V Mode selection The three operating modes of the TDA7492E are set by two inputs: STBY (pin 20) and MUTE (pin 21). * * * Standby mode: all circuits are turned off, very low current consumption. Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle Play mode: the amplifiers are active. The protection functions of the TDA7492E are implemented by pulling down the voltages of the STBY and MUTE inputs shown in Figure 5: "Standby and mute circuits". The input current of the corresponding pins must be limited to 200 A. Table 12: Mode settings Mode STBY MUTE Standby L(1) X (don't care) Mute H L Play H H Notes: (1)Drive levels defined in Table 5: "Electrical specifications". DocID027638 Rev 1 13/24 Application information TDA7492E Figure 5: Standby and mute circuits R2 Standby 20 STBY 3.3 V 33 k 0V C7 Mute TDA7492E R4 3.3 V 0V 2.2 F 21 MUTE 33 k C15 2.2 F Figure 6: Turn-on/off sequence for minimizing speaker "pop" 14/24 DocID027638 Rev 1 TDA7492E 5 Schematic diagram Schematic diagram Figure 7: Application circuit L4 C1 22uH 1uF C3 1nF C2 J1 C5 INPUT 100nF For Single-Ended J7 Input 4 L+ 1 R2 R+ 100nF C27 330pF 47k INPUT L+, L- Only INNB MONO Config R16 8R L1 R3 39K R11 100k R12 100k J11 J10 C18 1 2 C14 1nF 2 33k R2 S1 STBY 1 3 750k OUT 1 C29 2.2uF IN IC2 L4931CZ33 3 2 R8 VCC R17 8R 220nF 1uF C10 100nF 1uF R4 3 4.7k GND C20 *220nF C31 C12 S2 MUTE R19 VCC 2 J2 220nF C19 100nF C13 1nF J4 1 C42 J6 J5 INNB 1uF PS MONO OUTPUT L+, L- Only 22uH C21 MONO OUT 330pF C11 3V3 220nF L3 R5 22R J8 For Single-Ended Input and MONO Config J3 C24 C23 + 2200uF 35V 2 100k J13 C41 22uH C8 100nF R10 2 L- 220nF 3 1 47k R14 PS 100k MONO OUT L-OUTPUT Load=6 ohm L+ 1 100nF FREQUENCY SHIFT R9 Q1 180K KTC3875(S) R13 C40 C26 *220nF C30 1uF C25 INNB C6 MONO 220nF 220nF R1 R7 22R R15 8R C28 22R C4 1nF 1uF 3 L- R6 L2 R-OUTPUT Load=6 ohm R+ 2 1 RC43 C22 220nF 220nF R18 J14 8R 22uH C17 4.7uF 10V + C15 2.2uF 16V + C7 2.2uF 16V C16 10uF 10V 1.2k GND C9 100nF TDA7492E CLASS-DAMPLIFIER DocID027638 Rev 1 15/24 Characterization curves 6 TDA7492E Characterization curves Unless otherwise stated, measurements were made under the following conditions: VCC = 22 V, Rl = 6 , f = 1 kHz, Gv = 20.8 dB, ROSC = 33 k, Tamb = 25 C. Note: Maximum output power must be derated according to case temperature. 6.1 Stereo configuration The following characterization curves were made using the TDA7492E demonstration board (Figure 7: "Application circuit"). The characterization curves were made under the following test conditions: Vs = 7 and 26 V, Rl = 6 , Rosc = 33 k, Cosc = 100 nF, Gain = 20.8 dB and Tamb = 25C unless otherwise specified. Figure 9: THD vs. Pout (Vs = 26 V, f = 1 kHz) Figure 8: Output power vs. supply voltage 10 5 THD (%) 2 1 0.5 Vs=26V, Rl=6 , f=1kHz 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 Pout (W) Figure 11: THD vs. Pout (Vs = 26 V, f = 6 kHz) Figure 10: THD vs. Pout (Vs = 26 V, f = 100 Hz) 10 10 5 5 2 1 1 Rl =6 , f=100 Hz 0.2 0.1 0.05 0.02 Rl =6 , f=6kHz 0.2 0.1 0.05 0.02 0.01 0.01 0.005 0.005 0.002 0.002 0.001 10m 20m 0.001 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 Pout (W) 16/24 Vs=26V, 0.5 THD (%) THD (%) 0.5 2 Vs=26V, DocID027638 Rev 1 50m 100m 200m 500m 1 2 Pout (W) 5 10 20 50 TDA7492E Characterization curves Figure 12: THD vs. frequency (Vs = 26 V, Po = 1 W) Figure 13: Frequency response Vs = 26 V 10 5 2 1 Vs=26V, Rl =6 , Po= 1W 0.2 dBrA THD (%) 0.5 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k Frequency (Hz) 2k 5k 10k 20k Figure 14: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, not weighted) +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 20 +0 +0 -10 -20 -20 -30 -40 -60 -50 200 500 1k 2k Frequency (Hz) 5k 10k 20k -70 -80 -80 -90 -90 -100 -100 -110 -110 50 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k DocID027638 Rev 1 Gain=20.6dB, No-Weight Vs=26V, Rl=6 , Po= 1W, f=1kHz -60 -70 -120 20 100 -30 Gain = 32.6dB, No -Weight Vs=26V,Rl=6 ,Po=1W, f=1kHz dBrA dBrA -50 50 Figure 15: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, not weighted) -10 -40 Rl =6 , Po= 1W -120 20 50 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k 17/24 Characterization curves TDA7492E Figure 16: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, A-weighted) Figure 17: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, A-weighted) +0 -10 -20 -30 -40 dBrA -50 Gain=20.6dB, A-Weight Vs=26V, Rl=6 , Po=1W, f=1kHz -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Frequency (Hz) Figure 18: Crosstalk Vs = 26 V +0 -10 -20 Figure 19: FFT (0 dB) Vs = 26 V T -30 -40 dB -50 dBrA Gain= 32.6dB, Vs=26V, Rl =6 , Po=1W, f=1kHz -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 18/24 50 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 Gain=32.6dB, Vs=26V, Rl =6 , Po=1W, f=1kHz 50 100 200 500 1k Frequency (Hz) DocID027638 Rev 1 2k 5k TDA7492E Characterization curves Figure 20: FFT (-60 dB) Vs = 26 V +0 -10 -20 -30 -40 Gain=32.6dB, Vs=26V, Rl =6 , Po=1W, f=1kHz dBrA -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DocID027638 Rev 1 19/24 Package information 7 TDA7492E Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO36 EPU package information The device comes in a 36-pin PowerSSO package with exposed pad up (EPU). Figure 21: "PowerSSO-36 EPU package outline" shows the package outline and Table 13: "PowerSSO-36 EPU package mechanical data" gives the dimensions. 20/24 DocID027638 Rev 1 TDA7492E Package information Figure 21: PowerSSO-36 EPU package outline 7618147_F DocID027638 Rev 1 21/24 Package information TDA7492E Table 13: PowerSSO-36 EPU package mechanical data Dimensions in mm Dimensions in inches Symbol 22/24 Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 DocID027638 Rev 1 TDA7492E 8 Revision history Revision history Table 14: Document revision history Date Revision 24-Feb-2017 1 Changes Initial release DocID027638 Rev 1 23/24 TDA7492E IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved 24/24 DocID027638 Rev 1