Never stop thinking.
HYS72D128300GBR-[5/6/7]-B
HYS72D256320GBR-[5/6/7]-B
HYS72D128500HR-[7F/7]-B
HYS72D128321GBR-[5/6/7]-B
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
DDR SDRAM
Green Product
Lead Containing Product
Data Sheet, Rev. 0.5, Dec. 2003
Memory Products
Edition 2003-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain compo nents and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions an d charts stated herein.
Information
F or further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical require ments components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support de vices or systems with the e x press written
approv al of Infineon Technologies, if a f ailure of such components can reasonab ly be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Never stop thinking.
HYS72D128300GBR-[5/6/7]-B
HYS72D256320GBR-[5/6/7]-B
HYS72D128500HR-[7F/7]-B
HYS72D128321GBR-[5/6/7]-B
184-Pin Registered Double Data Rate SDRAM Module
Reg DIMM
Data Sheet, Rev. 0.5, Dec. 2003
Memory Products
Template: mp_a4_v2.0_2003-06-06.fm
HYS72D128300GBR-[ 5/6/7]-B, HYS72D256320GBR-[5/6/7]-B, HYS72D128500HR-[7F/7]-B
Revision History: Rev. 0.5 2003-12
Previous Version:
Page Subjects (major changes since last revision)
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Data Sheet 5 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Overview
Data Sheet 6 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Overview
Data Sheet 6 Rev. 0.5, 2003-12
1Overview
1.1 Features
• 184-pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for “1U” PC, Workstation and Server main
memory applications
• One rank 128M ×72 organizat ion and two rank 256M ×72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (±0.2 V) power
supply and +2.6(±0.1 V) power supply for DDR400
• Built with DDR SDRAMs in 66-Lead TSOPII and FBGA 60 package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Re-drive for all input signals using register and PLL devices.
• Serial Presence Detect with E2PROM
• Low Profile Modules form factor: 133.35 mm ×28.58 mm (1.1”) ×4.00 mm and 133.35 mm ×30.48 mm
(1.2”) ×4.00 mm
• Based on Jedec standard reference card layout RawCard “B”, “C“ and “D“
• Gold plated contacts
1.2 Description
The HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B are low profile versions of the standard
Registered DIMM modules with 1.1” inch (28.58 ) and 1.2” inch (30, 40 mm) height f or 1U Server Applications. The
Low Profile DI MM versions are available as 128M ×72 (1 GB) and 256M × 72 (2 GB).
The memory array is designed with Double Data Rate Synchro nous DRAMs for ECC applications. All cont rol and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to th e system bus, but adds on e cycle to the SDRAM timing. A varie ty of decoupling capacito rs
are mounted on t he PC board. The DIMMs feature se rial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Table 1 Performance
Part Number Speed Code –5–6–7–7F Unit
Speed Grade Component DDR400B DDR333B DDR266A DDR266 —
Module PC3200–3033 PC2700–2533 PC2100–2033 PC2100–2022 —
max. Clock Frequency @ CL = 3 fCK3 200 166 — — MHz
@ CL = 2.5 fCK2.5 166 166 143 143 MHz
@ CL = 2 fCK2 133 133 133 133 MHz
Data Sheet 7 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Overview
Data Sheet 7 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Overview
Table 2 Ordering Information1)2)
Type Compliance Code2) Description SDRAM
Technology
PC3200 (CL=3)
HYS72D128300GBR–5–B PC3200R–30331–C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (×4)
HYS72D128321GBR–5–B PC32 00R–30331–B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (×8)
HYS72D256320GBR–5 –B PC3200R–30331–D0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)
PC2700 (CL=2.5)
HYS72D128300GBR–6–B PC2700R–25330–C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (×4)
HYS72D128321GBR–6–B PC27 00R–25330–B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (×8)
HYS72D256320GBR–6–B PC2700R–25330–D0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)
PC2100 (CL=2)
HYS72D128300GBR–7–B PC2100R–20330–C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (×4)
HYS72D128321GBR–7–B PC21 00R–203 30–B0 t wo ran ks1 GByte Reg. ECC DIMM 512 MBit (×8)
HYS72D256320GBR–7–B PC2100R–20330–D0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (×4)
HYS72D128500HR–7F–B PC2100R–20220–M one rank 1GByte Reg. ECC DIMM 512 MBit (×4)
HYS72D128500HR–7–B PC2100R–20330–M one rank 1GByte Reg. ECC DIMM 512 MBit (×4)
1) All part numbers end with a place code (no t shown), designa ting the silico n-die revision. Referen ce information available
on request. Example: HYS72D128300GBR-[5/6/7]-B, indicating Rev.B die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort for example “PC2100R”, the latencies
(for example “20330” means CAS latency = 2.5, tRCD latency = 3 and tRP latency =3 ) and the Raw Card used for this module
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 8 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 8 Rev. 0.5, 2003-12
2 Pin Configuration
Table 3 Pin Definitions and Functions
Symbol Type Function
A0 - A11,A12 Address Inputs
BA0, BA1 Bank Selects
DQ0 - DQ63 Data Input/Output
CB0 - CB7 Check Bits (×72 organization only)
RAS,CAS,WE Command Inputs
CKE0, CKE1 Clock Enable
DQS0 - DQS8 SDRAM low data strobes
CK0, CK0 Differential Clock Input
DM0 - DM8
DQS9 - DQS17 SDRAM low data mask/
high data strobes
S0 - S1 Chip Selects
VDD Power (+2.5 V)
VSS Ground
VDDQ I/O Driver power supply
VDDID VDD Indentification flag
VDDSPD EEPROM power supply
VREF I/O reference supply
SCL Serial bus clock
SDA Serial bus data line
SA0 - SA2 slave address select
NC no connect
DU don’t use
RESET Reset pin (forces register inputs low)1)
1) for detailed description of the Po wer Up an d Power Management on DDR Registered DIMMs see the Application Note at
the end of this datasheet
Data Sheet 9 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 9 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Table 4 Pin Config ur at io n1)
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
1VREF 48 A0 94 DQ4 141 A10
2 DQ0 49 CB2 95 DQ5 142 CB6
3VSS 50 VSS 96 VDDQ 143 VDDQ
4 DQ1 51 CB3 97 DQS9 144 CB7
5DQS052BA1 98DQ6 KEY
6DQ2 KEY 99 DQ7 145 VSS
7VDD 53 DQ32 100 VSS 146 DQ36
8DQ3 54
VDDQ 101 NC 147 DQ37
9NC 55DQ33102NC 148
VDD
10 RESET 56 DQS4 103 NC 149 DM4/DQS13
11 VSS 57 DQ34 104 VDDQ 150 DQ38
12 DQ8 58 VSS 105 DQ12 151 DQ39
13 DQ9 59 BA0 106 DQ13 152 VSS
14 DQS1 60 DQ35 107 DQS10 153 DQ44
15 VDDQ 61 DQ40 108 VDD 154 RAS
16 DU 62 VDDQ 109 DQ14 155 DQ45
17 DU 63 WE 110 DQ15 156 VDDQ
18 VSS 64 DQ41 111 CKE1 157 S0
19 DQ10 65 CAS 112 VDDQ 158 S1
20 DQ11 66 VSS 113 NC 159 DQS14
21 CKE0 67 DQS5 114 DQ20 160 VSS
22 VDDQ 68 DQ42 115 NC / A12 161 DQ46
23 DQ16 69 DQ43 116 VSS 162 DQ47
24 DQ17 70 VDD 117 DQ21 163 NC
25 DQS2 71 NC 118 A11 164 VDDQ
26 VSS 72 DQ48 119 DQS11 165 DQ52
27 A9 73 DQ49 120 VDD 166 DQ53
28 DQ18 74 VSS 121 DQ22 167 NC
29 A7 75 DU 122 A8 168 VDD
30 VDDQ 76 DU 123 DQ23 169 DQS15
31 DQ19 77 VDDQ 124 VSS 170 DQ54
32 A5 78 DQS6 125 A6 171 DQ55
33 DQ24 79 DQ50 126 DQ28 172 VDDQ
34 VSS 80 DQ51 127 DQ29 173 NC
35 DQ25 81 VSS 128 VDDQ 174 DQ60
36 DQS3 82 VDDID 129 DQS12 175 DQ61
37 A4 83 DQ56 130 A3 176 VSS
38 VDD 84 DQ57 131 DQ30 177 DQS16
39 DQ26 85 VDD 132 VSS 178 DQ62
40 DQ27 86 DQS7 133 DQ31 179 DQ63
41 A2 87 DQ58 134 CB4 180 VDDQ
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 10 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 10 Rev. 0.5, 2003-12
42 VSS 88 DQ59 135 CB5 181 SA0
43 A1 89 VSS 136 VDDQ 182 SA1
44 CB0 90 NC 137 CK0 183 SA2
45 CB1 91 SDA 138 CK0 184 VDDSPD
46 VDD 92 SCL 139 VSS ––
47 DQS8 93 VSS 140 DQS17 – –
1) A12 is used for 256Mbit and 512Mbit based modules only.
Table 5 Address Format
Density Organization Memory
Ranks SDRAMs # of
SDRAMs # of row/bank/
column bits Refresh Period Interval
1 GB 128M x 72 1 128M ×4 18 13/2/12 8K 64 ms 7.8 µs
1 GB 128M x 72 2 64M ×8 18 13/2/11 8K 64 ms 7.8 µs
2 GB 256M x 72 2 128M ×4 36 13/2/12 8K 64 ms 7.8 µs
Table 4 Pin Config ur at io n1) (cont’d)
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
Data Sheet 11 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 11 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Figure 1 Block Diagram: 1 Rank 128M ×72 DDR SDRAM DIMM HYS72D128[300/500]GBR–[5/6/7/7F]–B
RS0
DQS4
DQS6
DQS2
DQ0
DQ1
DQ2
DQ3
DQ8
DQ9
DQ10
DQ11
DQ16
DQ17
DQ18
DQ19
DQ24
DQ25
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ56
DQ57
DQ58
DQ59
DQS
D0
DQS
DQS
DQS
DQS
DQS
DQS
DQS0
D1
D2
D3
D4
D5
D7
DQ48
DQ49
DQ50
DQ51
DQS
D6
DQ4
DQ5
DQ6
DQ7
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ60
DQ61
DQ62
DQ63
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM0/DQS9
D10
D11
D12
D13
D14
D16
DQ52
DQ53
DQ54
DQ55
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
CB0
CB1
CB2
CB3
DQS
D8
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D17
SS
SS
SS
SS
SS
SS
SS
SS
SS
VSS
DQS1
DQS3
DQS8
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS5
DQS7
DM6/DQS15
DM5/DQS14
DM4/DQS13
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM7/DQS16
DM8/DQS17
Notes:
1. DQ-to-I/O wiring may be changed
within a byte.
2. DQ/DQS/DM/CKE/S relationships
must be maintained as shown.
3. DQ/DQS resistors should be 22
Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. Address and control resistors
should be 22 Ohms.
6. A13 is not wired for raw card B.
VDD
VSS
D0-D17
D0-D17
VDDQ D0-D17
D0-D17
VREF
VDDID Strap: see Note 4
CK0, CK0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
A0-A136RA0-RA136 -> A0-A136: SDRAMs D0-D17
RAS RRAS -> RAS: SDRAMs D0-D17
S0 RS0 -> CS : SDRAMs D0-D17
CAS RCAS -> CAS: SDRAMs D0-D17
CKE0 RCKE0A -> CKE: SDRAMs D0-D17
WE RWE -> WE: SDRAMs D0-D17
R
E
G
I
S
T
E
R
PCK
PCK RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
V
DDSPD
Serial PD
A0
Serial PD
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
Data Sheet 12 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 12 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Figure 2 Block Diagram – 2 Ranks 64M ×72 DDR SDRA M HYS72D128321GBR-[5/6/7]–B
DM0/DQS9
DQS3 DQS7
DQS2 DQS6
DQS1 DQS5
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
D0
DM
D9
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
D1
DM
D10
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
D2
DM
D11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
D3
DM
D12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
D4
DM
D13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
D5
DM
D14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
D6
DM
D15
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
D7
DM
D16
RS0
RS1
CS CS CS CS
CS CS CS CS
CS CS
CS CS
CS CS
CS CS
DQS0
DQS
DQS4
DQS DQS
DQS DQS
DQS DQS
DQ15
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
D8
DM
D17
CS CS
DQS8
DQS DQS
DQS
DQS
DQSDQS
DQS
DQS
DQS DQS DQS
VDD
VSS
D0-D17
D0-D17
VDDQ D0-D17
D0-D17VREF
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. RS0 and RS1 alternate between the back and front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
7. A13 is not wired for raw card A.
VDDID Strap: see Note 4
CK0, CK0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
S1 RS1 -> CS : SDRAMs D9-D17
BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
A0-A137RA0-RA137 -> A0-A137: SDRAMs D0-D17
RAS RRAS -> RAS: SDRAMs D0-D17
S0 RS0 -> CS : SDRAMs D0-D8
CAS RCAS -> CAS: SDRAMs D0-D17
CKE0 RCKE0 -> CKE: SDRAMs D0-D8
WE RWE -> WE: SDRAMs D0-D17
R
E
G
I
S
T
E
R
PCK
PCK RESET
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM7
DM6/DQS15
DM8/DQS17
DQS16
CKE1 RCKE1 -> CKE: SDRAMs D9-D17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
DDSPD
Serial PD
A0
Serial PD
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
Data Sheet 13 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Pin Configuration
Data Sheet 13 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Figure 3 Block Diagram – 2 Ranks 128M ×72 DDR SDRAM HYS72D256320GBR-[5/6/7]–B
PCK
PCK
RS0
DQS4
DQS6
DQS2
DQ0
DQ1
DQ2
DQ3
DQ8
DQ9
DQ10
DQ11
DQ16
DQ17
DQ18
DQ19
DQ24
DQ25
DQ26
DQ27
DQ32
DQ33
DQ34
DQ35
DQ40
DQ41
DQ42
DQ43
DQ56
DQ57
DQ58
DQ59
DQS
D0
DQS
DQS
DQS
DQS
DQS
DQS
DQS0
D1
D2
D3
D4
D5
D7
DQ48
DQ49
DQ50
DQ51
DQS
D6
DQ4
DQ5
DQ6
DQ7
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ60
DQ61
DQ62
DQ63
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM0/DQS9
D10
D11
D12
D13
D14
D16
DQ52
DQ53
DQ54
DQ55
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
CK0, CK0 --------- PLL*
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
CS CS
S1 RS1 -> CS: SDRAMs D18-D35
BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
A0-A13 RA0-RA13 -> A0-A13: SDRAMs D0- D35
RAS RRAS -> RAS: SDRAMs D0-D35
S0 RSO -> CS : SDRAMs D0-D17
VSS
DQS1
DQS3
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS5
DQS7
DM6/DQS15
DM5/DQS14
DM4/DQS13
DM1/DQS10
DM2/DQS11
DM3/DQS12
DM7/DQS16
* Wire per Clock Loading Table/Wiring Diagrams
V
DD
V
SS
D0-D35
D0-D35
V
DDQ
D0-D35
D0-D35
VREF
RS1
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. Address and control resistors should be 22 Ohms.
6. Each Chip Select and CKE pair alternate between decks for ther-
mal enhancement.
VDDID Strap: see Note 4
CAS RCAS -> CAS: SDRAMs D0-D35
CKE0 RCKE0 -> CKE: SDRAMs D0-D17
WE RWE -> WE: SDRAMs D0-D35
R
E
G
I
S
T
E
R
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D18
DQS
DQS
DQS
DQS
DQS
DQS
D19
D20
D21
D22
D23
D25
DQS
D24
CS
CS
CS
CS
CS
CS
CS
CS
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D28
D29
D30
D31
D32
D34
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D33
CS
CS
CS
CS
CS
CS
CS
CS
DM
DM
DM
DM
DM
DM
DM
DM
CB0
CB1
CB2
CB3
DQS
D8
CS DM
DQS8
DQS
D26
CS DM
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D17
CS DM
DM8/DQS17
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D35
CS DM
RESET
CKE1 RCKE1 -> CKE: SDRAMs D18-D35
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
V
DDSPD
Serial PD
A0
Serial PD
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 14 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 14 Rev. 0.5, 2003-12
3 Electrical Characteristics
3.1 Operating Conditions
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure t o absolute maximum rating conditions f or extended periods of time may
affect devi ce relia bility and exceeding on ly one of the values may cause irreversible damage to
the integrated circuit.
Table 6 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/ Test
Condition
min. typ. max.
Voltage on I/O pins relative to VSS VIN, VOUT –0.5 – VDDQ +
0.5 V–
Voltage on inputs relative t o VSS VIN –1 – +3.6 V –
Voltage on VDD supply relative to VSS VDD –1 – +3.6 V –
Voltage on VDDQ supply relative to VSS VDDQ –1 – +3.6 V –
Operating temperature (ambient) TA0–+70°C–
Storage temperature (plastic) TSTG -55 – +150 °C–
Power dissipation (per SDRAM component) PD–1–W–
Short circuit output current IOUT –50–mA–
Table 7 Electrical Chara cteristics and DC Operating Conditi ons
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK >166MHz
2)
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤166 MHz 3)
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz
2)3)
EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —
Supply Voltage, I/O Supply
Voltage VSS,
VSSQ
00V—
Input Reference Voltage VREF 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V4)
I/O Termination Voltage
(System) VTT VREF – 0.04 VREF + 0.04 V 5)
Input High (Logic1 ) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 8)
Input Low (Log ic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 8)
Input Voltage Level,
CK and CK Inputs VIN(DC) –0.3 VDDQ + 0.3 V 8)
Input Differential Voltage,
CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio 0.71 1.4 — 7)
Data Sheet 15 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 15 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Input Leakage Current II–2 2 µA Any input 0 V ≤VIN ≤VDD;
All other pins not under test
=0V
8)9)
Output Leakage Current IOZ –5 5 µA DQs are disa b led ;
0V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver IOH — –16.2 mA VOUT = 1.95 V
Output Low
Current, Normal Strength
Driver
IOL 16.2 — mA VOUT = 0.35 V
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up cu rre nt to the p ull -down current is sp ecified fo r th e sa me temperature and volt age, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Table 7 Electrical Chara cteristics and DC Operating Conditi ons (cont’d)
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 16 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 16 Rev. 0.5, 2003-12
Table 8 IDD Conditions
Parameter Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active /read/precharge; Burst Length = 4; see component data sheet. IDD1
Precharge Power-Down Stan dby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC =tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and contr ol inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Lengt h = 2; reads; continuous burst;
address and contr ol inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT =0mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Curr ent
tRC = tRFCMIN, burst refresh IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet. IDD7
Data Sheet 17 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 17 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Table 9 IDD Specification for –7
Part Number & Organization
HYS72D128500HR–7F–B
HYS72D128500HR–7–B
HYS72D128300GBR–7–B
HYS72D128321GBR–7–B
HYS72D256320GBR–7–B
Unit Note 1)2)
1) DRAM component currents only
2) Test condition for maximum values: VDD =2.7V, TA=10°C
1 GB 1 GB 1 GB 2 GB
×72 ×72 ×72 ×72
1 Rank 1 Rank 2 Ranks 2 Ranks
–7F –7 –7 –7
Symbol typ. max. typ. max. typ. max. typ. max.
IDD0 2158 2452 2028 2298 1587 1776 2586 2964 mA 3)
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
IDD1 2354 2746 2208 2568 1677 1911 2766 3234 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
IDD2P 430 448 430 448 430 448 484 520mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
IDD2F 736 808 736 808 736 808 1096 1240 mA 5)
IDD2Q 646 754 646 754 646 754 916 1132 mA 5)
IDD3P 538 610 538 610 538 610 700 844mA 5)
IDD3N 934 1042 934 1042 934 1042 1492 1708 mA 5)
IDD4R 2179 2460 2118 2388 1632 1821 2676 3054 mA 3)4)
IDD4W 2273 2554 2208 2478 1677 1866 2766 3144 mA 3)
IDD5 4499 5263 4278 4998 2712 3126 4836 5664 mA 3)
IDD6 414 468 414 468 414 468 451 560mA 5)
IDD7 5493 6376 5088 5898 3117 3576 5646 6564 mA 3)4)
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 18 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 18 Rev. 0.5, 2003-12
Table 10 IDD Specification for –6
Part Number & Organization
HYS72D128300GBR–6–B
HYS72D128321GBR–6–B
HYS72D256320GBR–6–B
Unit Note 1)2)
1) DRAM component currents only
2) Test condition for maximum values: VDD =2.7V, TA=10°C
1GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–6 –6 –6
Symbol typ. max. typ. max. typ. max.
IDD0 2350 2710 1873 2116 3016 3502 mA 3)
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
IDD1 2620 2980 2008 2251 3286 3772 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depen ding on
load conditions
IDD2P 484 502 484 502 538 574 mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
IDD2F 880 970 880 970 1330 1510 mA 5)
IDD2Q 736 862 736 862 1042 1294 mA 5)
IDD3P 628 700 628 700 826 970 mA 5)
IDD3N 1096 1222 1096 1222 1762 2014 mA 5)
IDD4R 2620 2980 2008 2251 3286 3772 mA 3)4)
IDD4W 2710 3070 2053 2296 3376 3862 mA 3)
IDD5 4690 5500 3043 3511 5356 6292 mA 3)
IDD6 475 523.6 475 523.6 520 617.2 mA 5)
IDD7 6310 7300 3853 4411 6976 8092 mA 3)4)
Data Sheet 19 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 19 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Table 11 IDD Specification for –5
Part Number & Organization
HYS72D128300GBR–5–B
HYS72D128321GBR–5–B
HYS72D256320GBR–5–B
Unit Note 1)2)
1) DRAM component currents only
2) Test condition for maximum values: VDD =2.7V, TA=10°C
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–5 –5 –5
Symbol typ. max. typ. max. typ. max.
IDD0 2680 3040 3436 3940 3436 3940 mA 3)
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
IDD1 2950 3400 3706 4300 3706 4300 mA 3)4)
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depen ding on
load conditions
IDD2P 698 734 752 824 752 824 mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
IDD2F 1184 1292 1724 1940 1724 1940 mA 5)
IDD2Q 986 1112 1328 1580 1328 1580 mA 5)
IDD3P 860 932 1076 1220 1076 1220 mA 5)
IDD3N 1400 1544 2156 2444 2156 2444 mA 5)
IDD4R 3040 3490 3796 4390 3796 4390 mA 3)4)
IDD4W 3130 3580 3886 4480 3886 4480 mA 3)
IDD5 5290 6190 6046 7090 6046 7090 mA 3)
IDD6 696.2 737.6 748.4 831.2 748.4 831.2 mA 5)
IDD7 7090 8260 7846 9160 7846 9160 mA 3)4)
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 20 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 20 Rev. 0.5, 2003-12
Table 12 AC Timing - Absolute Specifications –6/–5
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
DQ output access time from CK/CK tAC –0.6 +0.6 –0.7 +0.7 ns 2)3)4)5)
DQS output access time from CK/CK tDQSCK –0.5 +0.5 –0.6 +0.6 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
Clock Half Period tHP min. (tCL, tCH)min. (tCL, tCH)ns 2)3)4)5)
Clock cycle time tCK 5 12 — — ns CL = 3.0 2)3)4)5)
6 12 6 12 ns CL = 2.5 2)3)4)5)
7.5 12 7.5 12 ns CL = 2.0 2)3)4)5)
DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)
DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)
Control and Addr. input pulse width (each
input) tIPW 2.2 — 2.2 — ns 2)3)4)5)6)
DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)
Data-out high-impedance time from CK/CK tHZ –0.6 +0.6 –0.7 +0.7 ns 2)3)4)5)7)
Data-out low-impedance time from CK/CK tLZ –0.6 +0.6 –0.7 +0.7 ns 2)3)4)5)7)
Write command to 1st DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5)
DQS-DQ skew (DQS and associat ed DQ
signals) tDQSQ — +0.40 — +0.40 ns TFBGA 2)3)4)5)
— +0.40 — +0.45 ns TSOPII 2)3)4)5)
Data hold skew factor tQHS — +0.50 — +0.50 ns TFBGA 2)3)4)5)
— +0.50 — +0.55 ns TSOPII
2)3)4)5)
DQ/DQS output hold time tQH tHP –tQHS tHP –tQHS ns 2)3)4)5)
DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 — 0.35 — tCK 2)3)4)5)
DQS falling edge to CK setup time (write
cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5)
DQS falling edge hold time from CK (write
cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5)
Mode register set command cycle time tMRD 2— 2— tCK 2)3)4)5)
Write preamble setup time tWPRES 0— 0— ns
2)3)4)5)8)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)9)
Write preamble tWPRE 0.25 — 0.25 — tCK 2)3)4)5)
Address and control input setup time tIS 0.6 — 0.75 — ns fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns slow slew rate
3)4)5)6)10)
Address and cont ro l inpu t ho ld tim e tIH 0.6 — 0.75 — ns fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns slow slew rate
3)4)5)6)10)
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5)
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 21 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 21 Rev. 0.5, 2003-12
Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)
Active to Active/Auto-refresh command
period tRC 55 — 60 — ns 2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period tRFC 65 — 72 — ns 2)3)4)5)
Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)
Precharge command period tRP 15 — 18 — ns 2)3)4)5)
Active to Autoprecha rge delay tRAP 15 — 18 — ns 2)3)4)5)
Active bank A to Active bank B command tRRD 10 — 12 — ns 2)3)4)5)
Write recovery time tWR 15 — 15 — ns 2)3)4)5)
Auto precharge write recovery + precharge
time tDAL (tWR/tCK) +
(tRP/tCK)(tWR/tCK) +
(tRP/tCK)tCK 2)3)4)5)11)
Internal write to re ad command delay tWTR 1— 1— tCK 2)3)4)5)
Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5)
Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5)
Average Periodic Refresh Interval tREFI —7.8 —7.8 µs2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when th e device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning fr om Hi-Z to l ogic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest intege r. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 12 AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 22 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 22 Rev. 0.5, 2003-12
Table 13 AC Timing - Absolute Specifications –7/–7F
Parameter Symbol –7F –7 Unit Note/ Test
Condition
1)1)
DDR266 DDR266A
Min. Max. Min. Max.
DQ output access time from CK/CK tAC –0.75 +0.75 –0.75 +0.75 ns 2)2)3)3)4)4)5)5)
DQS output access time from CK/CK tDQSCK –0.75 +0.75 –0.75 +0.75 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
Clock Half Period tHP min. (tCL, tCH)min. (tCL, tCH)ns 2)3)4)5)
Clock cycle time tCK 7.5 12 7.5 12 ns CL = 2.5
2)3)4)5)
7.5 12 7.5 12 ns CL = 2.0
2)3)4)5)
DQ and DM input hold time tDH 0.5 — 0.5 — ns 2)3)4)5)
DQ and DM input setup time tDS 0.5 — 0.5 — ns 2)3)4)5)
Control and Addr. input pulse width (each input) tIPW 2.2 — 2.2 — ns 2)3)4)5)6)
DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)
Data-out high-impedance time from CK/CK tHZ –0.75 +0.75 –0.75 +0.75 ns 2)3)4)5)7)
Data-out low-impedance time from CK/CK tLZ –0.75 +0.75 –0.75 +0.75 ns 2)3)4)5)7)
Write command to 1st DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5)
DQS-DQ skew (DQS and associat ed DQ
signals) tDQSQ — +0.5 — +0.5 ns TFBGA
2)3)4)5)
— +0.5 — +0.5 ns TSOPII
2)3)4)5)
Data hold skew factor tQHS — +0.75 — +0.75 ns TFBGA
2)3)4)5)
— +0.75 — +0.75 ns TSOPII
2)3)4)5)
DQ/DQS output hold time tQH tHP – tQHS tHP – tQHS ns 2)3)4)5)
DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 — 0.35 — tCK 2)3)4)5)
DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5)
DQS falling edge hold time from CK (write cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5)
Mode register set command cycle time tMRD 2— 2— tCK 2)3)4)5)
Write preamble setup time tWPRES 0— 0— ns
2)3)4)5)8)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)9)
Write preamble tWPRE 0.25 — 0.25 — tCK 2)3)4)5)
Address and control input setup time tIS 0.9 — 0.9 — ns fast slew
rate
3)4)5)6)10)
0.9 — 0.9 — ns slow slew
rate
3)4)5)6)10)
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 23 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 23 Rev. 0.5, 2003-12
Address and cont ro l inpu t ho ld tim e tIH 0.9 — 0.9 — ns fast slew
rate
3)4)5)6)10)
1.0 — 1.0 — ns slow slew
rate
3)4)5)6)10)
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5)
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)
Active to Precharge command tRAS 45 120E+3 45 120E+3 ns 2)3)4)5)
Active to Active/A uto-refresh command period tRC 65 — 65 — ns 2)3)4)5)
Auto-refresh to Active/Auto-refresh command
period tRFC 75 — 75 — ns 2)3)4)5)
Active to Read or Write delay tRCD 20 — 20 — ns 2)3)4)5)
Precharge command period tRP 20 — 20 — ns 2)3)4)5)
Active to Autoprecha rge delay tRAP 20 — 20 — ns 2)3)4)5)
Active bank A to Active bank B command tRRD 15 — 15 — ns 2)3)4)5)
Write recovery time tWR 15 — 15 — ns 2)3)4)5)
Auto precharge wr it e recover y + prechar ge t ime tDAL (tWR/tCK) +
(tRP/tCK)(tWR/tCK) +
(tRP/tCK)tCK 2)3)4)5)11)
Internal write to re ad command delay tWTR 1— 1— tCK 2)3)4)5)
Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5)
Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5)
Average Periodic Refresh Interval tREFI —7.8 —7.8 µs2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when th e device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning fr om Hi-Z to l ogic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
Table 13 AC Timing - Absolute Specifications –7/–7F
Parameter Symbol –7F –7 Unit Note/ Test
Condition
1)1)
DDR266 DDR266A
Min. Max. Min. Max.
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Electrical Characteristics
Data Sheet 24 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 24 Rev. 0.5, 2003-12
11) For each of the terms, if not already an integer, round to the next highest intege r. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet 25 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 25 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
4SPD Contents
Table 14 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–5–B
Part Number & Organization
HYS72D128300GBR–5–B
HYS72D128321GBR–5–B
HYS72D256320GBR–5–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–5 –5 –5
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0C 0B 0C
5 Number of DIMM Ranks 01 02 02
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50
11 Error Correction Support (non- / ECC) 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 04 08 04
14 Error Checking SDRAM Width 04 08 04
15 tCCD [cycles] 01 01 01
16 Burst Length Sup ported 0E 0 E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 1C 1C 1C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 26 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 26 Rev. 0.5, 2003-12
26 tAC SDRAM @ CLmax -1 [ns] 50 50 50
27 tRPmin [ns] 3C 3C 3C
28 tRRDmin [ns] 28 28 28
29 tRCDmin [ns] 3C 3C 3C
30 tRASmin [ns] 28 28 28
31 Module Density per Rank 01 80 01
32 tAS, tCS [ns] 60 60 60
33 tAH, TCH [ns] 60 60 60
34 tDS [ns] 40 40 40
35 tDH [ns] 40 40 40
36 – 40 not used 00 00 00
41 tRCmin [ns] 37 37 37
42 tRFCmin [ns] 41 41 41
43 tCKmax [ns] 28 28 28
44 tDQSQmax [ns] 28 28 28
45 tQHSmax [ns] 50 50 50
46 not used 00 00 00
47 DIMM PCB Height 01 01 01
48 – 61 not used 00 00 00
62 SPD Revision 10 10 10
63 Checksum of Byte 0-62 E1 68 E2
64 JEDEC ID Code of Infi neon (1) C1 C1 C1
65 – 71 JEDEC ID Code of Infineon (2) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
Table 14 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–5–B
Part Number & Organization
HYS72D128300GBR–5–B
HYS72D128321GBR–5–B
HYS72D256320GBR–5–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–5 –5 –5
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0
Byte# Description HEX HEX HEX
Data Sheet 27 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 27 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
76 Part Number, Char 4 31 31 32
77 Part Number, Char 5 32 32 35
78 Part Number, Char 6 38 38 36
79 Part Number, Char 7 33 33 33
80 Part Number, Char 8 30 32 32
81 Part Number, Char 9 30 31 30
82 Part Number, Char 10 47 47 47
83 Part Number, Char 11 42 42 42
84 Part Number, Char 12 52 52 52
85 Part Number, Char 13 35 35 35
86 Part Number, Char 14 42 42 42
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code xx xx xx
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Man uf ac tur in g Dat e Week xx xx xx
95 – 98 Module Seria l Numb e r (1 - 4) xx xx xx
99 – 127 not used 00 00 00
Table 14 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–5–B
Part Number & Organization
HYS72D128300GBR–5–B
HYS72D128321GBR–5–B
HYS72D256320GBR–5–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–5 –5 –5
Label Code PC3200R–30331 PC3200R–30331 PC3200R–30331
JEDEC SPD Revision Rev. 1.0 Rev. 1.0 Rev. 1.0
Byte# Description HEX HEX HEX
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 28 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 28 Rev. 0.5, 2003-12
Table 15 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–6–B
Part Number & Organization
HYS72D128300GBR–6–B
HYS72D128321GBR–6–B
HYS72D256320GBR–6–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–6 –6 –6
Label Code PC2700R–25330 PC2700R–25330 PC2700R–25330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0C 0B 0C
5 Number of DIMM Ranks 01 02 02
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70
11 Error Correction Support (non- / ECC) 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 04 08 04
14 Error Checking SDRAM Width 04 08 04
15 tCCD [cycles] 01 01 01
16 Burst Length Sup ported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 0C 0C 0C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00
Data Sheet 29 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 29 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00
27 tRPmin [ns] 48 48 48
28 tRRDmin [ns] 30 30 30
29 tRCDmin [ns] 48 48 48
30 tRASmin [ns] 2A 2A 2A
31 Module Density per Rank 01 80 01
32 tAS, tCS [ns] 75 75 75
33 tAH, TCH [ns] 75 75 75
34 tDS [ns] 45 45 45
35 tDH [ns] 45 45 45
36 – 40 not used 00 00 00
41 tRCmin [ns] 3C 3C 3C
42 tRFCmin [ns] 48 48 48
43 tCKmax [ns] 30 30 30
44 tDQSQmax [ns] 28 28 28
45 tQHSmax [ns] 50 50 50
46 not used 00 00 00
47 DIMM PCB Height 00 00 00
48 – 61 not used 00 00 00
62 SPD Revision 00 00 00
63 Checksum of Byte 0-62 CA 51 CB
64 JEDEC ID Code of Infi neon (1) C1 C1 C1
65 – 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
Table 15 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–6–B
Part Number & Organization
HYS72D128300GBR–6–B
HYS72D128321GBR–6–B
HYS72D256320GBR–6–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–6 –6 –6
Label Code PC2700R–25330 PC2700R–25330 PC2700R–25330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 30 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 30 Rev. 0.5, 2003-12
76 Part Number, Char 4 31 31 32
77 Part Number, Char 5 32 32 35
78 Part Number, Char 6 38 38 36
79 Part Number, Char 7 33 33 33
80 Part Number, Char 8 30 32 32
81 Part Number, Char 9 30 31 30
82 Part Number, Char 10 47 47 47
83 Part Number, Char 11 42 42 42
84 Part Number, Char 12 52 52 52
85 Part Number, Char 13 36 36 36
86 Part Number, Char 14 42 42 42
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code xx xx xx
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Man uf ac tur in g Dat e Week xx xx xx
95 – 98 Module Seria l Numb e r (1 - 4) xx xx xx
99 – 127 not used 00 00 00
Table 15 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–6–B
Part Number & Organization
HYS72D128300GBR–6–B
HYS72D128321GBR–6–B
HYS72D256320GBR–6–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
–6 –6 –6
Label Code PC2700R–25330 PC2700R–25330 PC2700R–25330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
Data Sheet 31 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 31 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Table 16 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–7–B
Part Number & Organization
HYS72D128300GBR–7–B
HYS72D128321GBR–7–B
HYS72D256320GBR–7–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
reg reg reg
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80 80
1 Total number of Bytes in E2PROM 08 08 08
2 Memory Type (DDR = 07h) 07 07 07
3 Number of Row Addresses 0D 0D 0D
4 Number of Column Addresses 0C 0B 0C
5 Number of DIMM Ranks 01 02 02
6 Data Width (LSB) 48 48 48
7 Data Width (MSB) 00 00 00
8 Interface Voltage Levels 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 70 70 70
10 tAC SDRAM @ CLmax (Byte 18) [ns] 75 75 75
11 Error Correction Support (non- / ECC) 02 02 02
12 Refresh Rate 82 82 82
13 Primary SDRAM Width 04 08 04
14 Error Checking SDRAM Width 04 08 04
15 tCCD [cycles] 01 01 01
16 Burst Length Sup ported 0E 0E 0E
17 Number of Banks on SDRAM Device 04 04 04
18 CAS Latency 0C 0C 0C
19 CS Latency 01 01 01
20 Write Latency 02 02 02
21 DIMM Attributes 26 26 26
22 Component Attributes C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 75 75 75
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 32 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 32 Rev. 0.5, 2003-12
26 tAC SDRAM @ CLmax -1 [ns] 00 00 00
27 tRPmin [ns] 50 50 50
28 tRRDmin [ns] 3C 3C 3C
29 tRCDmin [ns] 50 50 50
30 tRASmin [ns] 2D 2D 2D
31 Module Density per Rank 01 80 01
32 tAS, tCS [ns] 90 90 90
33 tAH, TCH [ns] 90 90 90
34 tDS [ns] 50 50 50
35 tDH [ns] 50 50 50
36 – 40 not used 00 00 00
41 tRCmin [ns] 41 41 41
42 tRFCmin [ns] 4B 4B 4B
43 tCKmax [ns] 30 30 30
44 tDQSQmax [ns] 32 32 32
45 tQHSmax [ns] 75 75 75
46 not used 00 00 00
47 DIMM PCB Height 00 00 00
48 – 61 not used 00 00 00
62 SPD Revision 00 00 00
63 Checksum of Byte 0-62 86 0D 87
64 JEDEC ID Code of Infi neon (1) C1 C1 C1
65 – 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00
72 Module Manufacturer Location xx xx xx
73 Part Number, Char 1 37 37 37
74 Part Number, Char 2 32 32 32
75 Part Number, Char 3 44 44 44
Table 16 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–7–B
Part Number & Organization
HYS72D128300GBR–7–B
HYS72D128321GBR–7–B
HYS72D256320GBR–7–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
reg reg reg
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
Data Sheet 33 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 33 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
76 Part Number, Char 4 31 31 32
77 Part Number, Char 5 32 32 35
78 Part Number, Char 6 38 38 36
79 Part Number, Char 7 33 33 33
80 Part Number, Char 8 30 32 32
81 Part Number, Char 9 30 31 30
82 Part Number, Char 10 47 47 47
83 Part Number, Char 11 42 42 42
84 Part Number, Char 12 52 52 52
85 Part Number, Char 13 37 37 37
86 Part Number, Char 14 42 42 42
87 Part Number, Char 15 20 20 20
88 Part Number, Char 16 20 20 20
89 Part Number, Char 17 20 20 20
90 Part Number, Char 18 20 20 20
91 Module Revision Code xx xx xx
92 Test Program Revision Code xx xx xx
93 Module Manufacturing Date Year xx xx xx
94 Module Man uf ac tur in g Dat e Week xx xx xx
95 – 98 Module Seria l Numb e r (1 - 4) xx xx xx
99 – 127 not used 00 00 00
Table 16 SPD Codes for HYS72D[128/256 ][300/321/320]GBR–7–B
Part Number & Organization
HYS72D128300GBR–7–B
HYS72D128321GBR–7–B
HYS72D256320GBR–7–B
1 GB 1 GB 2 GB
×72 ×72 ×72
1 Rank 2 Ranks 2 Ranks
reg reg reg
Label Code PC2100R–20330 PC2100R–20330 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX HEX
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 34 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 34 Rev. 0.5, 2003-12
Table 17 SPD Codes for HYS72D128500HR–[ 7F/7]–B
Part Number & Organization
HYS72D128500HR–7F–B
HYS72D128500HR–7–B
1 GB 1 GB
×72 ×72
1 Rank 1 Rank
reg reg
Label Code PC2100R–20220 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type (DDR = 07h) 07 07
3 Number of Row Addresses 0D 0D
4 Number of Column Addresses 0C 0C
5 Number of DIMM Ranks 01 01
6 Data Width (LSB) 48 48
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 70 70
10 tAC SDRAM @ CLmax (Byte 18) [ns] 75 75
11 Error Correction Support (non- / ECC) 02 02
12 Refresh Rate 82 82
13 Primary SDRAM Width 04 04
14 Error Checking SDRAM Width 04 04
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM Device 04 04
18 CAS Latency 0C 0C
19 CS Latency 01 01
20 Write Latency 02 02
21 DIMM Attributes 26 26
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 75 75
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00
Data Sheet 35 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 35 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
26 tAC SDRAM @ CLmax -1 [ns] 00 00
27 tRPmin [ns] 3C 50
28 tRRDmin [ns] 3C 3C
29 tRCDmin [ns] 3C 50
30 tRASmin [ns] 2D 2D
31 Module Density per Rank 01 01
32 tAS, tCS [ns] 90 90
33 tAH, TCH [ns] 90 90
34 tDS [ns] 50 50
35 tDH [ns] 50 50
36 – 40 not used 00 00
41 tRCmin [ns] 3C 41
42 tRFCmin [ns] 4B 4B
43 tCKmax [ns] 30 30
44 tDQSQmax [ns] 32 32
45 tQHSmax [ns] 75 75
46 not used 00 00
47 DIMM PCB Height 00 00
48 – 61 not used 00 00
62 SPD Revision 00 00
63 Checksum of Byte 0-62 59 86
64 JEDEC ID Code of Infineon (1) C1 C1
65 – 71 JEDEC ID Code of Infineon (2 – 8) 00 00
72 Module Manufacturer Location xx xx
73 Part Numbe r, Char 1 37 37
74 Part Numbe r, Char 2 32 32
75 Part Numbe r, Char 3 44 44
Table 17 SPD Codes for HYS72D128500HR–[ 7F/7]–B
Part Number & Organization
HYS72D128500HR–7F–B
HYS72D128500HR–7–B
1 GB 1 GB
×72 ×72
1 Rank 1 Rank
reg reg
Label Code PC2100R–20220 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
SPD Contents
Data Sheet 36 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 36 Rev. 0.5, 2003-12
76 Part Numbe r, Char 4 31 31
77 Part Numbe r, Char 5 32 32
78 Part Numbe r, Char 6 38 38
79 Part Numbe r, Char 7 35 35
80 Part Numbe r, Char 8 30 30
81 Part Numbe r, Char 9 30 30
82 Part Number , Char 10 48 48
83 Part Number , Char 11 52 52
84 Part Number , Char 12 37 37
85 Part Number , Char 13 46 42
86 Part Number , Char 14 42 20
87 Part Number , Char 15 20 20
88 Part Number , Char 16 20 20
89 Part Number , Char 17 20 20
90 Part Number , Char 18 20 20
91 Module Revision Code xx xx
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 – 98 Module Serial Number (1 – 4) xx xx
99 – 127 not used 00 00
Table 17 SPD Codes for HYS72D128500HR–[ 7F/7]–B
Part Number & Organization
HYS72D128500HR–7F–B
HYS72D128500HR–7–B
1 GB 1 GB
×72 ×72
1 Rank 1 Rank
reg reg
Label Code PC2100R–20220 PC2100R–20330
Jedec SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
Data Sheet 37 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Package Outlines
Data Sheet 37 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
5 Package Outlines
Figure 4 Package Outline – Raw Card C DDR Registered DIMM HYS72D128300GBR–[5/6/7]–B
128.95
2.5
1
64.77
ø0.1
±0.1
ABC
4±0.1 0.1A
120.65
6.35
1.2795 x =
2.175
49.53
A
CB
133.35
92 B
±0.13
28.58
0.15 BA C
±0.13
±0.05
1
1.27 0.1 ABC
Detail of contacts
0.2
2.5 ±0.2
3.8
93
1.8
±0.1
C
0.1AB
17.8
184
10
1.27
0.4
C
±0.1
4 MAX.
Burr max. 0.4 allowed
3 MIN.
6.62
L-DIM-184-22-2
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Package Outlines
Data Sheet 38 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 38 Rev. 0.5, 2003-12
4 MAX.
1.27
C
±0.1
0.4
0.1
ø0.1
±0.1
2.5
±0.1
4
1
x95
C
64.77
AB
120.651.27 =
2.175 6.35
A
B CA
133.35
128.95
49.53
92
0.15 C
AB
±0.13
B
28.58
BA
0.1 C
1.8
C
1B
0.1 A
Detail of contacts
0.2
1.27
3.8 ±0.13
93
±0.2
2.5
±0.05
17.8
184
10
±0.1
3 MIN.
Burr max. 0.4 allowed
6.62
Figure 5 Package Outline – Raw Card B DDR Registered DIMM HYS72D128321HR–[5/6/7]–B
L-DIM-184-23-2
Data Sheet 39 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Package Outlines
Data Sheet 39 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Figure 6 Package Outline – Raw Card D DDR Registered DIMM HYS72D256320GBR–[5/6/7]–B
128.95
133.35 0.15 ABC
AA
6.62
6.35
2.175
49.53
92
±0.1
2.5 ø0.1 C
AB
1
64.77
±0.13
30.48
B
±0.1
40.1 BA C
4 MAX.
C
0.4 ±0.1
1.27
1.8 ±0.1 0.1 BAC
±0.13
3.8
3 MIN.
17.8
10
93 184
Burr max. 0.4 allowed
Detail of contacts
0.2
1.27 ±0.05
10.1 ABC
±0.2
2.5
L-DIM-184-25
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Package Outlines
Data Sheet 40 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Data Sheet 40 Rev. 0.5, 2003-12
192
A
93 184
128.95
A
0.1
A
BC
133.35
4 MAX.
0.15 BA C
1.27
0.4
BC
±0.13
30.48
±0.1
6.35
±0.1
2.5
64.77
ø0.1ABC 2.175
6.62
49.53
±0.1
4
0.1
±0.1
1.8 A CB
3.8
±0.13
3 MIN.
17.8
10
1.27 1±0.05 A
0.1 CB
Detail of contacts
0.2
2.5
±0.2
120.65x95 1.27 =
1)
1)
Burr max. 0.4 allowed
1) On ECC modules only
Figure 7 Package Outline – Raw Card M DDR Registered DIMM HYS72D128500HR–[7/7F]–B
L-DIM-184-12-3
Data Sheet 41 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Application Note
Data Sheet 41 Rev. 0.5, 2003-12
6 Application Note
Power Up and Power Manageme nt on DDR Registered DIMMs
(according to JEDEC ballot JC-42.5 Item 1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a system-
generated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z st ate (eliminating risk of high current dissipa tions
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also pe rm its the sys te m a n d DI MM
clocks to be stopped dur ing memory Self Refr esh operation, while e nsuring that the SDRAMs sta y in Self Refresh
mode.
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is s topped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM .
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-
bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Table 18 The function for RESET is as follows:1)
1) X : Don’t care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling
Register Inputs Register Outputs
RESET CK CK Data in (D) Data out (Q)
H Rising Falling H H
H Rising Falling L L
H L or H L or H X Qo
H High Z High Z X Illegal input conditions
L X or Hi-Z X or Hi-Z X or Hi-Z L
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Application Note
Data Sheet 42 Rev. 0.5, 2003-12
Data Sheet 42 Rev. 0.5, 2003-12
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input
condition forces all r egister out puts to a low stat e independent of the condition on the register inputs (data and
clock), ensuring th at CKE is at a stable low-level at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL
operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be
affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.
Once a stable clock is received at the DIMM PLL, the required PLL s tabilization time (assuming power to the
DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the
PLL), the DDR SDRAM requires 200 µsec prior to SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally
this would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs
to be consistent with the stat e of the register outputs.
5. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive
commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock
edge is not required (during this period, register inputs must remain stable).
6. The system must maintain sta ble register inputs until normal r egister operatio n is attained. The re gisters have
an activation t ime that allows th eir clock receivers, data inpu t receivers, and outp ut drivers sufficient time to be
turned on and become stable. During this time the system must maintain the valid logic levels described in step
5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee
that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from
asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input
signal, is specified in the regi ster and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-
pproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain dat a with out extern al cl ockin g.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. The system applies Self Refresh entry command. (CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→
High)
Note:Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the excep tio n of CKE.
2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,
independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other
control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is
asynchronous, setting the RESET timing in relation to a sp ecific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address
Data Sheet 43 Rev. 0.5, 2003-12
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Application Note
Data Sheet 43 Rev. 0.5, 2003-12
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET
deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the
address signals must maintain valid levels after RESET low has been applied. It is highly recommended that
CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered of f) — Optional
1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL
operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be
affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.
Once a stable clock is received at the DIMM PLL, the required PLL s tabilization time (assuming power to the
DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence
(ideally this would be a ‘NOP Deselect’ command). A secon d option is to a pply low levels o n all of th e register
inputs, to be consistent with the state of t he register outputs.
3. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive
commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is
not required (during this period, register inputs must remain stable).
4. The system must maintain sta ble register inputs until normal r egister operatio n is attained. The re gisters have
an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned
on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It
is also a fun ctional requirement that the registe rs maintain a low stat e at the CKE outputs to guarantee that the
DDR SDRAMs continue to receive a low level on CKE. Register activa tion ti me (t (ACT) ), from asynchronous
switching of RESET from low to high until the registers are stable and ready to accept an input signal, is
specified in the registe r and DIMM do-umentation.
5. System can begin the JEDEC-defi ned DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running incre ases power consumption from the on-DIMM PLL during se lf refresh, this
is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command. (CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note:Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRA M ar e Do n’t Ca re s — with th e exc ep tio n of CKE.
2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,
independent of th e cond ition on th e data and clock registe r input s, a nd ensure s that CKE is a stable low-le ve l
at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET
deactivate ti me of the register (t (INACT) ). The deactivat e time descr ibes the t ime in which the clo cks and the
control and the address signals must maintain valid levels after RESET low has been applied. It is highly
recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
HYS72D[128/256][300/320/321/500][GBR/HR]-[5/6/7/7F]-B
Registered Double Data Rate SDRAM Module
Application Note
Data Sheet 44 Rev. 0.5, 2003-12
Data Sheet 44 Rev. 0.5, 2003-12
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequenc e (ide ally this
would be a ‘NOP Desele ct’ command). A second option is to app ly low levels on a ll of the regist er inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive
commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge
(during this period, register inputs must continue to remain stable).
3. The system must maintain sta ble register inputs until normal r egister operatio n is attained. The re gisters have
an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned
on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It
is also a functional re quirement that the registers maint ain a low state at the CKE outputs in order to guarantee
that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous
switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT
) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this ap plication note. In the case where RESET remains high and the clocks are powered off ,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Published by Infineon Technologies AG
http://www.infineon.com
