TEMIC Semiconductors U6815BM Dual Hex DMOS Output Driver with Serial Input Control Description The U6815BM is a fully protected driver interface designed in 0.8-um BCDMOS technology. It is used to control up to 12 different loads by a microcontroller in automotive and industrial applications. Each of the 6 high-side and 6 low-side drivers is capable to drive currents up to 600 mA. The drivers are free configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors Features @ Six high-side and six low-side drivers @ Outputs free configurable as switch, half bridge or H- bridge @ Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors @ 0.6 A continuous current per switch @ Low-side: Rpson < 1.5 Q vs. total temperature range @ High-side: Rpson < 2.0 Q vs. total temperature range Ordering Information can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Built-in protection in terms of short-circuit conditions, over-temperature, under- and overvoltage. Various diagnosis functions and a very low quiescent current in stand-by-mode opens a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for demanding up-market applications. @ Very low quiescent current Is < 20 wA in stand-by mode Outputs short-circuit protected Overtemperature prewarning and protection Under- and overvoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power supply fail Serial data interface SO28 power package U6815BM-FL S028 Power package Rev. A2, 14-Sep-99 1 (13) Preliminary InformationU6815BM TEMIC Semiconductors Block Diagram MALL ont Register ut Register ity rial CoO EEE EES RHE sR RE: 2 1 =1 Figure 1. Block diagram 2 (13) Preliminary Information Rev. A2, 14-Sep-99TEMIC Semiconductors U6815BM Pin Description LS6 DI CLK CS GND GND GND GND VCC DO INH LSI HS1 2] (3) la] [5] [el (7) is) (9) fil ny 2] 3) [4 HSS HS4 LS4 VS GND GND GND GND VS_ LS3 HS3 HS2 LS2 14167 Figure 2. Pinning 1 LS5 Low-side driver output 5; Power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short circuit protection; diagnosis for short and open load 2 HS5 High-side driver output 5; Power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short circuit protection; diagnosis for short and open load 3 HS4 High-side driver output 4; see Pin 2 4 LS4 Low-side driver output 4; see Pin 1 5 VS Power supply output stages HS1, HS2 and HS3, internal supply; external connection to Pin 10 necessary; add blocking capacitor as close as possible to Pin 5, 10 and GND. Recommended value: 22 UWF to 100 UF electrolytic in parallel to 100 nF ceramic (depending on EMI requirements). 6,7,89 GND Ground; reference potential; internal connection to Pin 20 23; cooling tab, to reduce thermal resistance place cooling areas on PCB close to these pins. 10 VS Power supply output stages HS4, HS5 and HS6 11 LS3 Low-side driver output 3; see Pin 1 12 HS3 High-side driver output 3; see Pin 2 13 HS2 High-side driver output 2; see Pin 2 14 LS2 Low-side driver output 2; see Pin 1 15 HS1 High-side driver output 1; see Pin 2 16 LS1 Low-side driver output 1; see Pin 1 17 INH Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operating 18 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit sta- tus information to the wC (LSB is transferred first). Output will remain tristated, unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 19 VCC __ |Logic supply voltage (5 V); add blocking capacitor as close as possible to Pin 19 and GND. Recom- mended value: 10 uF electrolytic in parallel to 100 nF ceramic. 20, 21, GND Ground; see Pin 6 9 22 23 24 CS Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 25 CLK | Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fyyax = 2 MHz) 26 DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the con- trol device; DI expects a 16-bit control word with LSB being transferred first 27 LS6 Low-side driver output 6; see Pin 1 28 HS6 High-side driver output 6; see Pin 2 Rev. A2, 14-Sep-99 3 (13) Preliminary InformationU6815BM TEMIC Functional Description Serial Interface co [ aio FLU UU UU UU UU UU UU uu DI COX DIX DIX DIX DIK DSK DEX DIK DEX DIX DIK DIK DIIXDISXDIGADI bo COX DIX BAX DIX DIK DSK DEX DTK DEX DIK DIK DIK PIZXDISXDIGKDI 14168 Figure 3. Data transfer Data transfer starts with the falling edge of the CS signal. When CS is high, Pin DO is in tristate condition. This Data must appear at DI synchronized to CLK and are output is enabled on the falling edge of CS. Output data accepted on the falling edge of the CLK signal. LSB will change their state with the rising edge of CLK and (bit O, SRR) has to be transferred first. Execution of new __ stay stable until the next rising edge of CLK appears. LSB input data is enabled on the rising edge of the CS signal. _ (bit 0, TP) is transferred first. Input Data Protocol 0 SRR Status register reset (high = reset; the bits PSF, SCD and Overtemperature Shutdown in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 LS4 See LS1 8 HS4 See HS1 9 LS5 See LS1 10 HS5 See HS1 11 LS6 See LS1 12 HS6 See HS1 13 OLD Open load detection (low = on) 14 SCT Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high / low = 100 ms/ 12.5 ms, overvoltage shutdown delay high / low = 15 ms / 3.5 ms 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digitalpart is still powered) After power on reset the input register has the following status: H H H L L L L L L L L L L L L L 4 (13) Rev. A2, 14-Sep-99 Preliminary InformationTEMIC Semiconductors U6815BM Output Data Protocol TP Temperature prewarning: high = warning (overtemperature shut down see remark below) 1 Status LS1 Normal operation: high = output is on, low = output is off Open load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 2 Status HS1 Normal operation: high = output is on, low = output is off Open load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 Status LS4 Description see LS1 8 Status HS4 Description see HS1 9 Status LS5 Description see LS1 10 Status HS5 Description see HS1 11 Status LS6 Description see LS1 12 Status HS6 Description see HS1 13 SCD Short circuit detected: set high, when at least one output is switched off by a short circuit condition 14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17). High = standby, low = normal operation 15 PSF Power supply fail: over- or undervoltage at Pin Vs detected Remark: Bit 0 to 15 = high: overtemperature shutdown Power Supply Fail In case of over/ undervoltage at pin Vs, an internal timer is started. When the overvoltage delay time (taov), programmed by the SCT Bit, or the undervoltage delay time (tquvy) is reached, the Power Supply Fail bit (PSF) in the Output Register is set and all outputs are disabled. After the over- / undervoltage occured the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR bit in the Input Register. Open Load Detection If the Open Load Detection bit (OLD) is set to low, a pull up current for each high side switch and a pull down current for each low side switch is turned on (Open load detection current Iys1-6, Itsi_6). If Vys-Vusi-_6 or Vis1_-6 18 lower than the open load detection threshold (open load condition) the corresponding bit of the output in the Output Register is set to high. Switching on an output stage with OLD bit set to low disables the open load function for this output. Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold Tjpw set, the temperature prewarning bit (TP) in the Output Register is set. When temperature falls below the thermal prewarning threshold Tjpw reset. the bit TP is reset. The TP bit can be read without transferring a complete 16 bit data word: with CS = low and CLK = high the state of TP appears at Pin DO. After the uC has read this information CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature exceeds the thermal shutdown threshold Tj switch oft, the outputs are disabled and all bits in the Output Register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold T; switch on and writing a high to the SRR bit in the Input Register. Thermal prewarning and shutdown threshold have hysteresis. Short Circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (hys1-6, ILsi1_6) are reached. Simultaneously an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tgsq) programmed by the short circuit timer bit (SCT) is reached. Additionally the short circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. Rev. A2, 14-Sep-99 5 (13) Preliminary InformationU6815BM TEMIC Absolute Maximum Ratings All values refer to GND pins Supply voltage Pins 5, 10 Vvs 0.3 to 40 Vv Supply voltage t<0.5 s; Is >-2 A Pins 5, 10 Vvs -1 Vv Supply voltage difference IVs pins Vs Piniol AVvs 150 mV Supply current Pins 5, 10 Ivs 1.4 A Supply current t< 200 ms Pins 5, 10 Ivs 2.6 A Logic supply voltage Pin 19 Vvcc 0.3 to 7 Vv Input voltage Pin 17 VINH 0.3 to 17 Vv Logic input voltage Pins 24 to 26 Vp. Vc_K. Ves -0.3 to Vvcc + 0.3 Vv Logic output voltage Pin 18 Vpo -0.3 to Vvcc + 0.3 Vv Input current Pins 17, 24 to 26 Tint Ipt. IeiK. Ics 10 to +10 mA Output current Pin 18 Ipo 10 to +10 mA Output current Pins 1 to 4, 11 to 16, I. s1 to Ins6 Internal limited, see mA Pins 27 and 28 Tys1 to Lus6 output specification Junction temperature range Tj 40 to 150 C Storage temperature range TstG 55 to 150 C Operating Range All values refer to GND pins Supply voltage Pins 5, 10 Vs Vuv 2 40 Vv Logic supply voltage Pin 19 Vec 4.5 5 5.5 Vv Logic input voltage Pin 17, 24 to 26 VinuVpi Vc_k. Ves -0.3 Vvcc Vv Serial interface clock frequency Pin 25 folk 2 MHz Junction temperature range Tj 40 150 C ') Threshold for undervoltage detection Thermal Resistance All values refer to GND pins Junction pin Measured to GND Rinse 25 K/W Pins 6 to 9 and 20 to 23 Junction ambient Rina 65 K/W 6 (13) Rev. A2, 14-Sep-99 Preliminary InformationTEMIC Semiconductors U6815BM Noise and Surge Immunity Conducted interferences ISO 7637-1 level 4 Interference Suppression VDE 0879 Part 3 level 6 ESD (Human Body Model) MIL-STD-883D Method 3015.7 2kV ESD (Machine Model) EOS / ESD S 5.2 150 V Electrical Characteristics 7.5 V<Vs5<40 V; 4.5 V < Vec<5.5 V; INH = High; 40C < Tj< 150C; unless otherwise specified, all values refer to GND pins. Current Consumption Quiescent current (VS) Vvs < 16 V, INH or Ivs 40 pA bit SI = low Pins 5, 10 Quiescent current (VCC) |4.5 V<Vvycc <5.5 V, Ivec 20 pA INH or bit SI=low Pin 19 Supply current (VS) Vvs < 16 V normal operating, Ivs 0.8 1.2 mA all output stages off, Pins 5, 10 Supply current (VS) Vvs < 16 V normal operating, Ivs 10 mA all output stages on no load Pins 5, 10 Supply current (VCC) 4.5 V<Vvcc <5.5 V, Ivcc 150 pA normal operating Pin 19 Internal Oscillator Frequency Frequency (Time-base for fosc 19 45 kHz delay timers) Over- and Undervoltage Detection, Power-On Reset Power-on reset thresh- Pin 19 Vvcc 3.4 3.9 4.4 Vv old Power-on reset delay After switching on Vcc taPor 30 95 160 ps time Undervoltage detection Pins 5, 10 Vuv 5.5 7.0 Vv threshold Undervoltage detection Pins 5, 10 AVuvy 0.4 Vv hysteresis Undervoltage detection tauv 10 20 ms delay Overvoltage detection Pins 5, 10 Vov 18 22.5 Vv threshold Overvoltage detection Pins 5, 10 AVov 1 Vv hysteresis Overvoltage detection Input register taov 7 21 ms delay bit 14 (SCT) = high Overvoltage detection Input register taov 1.75 5.25 ms delay bit 14 (SCT) = low Rev. A2, 14-Sep-99 7 (13) Preliminary InformationU6815BM TEMIC Electrical Characteristics (continued) Thermal Prewarning and Shutdown Thermal prewarning Tipwset 125 145 165 C Thermal prewarning Tjpwreset 105 125 145 C Thermal prewarning AT pw 15 20 25 K hysteresis Thermal shutdown Tj switch 150 170 190 C off Thermal shutdown Tj switch 130 150 170 C on Thermal shutdown AT; switch 15 20 25 K hysteresis off Ratio thermal shutdown / Tj switch off/ 1.05 1.17 thermal prewarning Tjpw set Ratio thermal shutdown / Tj switch on/ 1.05 1.2 thermal prewarning TjPW reset Output Specification (LS1 LS6, HS1 HS6) 71.5<Vys<Vov On resistance Tout = 600 mA Pins 1, 4, 11, 14, 16, 27 Rps on 1.5 Q On resistance Tou: = 600 mA Pins 2, 3, 12, 13, 15, 28 Rps on H 2.0 Q Output leakage current Vis1-6= 40 V all output stages off Ih s1-6 10 vA Pins 1, 4, 11, 14, 16, 27 Output leakage current Vus16=0V all output stages off Ts1-6 -10 vA Pins 2, 3, 12, 13, 15, 28 Inductive shutdown energy | Pins 1, 11-16, 27, 28 Woutx 8 mJ Output voltage edge steep- Pins 1+, 11-16, 27, 28 dvV- 50 200 400 mV/us ness Ls1-6/dt dv- Hs1-6/dt Overcurrent limitation and | Pins 1, 4, 11, 14, 16, 27 Th s1-6 650 950 1250 mA shutdown threshold Overcurrent limitation and | Pins 2, 3, 12, 13,15, 28 THs1-6 1250 950 650 mA shutdown threshold Overcurrent shutdown Input register tasa 710 100 140 ms delay time bit 14 (SCT) = high Overcurrent shutdown Input register tasa 8.75 17.5 ms delay time bit 14 (SCT) = low Open load detection current | Input register bit 13 (OLD) Is1-6 60 200 pA =low, output off Pins 1, 4, 11, 14, 16, 27 Open load detection current | Input register bit 13 (OLD) THs1-6 150 -30 pA =low, output off Pins 2, 3, 12, 13, 15, 28 Open load detection current Irs16/ 1.2 ratio Tys1-6 8 (13) Rev. A2, 14-Sep-99 Preliminary InformationTEMIC Semiconductors U6815BM Electrical Characteristics (continued) Open load detection thresh- | Input register bit 13 (OLD) VLS1-6 60 200 pA old =low, output off Pins 1, 4, 11, 14, 16, 27 Open load detection thresh- | Input register bit 13 (OLD) Vvs- 1 4 Vv old =low, output off VHSs1-6 Pins 2, 3, 12, 13, 15, 28 Output Switch on delay | RLoad = 1 kQ. tdon 0.5 ms Output Switch off delay) | RLoad = 1 kQ tdon 1 ms Inhibit Input Input voltage low level Pin 17 Vit |9.3xVvcc Vv threshold Input voltage high level Pin 17 Vin 0.7xVycc V threshold Hysteresis of input voltage Pin 17 AV} 100 700 mV Pull-down current Vinn=Vvcc Pin 17 Ipp 10 80 pA Serial Interface Logic Inputs DI, CLK, CS Input voltage low level Pins 24-26 VIL 0.3xVycc Vv threshold Input voltage high level Pins 24-26 Vin 0.7xVycc V threshold Hysteresis of input voltage Pins 24-26 AV{ 50 500 mV Pull down current Pin DI, Vp. Veik = Vcc 2 50 pA CLK Pins 25, 26 Pull up current Pin CS Vcs=0V Pin 24 50 2 pA Serial Interface Logic Output DO Output voltage low level Io. = 3 mA Pin 18 VDOL 0.5 Vv Output voltage high level Ip, =-2 mA Pin 18 Vpou | Vvec-1V Vv Leakage current Ves = Vec,0 V< Vpo< Vvcc Ipo -10 10 pA (tristate) Pin 18 !) Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. Rev. A2, 14-Sep-99 Preliminary Information 9 (13)U6815BM TEMIC Semiconductors Electrical Characteristics (continued) Serial Interface timing DO enable after CS falling edge | Cpo = 100 pF 1 tENDO 200 ns DO disable after CS rising edge Cpo = 100 pF 2 tpIspo 200 ns DO fall time Cpo = 100 pF - toot 100 ns Vpo = 0.8 x Vec to 0.2 x Vcc DO rise time Cpo = 100 pF - toor 100 ns Vpo = 0.2 x Vec to 0.8 X Vcc DO valid time Cpo = 100 pF 10 tpoval 200 ns Vpo < 0.2 Vpo > 0.8 Vcc CS setup time 4 tcssethl 225 ns CS setup time 8 tcssetih 225 ns CS high time 9 tcsh 500 ns CLK high time 5 tCLKh 225 ns CLK low time 6 tCLKI 225 ns CLK period time - tcLKp 500 ns CLK setup time tcLKSeth! | 225 ns CLK setup time 3 tcLKSetih | 225 ns DI setup time 12 tpIHold 40 ns Inputs DI, CLK, CS: High level = 0.7 x Vcc, Low level = 0.3 x Vcc Output DO: High level = 0.8 x Vcc, Low level = 0.2 x Vcc Figure 4. Serial interface timing diagram with chart numbers 10 (13) Preliminary Information Rev. A2, 14-Sep-99TEMIC Semiconductors U6815BM Application Circuit Vec U5021M WATCHDOG I Veatt 13V Osc Control logic Thermal P-ON- Vec 5V Figure 5. Application circuit Application Notes It is strongly recommended to connect the blocking capacitors at Vcc and Vs as close as possible to the power supply and GND pins. Recommended value for capacitors at Vs: electrolythic capacitor C > 22 WF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, noise and surge immunity efforts. Recommended value for capacitors at Vcc: electrolythic capacitor C > 10 uF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. Rev. A2, 14-Sep-99 11 (13) Preliminary InformationU6815BM TEMIC Package Information Package SO28 9.15 Dimensions in mm 18.05 8.65 i A AABRARABARS S / a6 OURUGOURUUeER 1 14 13033 12 (13) Rev. A2, 14-Sep-99 Preliminary Information