MT9V126IA3XTC - ON SEMICONDUCTOR

Products and specifications discussed herein are subject to change by Aptina without notice.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Features

Aptina Confidential and Proprietary

PDF : 1548164444/Source:0992813814 Aptina reserves the right to change products or specifications without notice.

1/4-Inch Color CMOS NTSC/PAL Digital Image SOC with

Distortion Correction and Overlay Processor

MT9V126 Data Sheet

For the latest data sheet, refer to Aptina’s Web site: www.aptina.com

Features

• Low-power CMOS image sensor with integrated

image flow processor (IFP) and video encoder

• 1/4-inch optical format, VGA resolution (640H x

480V)

• ±2.5% additional columns and rows to compensate

for lens alignment tolerances

• Integrated lens distortion correction

• Overlay generator for dynamic bitmap overlay

• Integrated video encoder for NTSC/PAL with overlay

capability and 10-bit I-DAC

• Integrated microcontroller for flexibility

• On-chip image flow processor performs

sophisticated processing, such as color recovery and

correction, sharpening, gamma, lens shading

correction, on-the-fly defect correction, auto white

balancing, and auto exposure

• Auto black level calibration

• 10-bit, on-chip analog-to-digital converter (ADC)

• Internal master clock generated by on-chip phase-

locked loop (PLL)

• Two-wire serial programming interface

• Interface to low-cost Flash through SPI bus

• High-level host command interface

• Stand alone operation support

• Comprehensive tool support for overlay generation

and lens correction setup

• Development system with DevWare

• Overlay generation and compilation tools

Applications

• Automotive rearview camera and side mirror

• Blind spot and surround view

See “Ordering Information” on page 3.

See details of new features on page 3.

Key parameters are continued on next page.

Table 1: Key Parameters

Parameter Typical Value

Pixel size

and type

5.6μm x 5.6μm active pinned-photodiode

with high-sensitivity mode for low-light

conditions

Sensor format 680H x 512V (includes ±2.5% of rows and

columns for lens alignment)

NTSC output 720H x 480V

PAL output 720H x 576V

Imaging area Total array size: 3.584mm x 2.688mm

Optical format ¼-inch

Frame rate 50/60 fields/sec

Sensor scan mode Progressive scan

Color filter array RGB standard Bayer

Shutter type Electronic rolling shutter (ERS)

Automatic Functions Exposure, white balance, black level

offset correction, flicker avoidance, color

saturation control, on-the-fly defect

correction, aperture correction

Programmable

Controls

Exposure, white balance, horizontal and

vertical blanking, color, sharpness,

gamma correction, lens shading

correction, horizontal and vertical image

flip, zoom, windowing, sampling rates,

GPIO control

Lens distortion

correction1Maximum lens distortion supported up

to 25%

Flexible algorithm that can be calibrated

for many wide-angle lenses through

software tools

Perspective correction

PDF : 1548164444/Source:0992813814 Aptina reserves the right to change products or specifications without notice.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Applications

Aptina Confidential and Proprietary

Notes: 1. Lens distortion correction and graphical overlay is available only in CCIR656 output format.

2. Analog output enabled; parallel output disabled.

Table 2: Key Parameters (continued)

Parameter Typical Value

Overlay Support1Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the

following features:

•Overlay Size 360 x 480 pixel rendered into 720 x 480 pixel display format

•Up to four (4) overlays may be blended simultaneously

•Selectable readout: Rotating order user selected

•Dynamic scenes by loading pre-rendered frames from external memory

•Palette of 32 colors out of 64,000

•8 colors per bitmap

•Blend factor dynamically programmable for smooth transitions

•Fast Update rate of up to 30 fps

•Every bitmap object has independent x/y position

•Statistic Engine to calibrate optical alignment

•Number Generator

External Overlay Processing Support Digital input to on-chip NTSC encoder allows for external overlay, processing by a

DSP, or FPGA

Windowing Programmable to any size

Max analog gain 0.5–16x

ADC 10-bit, on-chip

Output interface Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output

Output data formats1Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB

Data rate

Parallel: 27 MB/s

NTSC: 60 fields/sec

PAL: 50 fields/sec

Control interface Two-wire I/F for register interface plus high-level command exchange. SPI port to interface

to external memory to load overlay data, register settings, or firmware extensions.

Input clock for PLL 27 MHz

SPI Clock Frequencies 4.5 - 9.0 - 18 MHz, programmable

Supply voltage

Analog: 2.8V ±5%

Core: 1.8V ±5%

IO: 2.8V ±5%

Power consumption Full resolution at 60 fps: <350mW2

Package 63-BGA, 9mm x 9mm, 1mm pin pitch

Ambient temperature Operating: –40 °C to 105°C

Functional: –40°C to +85°C

Storage: –50°C to +150°C

Dark Current < 200e/s at 60°C with a gain of 1

Fixed pattern noise Column < 2%

Row < 2%

Responsitivity 11.9 V/lux-s at 550nm

Signal to noise ratio (S/N) 45dB

Pixel dynamic range 74.6 dB

PDF : 1548164444/Source:0992813814 Aptina reserves the right to change products or specifications without notice.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Ordering Information

Aptina Confidential and Proprietary

Ordering Information

New Features

Integrated Lens Distortion Correction

• Eliminates expensive DSP for image correction

• Can be calibrated for wide-angle lenses of up to 180 degree horizontal FOV (field of

view)

• Distortion correction for up to 25% distortion in FOV

• Perspective correction

– View from elevated angle

Integrated Video Encoder for PAL/NTSC with Overlay Capability

• Composite analog output (NTSC/PAL)

• 8-bit parallel digital output ITU-R BT.656 format

• Raw Bayer format

• Digital input to on-chip NTSC encoder to allow additional processing functions by

external DSP or FPGA

On-Chip Overlay Generator

• Static and dynamic overlay graphics with four overlay planes plus number plane

• Support for serial SPI memory up to 16 megabytes

•Number generator

• Overlay blending and x/y positioning

• Overlay position adjustment and statistics engine to calibrate overlay

• Overlay support utilizes SPI interface to load overlay data from external

Serial Flash/EEPROM to support the following features:

– Overlay size 360 x 480 pixel rendered into 720 x 480 pixel display format

– Up to four overlays may be blended simultaneously

– Selectable readout: rotating order user selected

– Dynamic scenes by loading pre-rendered frames from external memory

– Palette of 32 colors out of 64,000

– Eight colors per bitmap

– Blend factor dynamically programmable for smooth transitions

– Fast update rate of up to 30 fps

– Every bitmap object has independent x/y position

– Statistics engine to calibrate optical alignmentExternal overlay processing sup-

ports digital input to on-chip NTSC encoder; this enables external overlay process-

ing by a DSP or FPGA

Table 3: Available Part Numbers

Part Number Description

MT9V126IA3XTC ES 63-ball BGA Pb-free engineering sample

MT9V126IA3XTC 63-ball BGA (Pb-free)

MT9V126IA3XTCD ES Demo kit with DevWare setup tool software for overlay lens distortion correction

MT9V126IA3XTCH ES Headboard (requires demo kit)

PDF : 1548164444/Source:0992813814 Aptina reserves the right to change products or specifications without notice.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Table of Contents

Aptina Confidential and Proprietary

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Integrated Lens Distortion Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Integrated Video Encoder for PAL/NTSC with Overlay Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

On-Chip Overlay Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Internal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Crystal Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Detailed Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Sensor Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Image Flow Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

NTSC/PAL Test Pattern Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

CCIR-656 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Black Level Subtraction and Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Positional Gain Adjustments (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

The Correction Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Color Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Color Correction and Aperture Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

RGB to YUV Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Color Kill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

YUV Color Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

YUV-to-RGB/YUV Conversion and Output Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Output Format and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

YUV/RGB Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Uncompressed 10-Bit Bypass Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Readout Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

External Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Multicamera Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Auto-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Flash Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Host Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Supported SPI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Supported SPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Host Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Host Command Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

PDF : 1548164444/Source:0992813814 Aptina reserves the right to change products or specifications without notice.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Table of Contents

Aptina Confidential and Proprietary

Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Set Parallel Mode - Normal (Overlay i656). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Summary of Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Slave Address/Data Direction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Message Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Typical Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Single READ from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Single Write to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Integrated Lens Distortion Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Lens Distortion Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Lens Distortion Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Perspective View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

External Memory Speed Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Character Generator Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Composite Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

NTSC or PAL with External Image Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Single-Ended and Differential Composite Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Parallel Output (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Parallel Input (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Reset and Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Floating Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Power Consumption, Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

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Table of Contents

Aptina Confidential and Proprietary

Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Package and Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Figures

Aptina Confidential and Proprietary

List of Figures

Figure 1: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 2: System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 3: Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 4: Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 5: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 6: Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 7: Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 8: Pixel Color Pattern Detail (top right corner). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 9: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 10: Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 11: Color Bar Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 12: Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 13: Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 14: Auto-Config Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 15: Flash Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 16: Usage Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 17: Host Mode with Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 18: Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 19: External Overlay System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 20: Multicamera System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 21: External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 22: Power-Up Sequence – Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 23: Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 24: Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 25: Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 26: Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 27: Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 28: Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 29: Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 30: Barrel Distortion Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 31: Vertical Perspective Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 32: Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 33: Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 34: Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 35: Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 36: Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 37: Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 38: Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 39: Single-Ended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 40: Differential Connection—Grounded Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 41: CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .62

Figure 42: Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 43: Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 44: Parallel Input Data Timing Waveform Using DIN_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 45: Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 46: Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 47: NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 48: Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 49: Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 50: Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 51: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 52: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 53: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 54: FRAME_SYNC to FRAME_VALID/LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 55: Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 56: Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

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List of Figures

Aptina Confidential and Proprietary

Figure 57: Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 58: SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 59: Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 60: Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 61: V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 62: Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 63: Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Figure 64: 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Tables

Aptina Confidential and Proprietary

List of Tables

Table 1: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 5: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 6: Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 7: EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 8: EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 9: NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 10: PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 11: YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 12: RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 13: 2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 14: SPI Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 15: SPI Commands Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 16: GPIO Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 17: System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 18: Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 19: Dewarp Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 20: GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 21: Flash Manager Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 22: Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 23: TX Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 24: Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 25: Lens Correction Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 26: Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 27: Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 28: Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 29: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 30: Parallel Input Data Timing Values Using DIN_CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 31: Output Data Ordering in DOUT RGB Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 32: Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 33: Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 34: Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 35: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 36: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 37: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 38: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 39: RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 40: SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 41: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 42: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 43: Video DAC Electrical Characteristics–Single-Ended Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 44: Video DAC Electrical Characteristics–Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 45: Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 46: Power Consumption – Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 47: Power Consumption – Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 48: NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 49: Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 50: Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 51: V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

List of Tables

Aptina Confidential and Proprietary

Table 52: Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

General Description

Aptina Confidential and Proprietary

General Description

The AptinaTM MT9V126 is a VGA-format, single-chip CMOS active-pixel digital image

sensor for automotive applications. It captures high-quality color images at VGA resolu-

tion and outputs NTSC or PAL interlaced composite video.

The VGA CMOS image sensor features DigitalClarity®–Aptina’s breakthrough low-noise

CMOS imaging technology that achieves near-CCD image quality (based on signal-to-

noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low

power, and integration advantages of Aptina's advanced active pixel CMOS process

technology.

The MT9V126 is a complete camera-on-a-chip. It incorporates sophisticated camera

functions on-chip and is programmable through a simple two-wire serial interface or by

an attached SPI Flash memory that contains setup information that may be loaded auto-

matically at startup.

The MT9V126 performs sophisticated processing functions including color recovery,

color correction, sharpening, programmable gamma correction, auto black reference

clamping, auto exposure, 50Hz/60Hz flicker avoidance, lens shading correction, auto

white balance (AWB), and on-the-fly defect identification and correction.

The MT9V126 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and

PAL video formats. The image data can be output on one or two output ports:

• Composite analog video (single-ended and differential output support)

• Parallel 8-, 10-bit digital

The integrated lens correction and overlay generation for steering guidance eliminates

expensive overlay processing that is usually required by an external DSP; this signifi-

cantly reduces overall costs.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Architecture

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Architecture

Internal Block Diagram

Figure 1: Internal Block Diagram

Note: The active array is smaller than the sensor array.

Image Flow Processor

Colo r & Gamma Correctio n

Color Space Conversion

Edge Enhancement

Camera Control

AWB

Overlay

Graphics

Generation

¼” VGA ROI

@ 60

frames per sec.

640 x 480 Active Array

VideoEncoder

DAC

SPI & 2W I/F

Interface

SPI

4 2

NTSC /

PAL

BT -656

Optional

BT -656

Input

2.8V 1.8V

Two-Wire I/F

Lens correction

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

System Block Diagram

Aptina Confidential and Proprietary

System Block Diagram

The system block diagram will depend on the application. The system block diagram in

Figure 2 shows all components; optional peripheral components are highlighted.

Control information will be received by a microcontroller through the automotive bus,

such as LIN or CAN bus, to communicate with the MT9V126 through its two-wire serial

bus. Optional components will vary by application. For further details, see the MT9V126

Figure 2: System Block Diagram

SPI Serial Data

Flash

10Kb - 16MB

LP Filter

27 MHz

DAC _POS

μC 2WIRE I/F

Composite

Video

PAL /NTSC

(2.8V)

VAA _PIX (2.8V )

(1.8V)

EXTCLK

System Bus

CAN /LIN

4.7kΩ

DAC_REF

2.8V

DAC _NEG

LDO

_IO (2.8V)

CCIR 656/

GPO

CCIR 656/

or GPI

Optional

XTAL

75Ω

_PLL (2.8V).

_DAC (2.8V)

RESET_BAR

FRAME _SYNC

PIXCLK

FRAME_VALID

LINE_VALID

_CL K

[7:0]

OUT

LSB0,1

OUT

[7:0]

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

System Block Diagram

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Crystal Usage

As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be

connected between EXTCLK and XTAL. Two small loading capacitors of 15–22pF of NPO

dielectric should be added as shown in Figure 3.

Aptina does not recommend using the crystal option for automotive applications above

85°C. A crystal oscillator with temperature compensation is recommended.

Figure 3: Using a Crystal Instead of an External Oscillator

EXTCLK

XTAL

18pF

NPO

27.000 MHz

Sensor

NPO

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Aptina Confidential and Proprietary

Pin Descriptions and Assignments

Table 4: Pin Descriptions

Pin Number Pin Name Type Description

Clock and Reset

B1 EXTCLK Input Master input clock (27MHz): This can either be a square-wave generated from an

oscillator (in which case the XTAL input must be left unconnected) or connected

directly to a crystal.

B2 XTAL Output If EXTCLK is connected to one pin of a crystal, this signal is connected to the other

pin; otherwise this signal must be left unconnected.

C1 RESET_BAR Input Asynchronous active-low reset: When asserted, the device will return all

interfaces to their reset state. When released, the device will initiate the boot

sequence.

C2 FRAME_SYNC Input This input can be used to set the output timing of the MT9V126 to a fixed point in

the frame.

The input buffer associated with this input is permanently enabled. This signal

should be connected to GND if not used.

G3 SCLK Input These two signals implement serial communications protocol for access to the

internal registers and variables.

H3 SDATA Input/OD

H2 SADDR Input This signal controls the device ID that will respond to serial communication

commands.

Two-wire serial interface device ID selection:

0: 0x90

1: 0xBA

SPI Interface

H5 SPI_SCLK Output Clock output for interfacing to an external SPI memory such as Flash/EEPROM.

Tristate when RESET_BAR is asserted.

G5 SPI_SDI Input Data in from SPI device. This signal has an internal pull-up resistor.

H4 SPI_SDO Output Data out to SPI device. Tristate when RESET_BAR is asserted.

G4 SPI_CS_N Output Chip selects to SPI device. Tristated when RESET_BAR is asserted.

(Parallel) Pixel Data Input

D1 DIN_CLK Input Pixel clock input: Data on DIN[7:0] are sampled at the rising or falling edge of this

clock. (Alternatively, an internal sampling clock may be used.)

H1, G1, F1,

G2, F2, E1, E2,

DIN[7:0] Input Data coming in on this interface is passed through the overlay blender and to the

video encoder output.

The input buffers associated with inputs 7 to 0 are powered down by default. This

allows these signals to be left unconnected if not required.

These inputs can also be used as general purpose inputs.

(Parallel) Pixel Data Output

E7 FRAME_VALID Input/Output Pixel data from the MT9V126 can be routed out on this interface and processed

externally.

To save power, these signals are driven to a constant logic level unless the parallel

pixel data output or alternate (GPIO) function is enabled for these pins. For more

information see Table 16 on page 38.

This interface is disabled by default.

The slew rate of these outputs is programmable.

These signals can also be used as general purpose input/outputs.

E6 LINE_VALID Input/Output

E8 PIXCLK Output

C7, B6,

C8, B7,

B8, A6,

A7, A8

DOUT[7:0] Output

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

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D7 DOUT_LSB1 Input/Output

When the sensor core is running in bypass mode, it will generate 10 bits of output

data per pixel. These two pins make the two LSB of pixel data available externally.

Leave unconnected if not used. To save power, these signals are driven to a

constant logic level unless the sensor core is running in bypass mode or the

alternate function is enabled for these pins. For more information see Table 16,

“GPIO Bit Descriptions,” on page 38.

This interface is disabled by default.

The slew rate of these outputs is programmable.

D8 DOUT_LSB0 Input/Output

Composite Video Output

B3 DAC_POS Output Positive video DAC output in differential mode.

Video DAC output in single-ended mode. This interface is enabled by default

using NTSC/PAL signalling. For applications where composite video output is not

required, the video DAC can be placed in a power-down state under software

control.

A4 DAC_NEG Output Negative video DAC output in differential mode. Connect to AGND in single-ended

mode.

A2 DAC_REF Output External reference resistor for the video DAC.

Manufacturing Test Interface

D6 TDI Input JTAG Test pin (Reserved for Test Mode)

C6 TDO Output JTAG Test pin (Reserved for Test Mode)

F3 TMS Input JTAG Test pin (Reserved for Test Mode)

F4 TCK Input JTAG Test pin (Reserved for Test Mode)

F5 TRST_N Input Connect to GND.

F6 ATEST1 Input Analog test input. Connect to GND in normal operation.

G6 ATEST2 Input Analog test input. Connect to GND in normal operation.

Power

C3, D3, E3 VDD Supply Supply for VDD core: 1.8V nominal.

C5, D5, E5 VDD_IO Supply Supply for digital IOs: 2.8V nominal.

A5 VDD_DAC Supply Supply for video DAC: 2.8V nominal.

B5 VDD_PLL Supply Supply for PLL: 2.8V nominal.

G7, G8 VAA Supply Analog power: 2.8V nominal.

F7, F8 VAA_PIX Supply Analog pixel array power: 2.8V nominal. Must be at same voltage potential as

VAA.

A3 GND_DAC Supply Video DAC ground

B4, C4, D4, E4 DGND Supply Digital ground.

H6, H7, H8 AGND Supply Analog ground.

Table 4: Pin Descriptions (continued)

Pin Number Pin Name Type Description

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Aptina Confidential and Proprietary

Pin Assignments

Pin 1 is not populated with a ball. That allows the device to be identified by an additional

marking.

Table 5: Pin Assignments

1 2 3 4 5 6 7 8

A DAC_REF GND_DAC DAC_NEG VDD_DAC DOUT2DOUT1DOUT0

BEXTCLK XTAL DAC_POS GND V

DD_PLL DOUT6DOUT4DOUT3

C RESET_BAR FRAME_SYNC VDD GND VDD_IO TDO DOUT7DOUT5

IN_CLK DIN0VDD GND VDD_IO TDI DOUT_LSB1 DOUT_LSB0

IN2DIN1VDD GND VDD_IO LINE_VALID FRAME_VALID PIXCLK

FDIN5DIN3TMSTCKTRST_NATEST1VAA_PIX VAA_PIX

IN6DIN4 SCLK SPI_CS_N SPI_SDI ATEST2 VAA VAA

HDIN7SADDR SDATA SPI_SDO SPI_SCLK AGND AGND AGND

Table 6: Reset/Default State of Interfaces

Name Reset State Default State Notes

EXTCLK Clock running or stopped Clock running Input

XTAL N/A N/A Input

RESET_BAR Asserted De-asserted Input

SCLK N/A N/A Input. Must always be driven to a valid logic

level.

SDATA High impedance High impedance Input/Output. A valid logic level should be

established by pull-up resistor.

SADDR N/A N/A Input. Must always be driven to a valid logic

level. Must be permanently tied to VDD_IO or

GND.

SPI_SCLK High impedance. Driven, logic 0 Output. Output enable is R0x0032[9].

SPI_SDI Internal pull-up enabled. Internal pull-up enabled Input. Internal pull-up is permanently enabled.

SPI_SDO High impedance Driven, logic 0 Output enable is R0x0032[9].

SPI_CS_N High impedance Driven, logic 1 Output enable is R0x0032[9].

DINCLK Input buffer powered down Input buffer powered down Input. This interface is disabled by default, and

the input buffers are powered down. If this

interface is not required, these pins can be left

unconnected (floating).

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0

FRAME_VALID High impedance High impedance Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating). After reset, these pins

are powered up, sampled, then powered down

again as part of the auto-configuration

mechanism. See Note 2.

LINE_VALID

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

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Notes: 1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired in a

system (for example, on our demo boards), these outputs will be connected, and the inputs to which

they are connected will want to see a valid logic level. No current drain should result from driving these

to a valid logic level (unless there is a pull-up at the system level).

2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they

can be left floating but they will not drive a valid logic level to an attached device.

PIXCLK High impedance Driven, logic 0 Output. This interface disabled by default.

See Note 1.

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

DOUT_LSB1 High impedance High impedance Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating). After reset, these pins

are powered-up, sampled, then powered down

again as part of the auto-configuration

mechanism.

DOUT_LSB0 High impedance Driven, logic 0

DAC_POS High impedance Driven Output. Interface disabled by hardware reset

and enabled by default when the device starts

streaming.

DAC_NEG

DAC_REF

TDI Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TDO High impedance High impedance Output. Driven only during appropriate parts of

the JTAG shifter sequence.

TMS Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TCK Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can

be left unconnected (floating).

TRST_N N/A N/A Input. Must always be driven to a valid logic

level. Must be driven to GND for normal

operation.

FRAME_SYNC N/A N/A Input. Must always be driven to a valid logic

level. Must be driven to GND for normal

operation.

ATEST1 Must be driven to GND for normal operation.

ATEST2 Must be driven to GND for normal operation.

Table 6: Reset/Default State of Interfaces (continued)

Name Reset State Default State Notes

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

SOC Description

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SOC Description

Detailed Architecture Overview

Sensor Core

The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable

gain and black offset, and timing and control as illustrated in Figure 4.

Figure 4: Sensor Core Block Diagram

Pixel Array Structure

The sensor core pixel array is configured as 744 columns by 512 rows, as shown in

Figure 5. This includes black rows and columns.

Figure 5: Pixel Array Description

The black row data are used internally for the automatic black level adjustment.

However, these black rows can also be read out by setting the sensor to raw data output

mode.

There are 744 columns by 512 rows of optically-active pixels that include a pixel

boundary around the VGA (640 x 480) image to avoid boundary effects during color

interpolation and correction.

Communication

Bus

to IFP

10-Bit Data

to IFP

Sync

Signals

Clock

Control Register

Analog Processing

Active Pixel

Sensor (APS)

Array Timing and Control

ADC

active border rows

black row

black rows

black columns

active border rows

active border columns

Active pixel array

640 x 480

(not to scale)

Pixel logical address = (743, 511)

Pixel logical address = (0, 0)

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

SOC Description

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The one additional active column and two additional active rows are used to enable

horizontally and vertically mirrored readout to start on the same color pixel.

Figure 6 illustrates the process of capturing the image. The original scene is flipped and

mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image

is presented in true orientation by the output display.

Figure 6: Image Capture Example

SCENE

(Front view)

OPTICS

IMAGE CAPTURE

IMAGE RENDERING

Start Readout

Row by Row

IMAGE SENSOR

(Rear view)

Start Rasterization

Process of Image Gathering and Image Display

DISPLAY

(Front view)

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Sensor Pixel Array

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Sensor Pixel Array

The active pixel array is 640 x 480 pixels. In addition, there are rows and columns for lens

alignment and demosaic.

Not shown in Figure 7 are pixels for black level calibration.

Figure 7: Sensor Pixel Array

The range of adjustment is from Row 0 to 22 and Column 0 to 30. There are 4 rows/

columns needed to calculate the RGB values. The window should be moved only at even

numbers.

Figure 8: Pixel Color Pattern Detail (top right corner)

Lens Alignment Pixels - 16 Columns

Lens Alignment Pixels - 12 Rows

Lens Alignment Pixels - 16 Columns

Demosaic Pixels - 4 Columns

Demosaic Pixels - 4 Rows

Active Pixels

640 Rows, 480 Columns

Black Pixels

Column Readout Direction

...

Row

Readout

Direction

First Active

Border

Pixel

(64, 0)

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Sensor Pixel Array

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Output Data Format

The sensor core image data are read out in progressive scan order. Valid image data are

surrounded by horizontal and vertical blanking, shown in Figure 9.

For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size

is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of

the image field.

For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical

size is 288 pixels per field.

Figure 9: Spatial Illustration of Image Readout

P0,0 P0,1 P0,2.....................................P0,n-1 P0,n

P2,0 P2,1 P2,2.....................................P2,n-1 P2,n

00 00 00 .................. 00 00 00

Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n

Pm,0 Pm,1.....................................Pm,n-1 Pm,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

Valid Image Odd Field Horizontal

Blanking

Vertical Even Blanking Vertical/Horizontal

Blanking

P1,0 P1,1 P1,2.....................................P1,n-1 P1,n

P3,0 P3,1 P3,2.....................................P3,n-1 P3,n

00 00 00 .................. 00 00 00

Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n

Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

Valid Image Even Field Horizontal

Blanking

Vertical Odd Blanking Vertical/Horizontal

Blanking

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Image Flow Processor

Image and color processing in the MT9V126 are implemented as an image flow

processor (IFP) coded in hardware logic. During normal operation, the embedded

microcontroller will automatically adjust the operation parameters. The IFP is broken

down into different sections, as outlined in Figure 10.

Figure 10: Color Pipeline

Test Pattern

Generator

Black

Level

Subtraction

Color Correction

Aperture

Correction

Gamma

Correction

(12-to-8 Lookup)

Statistics

Engine

Color Kill

Output

Formatting

YUV to RGB

Raw Data

10/12-Bit

RGB

RAW 10

8-bit

RGB

8-bit

YUV

Parallel

Output

Interface

RGB to YUV

Digital Gain Control

Lens Shading

Correction

Defect Correction,

Noise Reduction,

Color Interpolation

MUX

IFP

Parallel Output Mux

Pixel Array

ADC

Analog Output Mux

NTSC/PAL

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Sensor Pixel Array

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Test Patterns

During normal operation of the MT9V126, a stream of raw image data from the sensor

core is continuously fed into the color pipeline. For test purposes, this stream can be

replaced with a fixed image generated by a special test module in the pipeline. The

module provides a selection of test patterns sufficient for basic testing of the pipeline.

Test patterns are accessible by programming a register and are shown in Figure 11.

Aptina recommends disabling the MCU before enabling test patterns.

Figure 11: Color Bar Test Pattern

Test Pattern Example

Flat Field

Vertical Ramp

Color Bar

Vertical Stripes

Pseudo-Random

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Sensor Pixel Array

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NTSC/PAL Test Pattern Generation

There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and

color saturation characterization. Each pattern consists of seven color bars (white,

yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are

detailed in Tables 7 and 8.

The test pattern is invoked through a Host Command call to the TX Manager. See the

MT9V126 Host Command Specification.

Figure 12: Color Bars

CCIR-656 Format

The color bar data is encoded in 656 data streams. The duration of the blanking and

active video periods of the generated 656 data are summarized in the following tables.

Table 7: EIA Color Bars (NTSC)

Nominal Range White Yellow Cyan Green Magenta Red Blue

Y 16 to 235 180 162 131 112 84 65 35

Cb 16 to 240 128 44 156 72 184 100 212

Cr 16 to 240 128 142 44 58 198 212 114

Table 8: EBU Color Bars (PAL)

Nominal Range White Yellow Cyan Green Magenta Red Blue

Y 16 to 235 235 162 131 112 84 65 35

Cb 16 to 240 128 44 156 72 184 100 212

Cr 16 to 240 128 142 44 58 198 212 114

Table 9: NTSC

Line Numbers Field Description

1-3 2 Blanking

4-19 1 Blanking

20-263 1 Active video

264-265 1 Blanking

266-282 2 Blanking

283-525 2 Active Video

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Black Level Subtraction and Digital Gain

Image stream processing starts with black level subtraction and multiplication of all

pixel values by a programmable digital gain. Both operations can be independently set

to separate values for each color channel (R, Gr, Gb, B). Independent color channel

digital gain can be adjusted with registers. Independent color channel black level adjust-

ments can also be made. If the black level subtraction produces a negative result for a

particular pixel, the value of this pixel is set to 0.

Positional Gain Adjustments (PGA)

Lenses tend to produce images whose brightness is significantly attenuated near the

edges. There are also other factors causing fixed pattern signal gradients in images

captured by image sensors. The cumulative result of all these factors is known as image

shading. The MT9V126 has an embedded shading correction module that can be

programmed to counter the shading effects on each individual R, Gb, Gr, and B color

signal.

The Correction Function

The correction functions can then be applied to each pixel value to equalize the

response across the image as follows:

(EQ 1)

where P are the pixel values and f is the color dependent correction functions for each

color channel.

Color Interpolation

In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a

10-bit integer number, which can be considered proportional to the pixel's response to a

one-color light stimulus, red, green, or blue, depending on the pixel's position under the

color filter array. Initial data processing steps, up to and including the defect correction,

preserve the one-color-per-pixel nature of the data stream, but after the defect correc-

tion it must be converted to a three-colors-per-pixel stream appropriate for standard

color processing. The conversion is done by an edge-sensitive color interpolation

module. The module pads the incomplete color information available for each pixel

with information extracted from an appropriate set of neighboring pixels. The algorithm

used to select this set and extract the information seeks the best compromise between

preserving edges and filtering out high frequency noise in flat field areas. The edge

threshold can be set through register settings.

Table 10: PAL

Line Numbers Field Description

1-22 1 Blanking

23-310 1 Active video

311-312 1 Blanking

313-335 2 Blanking

336-623 2 Active video

624-625 2 Blanking

Pcorrected(row,col)=Psensor(row,col)*f(row,col)

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Color Correction and Aperture Correction

To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are

subjected to color correction. The IFP multiplies each vector of three pixel colors by a

3 x 3 color correction matrix. The three components of the resulting color vector are all

sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit

width of the image data stream is widened to 12 bits per color (36 bits per pixel). The

color correction matrix can be either programmed by the user or automatically selected

by the auto white balance (AWB) algorithm implemented in the IFP. Color correction

should ideally produce output colors that are corrected for the spectral sensitivity and

color crosstalk characteristics of the image sensor. The optimal values of the color

correction matrix elements depend on those sensor characteristics and on the spectrum

of light incident on the sensor. The color correction variables can be adjusted through

To increase image sharpness, a programmable 2D aperture correction (sharpening filter)

is applied to color-corrected image data. The gain and threshold for 2D correction can

be defined through register settings.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

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Gamma Correction

The MT9V126 IFP includes a block for gamma correction that can adjust its shape based

on brightness to enhance the performance under certain lighting conditions. Two

custom gamma correction tables may be uploaded corresponding to a brighter lighting

condition and a darker lighting condition. At power-up, the IFP loads the two tables with

default values. The final gamma correction table used depends on the brightness of the

scene and takes the form of an interpolated version of the two tables.

The gamma correction curve (as shown in Figure 13) is implemented as a piecewise

linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit

output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,

1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates

are programmable through IFP registers.

Figure 13: Gamma Correction Curve

RGB to YUV Conversion

For further processing, the data is converted from RGB color space to YUV color space.

Color Kill

To remove high-or low-light color artifacts, a color kill circuit is included. It affects only

pixels whose luminance exceeds a certain preprogrammed threshold. The U and V

values of those pixels are attenuated proportionally to the difference between their lumi-

nance and the threshold.

YUV Color Filter

As an optional processing step, noise suppression by one-dimensional low-pass filtering

of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.

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YUV-to-RGB/YUV Conversion and Output Formatting

The YUV data stream emerging from the scaling module can either exit the color pipe-

line as-is or be converted before exit to an alternative YUV or RGB data format.

Output Format and Timing

YUV/RGB Data Ordering

The MT9V126 supports swapping YCbCr mode, as illustrated in Table 11.

The RGB output data ordering in default mode is shown in Table 12. The odd and even

bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise

swapped when chroma swap is enabled.

Uncompressed 10-Bit Bypass Output

Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:

• Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least

significant 2 bits of data.

• Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 13.

Readout Formats

Progressive format is used for raw Bayer output.

Table 11: YCbCr Output Data Ordering

Mode Data Sequence

Default (no swap) CbiYiCriYi+1

Swapped CbCr CriYiCbiYi+1

Swapped YC YiCbiYi+1 Cri

Swapped CbCr, YC YiCriYi+1 Cbi

Table 12: RGB Ordering in Default Mode

Mode (Swap Disabled) Byte D7D6D5D4D3D2D1D0

565RGB Odd R7R6R5R4R3G7G6G5

Even G4G3G2B7B6B5B4B3

555RGB Odd 0 R7R6R5R4R3G7G6

Even G5G4G3B7B6B5B4B3

444xRGB Odd R7R6R5R4G7G6G5G4

Even B7B6B5B4 0 0 0 0

x444RGB Odd 0 0 0 0 R7R6R5R4

Even G7G6G5G4B7B6B5B4

Table 13: 2-Byte Bayer Format

Byte Bits Used Bit Sequence

Odd bytes 8 data bits D9D8D7D6D5D4D3D2

Even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 D1D0

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Output Formats

ITU-R BT.656 and RGB Output

The MT9V126 can output processed video as a standard ITU-R BT.656 (CCIR656) stream,

an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr

4:2:2 data with fixed embedded synchronization codes. This output is typically suitable

for subsequent display by standard video equipment or JPEG/MPEG compression.

Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a

variety of RGB formats in 640 by 480 progressive format in conjunction with

LINE_VALID and FRAME_VALID.

The MT9V126 can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB),

and two types of 12-bit RGB (444RGB). Refer to Table 31 and Table 32 on page 67 for

details.

Bayer Output

Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by

simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,

and PIXCLK to time the data. This mode is called sensor stand-alone mode.

Output Ports

Composite Video Output

The composite video output DAC is external-resistor-programmable and supports both

single-ended and differential output. The DAC is driven by the on-chip video encoder

output.

Parallel Output

Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R

BT.656 and RGB output. Ten-bit output is used for raw Bayer output.

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Usage Modes

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Usage Modes

How a camera based on the MT9V126 will be configured depends on what features are

used. In the simplest case, only an MT9V126 plus an external flash memory, or an 8-bit

microcontroller (µC) might be sufficient.A back-up camera with dynamic input from the

steering system will require a µC with a system bus interface such as a CAN bus or a LIN

bus. Flash sizes vary depending on the data for registers, firmware, and overlay

data—somewhere between 10Kb to 16MB. The two-wire bus is adequate since only

high-level commands are used to invoke overlays, load registers from memory, or set up

lens correction parameters. Overlay data can alternatively be issued by the external µC if

the rate of refreshing data is deemed adequate. If there are no commands in the Flash

image the device can be in auto configuration mode by which the sensor is set up

according to the status of pins FRAME_VALID, LINE_VALID and DOUT_LSB0. For further

information, see “Auto-Configuration” on page 36.

In the simplest case no Flash memory or µC is required, as shown in Figure 14. This is

truly a single chip operation.

Note: Because mandatory patches must be loaded, the Auto-Config mode is not recom-

mended.

Figure 14: Auto-Config Mode

The MT9V126 can be configured by a serial Flash through the SPI Interface.

Figure 15: Flash Mode

Analog Out

Digital Out

Auto-Config Mode

MT9V126

SPI

Serial

Flash

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Usage Modes

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Overlay functions can also be assigned to general purpose inputs. For instance, a prox-

imity sensor would call up a warning message. That capability can be employed on all

configurations with external Flash memory by mapping overlay images to an input.

Alternatively, the µC may poll these inputs to create an action such as a new overlay as

shown in Figure 16.

Figure 16: Usage Mode 3

Typically, an automotive bus such as CAN or LIN bus will be connected to a rear-view

camera for the purpose of dynamically providing steering information that will in turn

be translated into overlay images being called by the µC as shown in Figure 17.

Figure 17: Host Mode with Flash

Overlay information may also be passed by the µC without a need for a Flash memory.

However, because the data transfer rate is limited over the two-wire serial bus, the

update rate may be slower. However, if overlay images are preloaded into the four on-

chip buffers, they may be turned on and off or move location at the frame rate as shown

in Figure 18.

Figure 18: Host Mode

MT9V126

SPI

Serial

Flash

GPI[7:0]

Proximity

Sensor

CAN/

LIN Bus

MT9V126

SPI

8/16bit uC Serial

Flash

two-wire

MT9V126

8/16bit μC

CAN /

LIN Bus

two-wire

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External Overlay

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External Overlay

In addition to the on-chip overlay generator, an externally generated overlay may be

superimposed onto the video output.

Figure 19: External Overlay System Block Diagram

SPI

Serial data

Flash

10Kb to 16MB

LP filter

27 MHz

VIDEO_P CVBS

PAL/NTSC

EXTCLK

VIDEO_N

DOUT [7:0]

PIXCLK

Overlay

FPGA/DSP DINCLK

DIN [7:0]

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Multicamera Support

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Multicamera Support

Two or more MT9V126 sensors may be synchronized to a frame by asserting the

FRAME_SYNC signal. At that point, the sensor and video encoder will reset without

affecting any register settings. The MT9V126 may be triggered to be synchronized with

another MT9V126 or an external event.

Figure 20: Multicamera System Block Diagram

Decoder /DSP

Camera 1

Camera 2

CVBS

CAN

μC

MT9V126

F_ SYNC

OSC

F_SYNC

Dual Camera

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

External Signal Processing

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External Signal Processing

An external signal processor can take data from ITU656 or raw Bayer output format and

post-process or compress the data in various formats.

Figure 21: External Signal Processing Block Diagram

Device Configuration

After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,

it will enter a boot sequence to configure its operating mode. There are essentially four

modes, two when Flash is present and two when Flash is not present. Figure 22: “Power-

Up Sequence – Configuration Options Flow Chart,” on page 37 contains more details on

the configuration options.

If Flash is present and:

• A valid Flash device identifier is detected AND the Flash device contains valid config-

uration records, then

– Disable Auto-Config

– Parse Flash Content

– Load Flash Configuration ->Flash Configuration Mode

• A valid Flash device identifier is detected BUT the Flash device DOES NOT contain

valid configuration records, then

– Enter Auto Configuration.

If Flash is not present and:

• SPI_SDI == 0, then

– Enter Host Configuration.

• SPI_SDI != 0, then

– Enter Auto Configuration

SPI

Serial data

Flash

10Kb to 16MB

27 MHz

VIDEO_P

CVBS

PAL/NTSC

EXTCLK

VIDEO_N

DOUT [7:0]

PIXCLK

Signal processor

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External Signal Processing

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Auto-Configuration

The device supports an auto-configuration feature. During system start-up, the device

first detects whether an SPI Flash device is attached to the MT9V126. If not, it will then

sample the state of a number of GPI inputs including FRAME_VALID, LINE_VALID and

DOUT_LSB0. For more information, see Table 16, “GPIO Bit Descriptions,” on page 38.

The state of these inputs then determines the configuration of a number of subsystems

of the device such as readout mode, pedestal and video format, respectively.

The auto-configuration feature can be disabled by grounding the SPI_DIN pin. The

device samples the state of this pin during the Flash device detection process. If no SPI

Flash device is detected (read device ID of 0x00 or 0xFF), OR the SPI_DIN pin is

grounded, then auto-configuration is disabled.

Flash Configuration Mode

If a valid Flash is detected (by reading device ID other than 0x00 or 0xFF) and the flash

device contains valid configuration records, then these configuration records are

processed.

Host Configuration

This mode is entered if the SPI_DIN pin is grounded. The SOC performs no configura-

tion, and remains idle waiting for configuration and instruction from the host.

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Power Sequence

In power-up, the core voltage (1.8V) must trail the IO (2.8V) by a positive number. All

2.8V rails can be turned on at the same time or follow the power-up sequence in Figure

52: “Power Up Sequence,” on page 73.

In power down, the sequence is reversed. The core voltage (1.8V) must be turned off

before any 2.8V. Refer to Figure 53: “Power Down Sequence,” on page 74 for details.

Figure 22: Power-Up Sequence – Configuration Options Flow Chart

Supported SPI Devices

Table 14 lists supported Flash devices. Devices not compatible will require a firmware

patch. Contact Aptina for additional support.

Table 14: SPI Flash Devices

Type Density Manufacturer Device Speed

(MHz) Standard Temp Range

(°F) Supported

Flash 8 MB Atmel AT26DF081A 70 JEDEC/Device ID –20 to +85 Yes

Flash 1 MB ST M25P10-AVMB3 50 –40 to +125 Yes

Power Up

/RESET

Flash

Header?

Auto Configuration:

FRAME_VALID,

LINE_VALID,

OUT

_LSB0

SPI _SDI = 0?

Wait for Host

Command

Wait for Host

Command

Disable Auto -Config

Parse Flash Content

Wait for Host

Command

yes

FRAME_VALID

LINE_VALID

OUT

_LSB0

Normal

1: Horizontal Mirror

0 No Pedestal

1: Pedestal

0: NTSC

1: PAL

Disable Auto-Config

Flash

Configuration:

Host

Configuration :

Host

Configuration:

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Supported SPI Commands

The SPI commands shown in Table 15 are supported by the MT9V126.

Table 15: SPI Commands Supported

Command Value

Read Array 0x03

Block Erase 0xD8

Chip Erase 0xC7

Read Status 0x05

Write status 0x01

Byte Page Program 0x02

Write Enable 0x06

Write Disable 0x04

Read Manufacturer and Device ID 0x9F

(Fast) Read Array 0x0B

Table 16: GPIO Bit Descriptions

GPI[2]

(DOUT_LSB0) GPI[1]

(FRAME_VALID) GPI[0]

(LINE_VALID)

Low (“0”) NTSC Normal No pedestal

High (“1”) PAL Horizontal mirror Pedestal

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Host Command Interface

Aptina’s sensors and SOCs contain numerous registers that are accessed through a

two-wire interface with speeds up to 400 kHz.

The MT9V126, in addition to writing or reading straight to/from registers or firmware

variables, has a mechanism to write higher level commands, the Host Command Inter-

face (HCI). Once a command has been written through the HCI, it will be executed by on

chip firmware and the results are reported back. In general, registers shall not be

accessed with the exception of registers that are marked for “User Access.”

Flash memory is also available to store commands for later execution. Under DMA

control, a command is written into the SOC and executed.

For a complete spec on host commands, refer to the MT9V126 Host Command Interface

Specification.

Figure 23: Interface Structure

Host Command to FW

Response from FW

15 0bit

command register

Addr 0x40

Addr 0xFC00

Addr 0xFC0E

Addr 0xFC02

Addr 0xFC04

Addr 0xFC06

Addr 0xFC08

Addr 0xFC0A

Addr 0xFC0C

door bell

15 0bit

Parameter 0

Parameter 7

cmd_handler_params_pool_0

cmd_handler_params_pool_1

cmd_handler_params_pool_2

cmd_handler_params_pool_3

cmd_handler_params_pool_4

cmd_handler_params_pool_5

cmd_handler_params_pool_6

cmd_handler_params_pool_7

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Host Command Process Flow

Command Flow

The host issues a command by writing (through a two-wire interface bus) to the

command register. All commands are encoded with bit 15 set, which automatically

generates the host command (doorbell) interrupt to the microprocessor.

Assuming initial conditions, the host first writes the command parameters (if any) to the

parameters pool (in the command handler's logical page), then writes the command to

command register. The interrupt handler then signals the command handler task to

process the command.

If the host wishes to determine the outcome of the command, it must poll the command

completed processing the command. The contents of the command register indicate the

command's result status. If the command generated response parameters, the host can

now retrieve these from the parameters pool.

Read Command

Doorb e ll

bit clear ?

Command has

para meters?

Yes

Write parameters

Parameter Pool

Yes

Write co mmand

Command registe r

Issue

Command

Host could inse rt an

optional delay here

Host could insert an

optional delay here

Wait f o r a

response?

Read Command

registe r

Doorbell bit

clear?

Yes

Command

has response

parameters ?

Yes

Read response

parameters from

Parameter Pool

Yes

At th is point

Command Registe r

contains response code

Done

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Note: The host must not write to the parameters pool, nor issue another command, until

the previous command completes. This is true even if the host does not care about the

result of the previous command. Therefore, the host must always poll the command

issuing a command.

For a complete command list and further information consult the Host Command Inter-

face Specification.

An example of how (using DevWare) a command may be initiated in the form of a

“Preset” follows.

Set Parallel Mode - Normal (Overlay i656)

All DevWare presets supplied by Aptina poll and test the doorbell bit after issuing the

command. Therefore there is no need to check if the doorbell bit is clear before issuing

the next command.

REG= 0xFC00, 0x1000 // CMD_HANDLER_PARAMS_POOL_0

REG= 0x0040, 0x8801 // issue command

// POLL COMMAND_REGISTER::DOORBELL => 0x0

Summary of Host Commands

Table 17 on page 41 through Table 23 on page 44 show summaries of the host

commands. The commands are divided into the following sections:

– System Manager

–Overlay

– Dewarp (or Lens Distortion Correction)

–GPIO Host interface

– Flash Manager Host

– Patch Loader Interface

– TX Manager

Following is a summary of the Host Interface commands. The description gives a quick

orientation. The “Type” column shows if it is an asynchronous or synchronous

command. For a complete list of all commands including parameters, consult the Host

Command Interface Specification document.

Table 17: System Manager Commands

System Manager

Host Command Value Type Description

Set State 0x8100 Asynchronous Request the system enter a new state

Get State 0x8101 Synchronous Get the current state of the system

Table 18: Overlay Host Commands

Overlay Host Command Value Type Description

Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem

Get Overlay State 0x8201 Synchronous Retrieve the state of the overlay subsystem

Set Calibration 0x8202 Synchronous Set the calibration offset

Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap

Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap

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Set String Property 0x8205 Synchronous Set a property of a character string

Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash)

Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation

Write Buffer 0x8208 Synchronous Write directly to an overlay buffer

Read Buffer 0x8209 Synchronous Read directly from an overlay buffer

Enable Layer 0x820A Synchronous Enable or disable an overlay layer

Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer

Set String 0x820C Synchronous Set the character string

Load String 0x820E Asynchronous Load a character string (from Flash)

Table 19: Dewarp Commands

Dewarp Host Command Value Type Description

Enable Dewarp 0x8300 Asynchronous Enable or disable the dewarp subsystem

Get Dewarp State 0x8301 Synchronous Retrieve the current state of the dewarp subsystem

Load Config 0x8302 Asynchronous Load a pair of dewarp configuration sets from SPI Flash into

local cache (and apply)

Config Status 0x8303 Synchronous Retrieve the status of a Load Config request

Write Config 0x8304 Synchronous Write a dewarp configuration set under Host control into local

cache

Apply Config 0x8305 Asynchronous Apply a dewarp configuration set stored in local cache

Read Config 0x8306 Synchronous Read a dewarp configuration set under Host control.

Table 20: GPIO Host Commands

GPIO Host Command Value Type Description

Set GPIO Property 0x8400 Synchronous Set a property of one or more GPIO pins

Get GPIO Property 0x8401 Synchronous Retrieve a property of a GPIO pin

Set GPO State 0x8402 Synchronous Set the state of a GPO pin or pins

Get GPIO State 0x8403 Synchronous Get the state of a GPI pin or pins

Set GPI Association 0x8404 Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash

Table 21: Flash Manager Host Commands

Flash Manager

Host Command Value Type Description

Get Lock 0x8500 Asynchronous Request the Flash Manager access lock

Lock Status 0x8501 Synchronous Retrieve the status of the access lock request

Release Lock 0x8502 Synchronous Release the Flash Manager access lock

Config 0x8503 Synchronous Configure the Flash Manager and underlying SPI Flash subsystem

Read 0x8504 Asynchronous Read data from the SPI Flash

Write 0x8505 Asynchronous Write data to the SPI Flash

Erase Block 0x8506 Asynchronous Erase a block of data from the SPI Flash

Erase Device 0x8507 Asynchronous Erase the SPI Flash device

Query Device 0x8508 Asynchronous Query device-specific information

Status 0x8509 Synchronous Obtain status of current asynchronous operation

Table 18: Overlay Host Commands

Overlay Host Command Value Type Description

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Table 22: Sequencer Host Commands

Sequencer Host

Command Value Type Description

Set Encoding Mode 0x8603 Synchronous Set the encoding mode

Enable Horizontal Flip 0x8604 Synchronous Enable or disable horizontal flip

Set Flicker Frequency 0x8605 Synchronous Set the flicker frequency

Refresh Mode 0x8606 Synchronous Refresh the Sequencer mode/context

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Table 23: TX Manager Host Commands

TX Manager Host

Command Value Type Description

Config DAC 0x8800 Synchronous Configure the Video DAC

Set Parallel Mode 0x8801 Synchronous Configure the Parallel output port

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

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Slave Two-Wire Serial Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the MT9V126. This interface is designed to be compatible with the MIPI Alli-

ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical

characteristics and transfer protocols of the two-wire serial interface specification.

The interface protocol uses a master/slave model in which a master controls one or

more slave devices. The sensor acts as a slave device. The master generates a clock

(SCLK) that is an input to the sensor and used to synchronize transfers.

Data is transferred between the master and the slave on a bidirectional signal (SDATA).

SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7kΩ

resistor.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements, as follows:

• a start or restart condition

• a slave address/data direction byte

• a 16-bit register address

• an acknowledge or a no-acknowledge bit

•data bytes

• a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with

a start condition, and the bus is released with a stop condition. Only the master can gen-

erate the start and stop conditions.

The SADDR pin is used to select between two different addresses in case of conflict with

another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave

address is 0xBA. See Table 24 below.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each SCLK clock period. SDATA can change when SCLK

is low and must be stable while SCLK is HIGH.

Table 24: Two-Wire Interface ID Address Switching

SADDR Two-Wire Interface Address ID

00x90

10xBA

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Slave Two-Wire Serial Interface

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Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data

transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default

slave addresses used by the MT9V126 are 0x90 (write address) and 0x91 (read address).

Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be

selected by asserting the SADDR input signal.

Message Byte

Message bytes are used for sending register addresses and register write data to the slave

device and for retrieving register read data. The protocol used is outside the scope of the

two-wire serial interface specification.

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the

SCLK clock period following the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-

edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is

LOW and must be stable while SCLK is HIGH.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver does not drive SDATA low during

the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-

nate a read sequence.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.

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Slave Two-Wire Serial Interface

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Typical Operation

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”

indicates a WRITE and a “1” indicates a READ. If the address matches the address of the

slave device, the slave device acknowledges receipt of the address by generating an

acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave

sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master will then transfer the 16-bit data, as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master stops writing by generating a (re)start or stop condition. If the

request was a READ, the master sends the 8-bit write slave address/data direction byte

and 16-bit register address, just as in the write request. The master then generates a

(re)start condition and the 8-bit read slave address/data direction byte, and clocks out

the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-

bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

Single READ from Random Location

Figure 24 shows the typical READ cycle of the host to MT9V126. The first two bytes sent

by the host are an internal 16-bit register address. The following 2-byte READ cycle sends

the contents of the registers to host.

Figure 24: Single READ from Random Location

Single READ from Current Location

Figure 25 shows the single READ cycle without writing the address. The internal address

will use the previous address value written to the register.

Figure 25: Single Read from Current Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master to slave

Slave Address 0

S A Reg Address[15:8] A Reg Address[7:0] Slave Address A

A 1Sr Read Data

[15:8] P

Previous Reg Address, N Reg Address, M M+1

Read Data

[7:0]

Slave Address 1S A Read Data

[15:8] Slave Address A1SP Read Data

[15:8] P

Previous Reg Address, N Reg Address, N+1 N+2

Read Data

[7:0]

ARead Data

[7:0]

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Slave Two-Wire Serial Interface

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Sequential READ, Start from Random Location

This sequence (Figure 26) starts in the same way as the single READ from random loca-

tion (Figure 24 on page 47). Instead of generating a no-acknowledge bit after the first

byte of data has been transferred, the master generates an acknowledge bit and

continues to perform byte READs until “L” bytes have been read.

Figure 26: Sequential READ, Start from Random Location

Sequential READ, Start from Current Location

This sequence (Figure 27) starts in the same way as the single READ from current loca-

tion (Figure 25). Instead of generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge bit and continues to

perform byte reads until “L” bytes have been read.

Figure 27: Sequential READ, Start from Current Location

Single Write to Random Location

Figure 28 shows the typical WRITE cycle from the host to the MT9V126. The first 2 bytes

indicate a 16-bit address of the internal registers with most-significant byte first. The

following 2 bytes indicate the 16-bit data.

Figure 28: Single WRITE to Random Location

Read Data

(15:8)

Read Data

(15:8)

Read Data

(7:0)

Slave Address 0

S Sr

AReg Address[15:8] AReg Address[7:0] ARead Data

Slave Address

Previous Reg Address, N Reg Address, M

M+1 M+2

M+1

M+3

M+L-2 M+L-1 M+L

A P

Read Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Read Data

(7:0)

ARead Data Read Data

Previous Reg Address, N N+1 N+2 N+L-1 N+

ARead DataSlave Address AA1 AS

Read Data

(15:8)

Read Data

(7:0) ARead Data

(15:8)

Read Data

(7:0) ARead Data

(15:8)

Read Data

(7:0)

Read Data

(15:8)

Read Data

(7:0)

Slave Address 0

SAReg Address[15:8] AReg Address[7:0] AP

Pre vio us Reg Address, N Reg Address, M M

Write Dat a

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Sequential WRITE, Start at Random Location

This sequence (Figure 29) starts in the same way as the single WRITE to random location

(Figure 28). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte writes until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 29: Sequential WRITE, Start at Random Location

Slave Address 0

SAReg Address[15:8]

Write Data

AReg Address[7:0] AWrite Data

Previous Reg Address, N Reg Address, M

M+1 M+2

M+1

M+3

Write Data Write Data

M+L-2 M+L-1 M+L

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

Write Data A

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Integrated Lens Distortion Correction

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Integrated Lens Distortion Correction

Integrated lens distortion correction eliminates the need for an expensive DSP for image

correction. Using software tools, a flexible algorithm can be calibrated for many

wide-angle lenses.

Lens Distortion Definition

Automotive backup cameras typically feature a wide FOV lens so that a single camera-

mounted above the center of the rear bumper can present the driver with a view of all

potential obstacles immediately behind the full width of the vehicle. Lenses with a wide

field of view typically exhibit at least a noticeable amount of barrel distortion.

Barrel distortion is caused by a reduction in object magnification the further away from

the optical axis. A barrel distortion percentage can be measured as the amount a refer-

ence line is bent as a percentage of the image height. For example, the lens used to

capture the image below demonstrates a barrel distortion of approximately 21 percent.

The distortion of this lens is near the maximum amount of distortion that must be

corrected by the MT9V126.

Figure 30: Barrel Distortion Definition

For the image to appear natural to the driver, the MT9V126 corrects this barrel distortion

and reprocesses the image so that the resulting distortion is less than one percent.

Table 25: Lens Correction Features

Description Value References/Comments

HFOV 60° to180° HFOV (horizontal field of view)

Aperture range f#2.0 to f#4.0 Aperture range

Maximum lens distortion 25% Maximum lens distortion as percentage of FOV

Maximum distortion after correction 1% Maximum distortion after correction

Input resolution 640 x 480 Progressive scan

Output resolution 720 x 240 NTSC mode

720 x 288 PAL mode

Horizontal ±10%

Vertical +10% to –25%

Distortion = 100 rows

Image Height = 480 rows

Barrel Distortion of 21% (100/480)

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Integrated Lens Distortion Correction

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Lens Distortion Correction

Distortion correction is the ability to digitally correct the lens barrel distortion and to

provide a natural view of objects.

In addition, with barrel distortion one can adjust the perspective view to enhance the

visibility by virtually elevating the point of viewing objects.

Notes: 1. This image shows the original image with the targeted field of view (FOV), which is programmable, after

correction.

2. The image is corrected.

3. The image is cropped to its largest usable rectangle.

4. The image is finally cropped and scaled up to NTSC output format.

3 4

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Integrated Lens Distortion Correction

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Perspective View

A backup camera has to be able to virtually adjust the vertical perspective as if the

camera were placed immediately behind the vehicle pointed directly down, as illus-

trated in Figure 31. The vertical perspective adjustment may be employed temporarily to

assist with parking conditions, or it may be enabled permanently by loading new param-

eters.

Figure 31: Vertical Perspective Adjustment

In the transition between different settings, one or two black frames may be inserted

temporarily, resulting in a slight flicker.

Conversion Sequence

Starting with the captured distorted image, the conversion process sequence is shown in

Figure 32 on page 53. The configuration data created by the lens distortion emulator are

then transferred into the memory compile tool with DevWare.

Perspective

Adjustment

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Figure 32: Conversion Sequence

Notes: 1. A distorted NTSC output image may be taken by the MT9V126.

2. Distortion-corrected image created with Aptina’s lens distortion emulator program.

3. Perspective view adjustment also using Aptina’s lens distortion emulator program.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Overlay Capability

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Overlay Capability

Figure 33 highlights the graphical overlay data flow of the MT9V126. The images are

separated to fit into 2KB blocks of memory after compression.

• Up to four overlays may be blended simultaneously

• Overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels

• Selectable readout: rotating order is user programmable

• Dynamic movement through predefined overlay images

• Palette of 32 colors out of 64,000 with eight colors per bitmap

• Blend factors may be changed dynamically to achieve smooth transitions

The host commands allow a bitmap to be written piecemeal to a memory buffer through

the I2C, and through the DMA direct from SPI Flash memory. Multiple encoding passes

may be required to fit an image into a 2KB block of memory; alternatively, the image can

be divided into two or more blocks to make the image fit. Every graphic image may be

positioned in an x/y direction and overlap with other graphic images.

The host may load an image at any time. Under control of DMA assist, data are trans-

ferred to the off-screen buffer in compressed form. This assures that no display data are

corrupted during the replenishment of the four active overlay buffers.

Figure 33: Overlay Data Flow

Note: These images are not actually rendered, but show conceptual objects and object blending.

Off-screen

buffer

Overlay buffers: 2KB each

Decompress

Blend and Overlay

Flash

Bitmaps - compressed

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Serial Memory Partition

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Serial Memory Partition

The contents of the Flash/EEPROM memory partition logically into three blocks (see

Figure 34):

• Memory for overlay data and descriptors

• Memory for register settings, which may be loaded at boot-up

• Firmware extensions or software patches; in addition to the on-chip firmware, exten-

sions reside in this block of memory

These blocks are not necessarily contiguous.

Figure 34: Memory Partitioning

For a complete description of memory organization, refer to the MT9V126 SPI Flash

Contents Encoding Specification.

External Memory Speed Requirement

For a 2KB block of overlay to be transferred within a frame time to achieve maximum

update rate, the serial memory has to be a certain speed.

Table 26: Transfer Time Estimate

Frame Time SPI Clock Transfer Time to 2KB

33.3ms 4.5 MHz 1ms

S/W Patch

Alterna te Reg.

Setting

Overlay Data

Flash

Partitioning Fixed Size

Overla

s-RLE

12Byte Header

RLE Encoded

Data

2kByte

Fixed Size

Overla

s-RLE

Lens Correction

Parameter

Fixed-size

Overlays – RLE

Fixed-size

Overlays – RLE

Flash

Partitioning

Overlay

Data

Software Patch

12-byte Header

RLE Encoded

Data

2KB

Lens Shading

Correction

Parameter

Alternate

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Overlay Adjustment

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Overlay Adjustment

To ensure a correct position of the overlay to compensate for assembly deviation, the

overlay can be adjusted with assistance from the overlay statistics engine:

• The overlay statistics engine supports a windowed 8-bin luma histogram, either row-

wise (vertical) or column-wise (horizontal).

• The example calibration statistics firmware patch can be used to perform an auto-

matic successive-approximation search of a cross-hair target within the scene.

• On the first frame, the firmware performs a coarse horizontal search, followed by a

coarse vertical search in the second frame.

• In subsequent frames, the firmware reduces the region-of-interest of the search to the

histogram bins containing the greatest accumulator values, thereby refining the

search.

• The resultant X, Y location of the cross-hair target can be used to assign a calibration

value of offset selected overlay graphic image positions within the output image.

• The calibration statistics patch also supports a manual mode, which allows the host

to access the raw accumulator values directly.

Note: For the overlay calibration feature to work, load the appropriate patch. See Statistics

Engine document.

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Figure 35: Overlay Calibration

The position of the target will be used to determine the calibration value that shifts the

X,Y position of adjustable overlay graphics.

Unlike the lens distortion correction and perspective correction, the overlay calibration

is intended to be applied on a device by device basis “in system,” which means after the

camera has been installed. Aptina provides basic programming scripts that may reside

in the SPI Flash memory to assist in this effort.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Overlay Character Generator

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Overlay Character Generator

In addition to the four overlay layers, a fifth layer exists for a character generator overlay

string.

There are a total of:

• 16 alphanumeric characters available

• 22 characters maximum per line

• 16 x 32 pixels with 1-bit color depth

Any update to the character generator string requires the string to be passed in its

entirety with the Host Command. Character strings have their own control properties

aside from the Overlay bitmap properties.

Figure 36: Internal Block Diagram Overlay

Overlay

Layer0

Layer1

Layer2

Layer3

BT656

Number

Generator

BT656

Tim ing control

User R egisters

D ata Bu s

DMA/CPU

ROM

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Overlay Character Generator

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Character Generator

The character generator can be seen as the fifth top layer, but instead of getting the

source from RLE data in the memory buffers, it has a predefined 16 characters stored in

ROM.

All the characters are 1-bit depth color and are sharing the same YCbCr look up table.

Figure 37: Example of Character Descriptor 0 Stored in ROM

It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when

blended with the BT 656 data).

ROM 151413121110 9 8 7 6 5 4 3 2 1 0

0x00 0000000000000000

0x02 0000000000000000

0x04 0000001111000000

0x06 0000011111100000

0x08 0000111111110000

0x0a 0001111001111000

0x0c 0001110000111100

0x0e 0011110000011100

0x10 0011100000011100

0x12 0011100000011110

0x14 0111100000001110

0x16 0111000000001110

0x18 0111000000001110

0x1a 0111000000001110

0x1c 0111000000001110

0x1e 0111000000001110

0x20 0111000000001110

0x22 0111000000001110

0x24 0111000000001110

0x26 0111000000001110

0x28 0011100000001110

0x2a 0011100000011110

0x2c 0011100000011100

0x2e 0011110000011100

0x30 0001110000111000

0x32 0001111001111000

0x34 0000111111110000

0x36 0000011111100000

0x38 0000001111000000

0x3a 0000000000000000

0x3c 0000000000000000

0x3e 0000000000000000

…

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Overlay Character Generator

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Character Generator Details

Table 27 shows the characters that can be generated.

It is the responsibility of the user to set up proper values in the character positioning to

fit them in the same row (that is one of the reasons that 22 is the maximum number of

characters).

Note: No error is generated if the character row overruns the horizontal or vertical limits of

the frame.

Full Character Set for Overlay

Figure 38 shows all of the characters that can be generated by the MT9V126.

Figure 38: Full Character Set for Overlay

Table 27: Character Generator Details

Item Quantity Description

16-bit character 22 Coder for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, –, (comma), (period)

1 bpp color 1 Depth of the bit map is 1 bpp

0x0 0x4 0x80xC

0x10x5 0x9

0x2

0x3

0x6

0x7

0xA

0xB

0xD

0xE

0xF

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Modes and Timing

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Modes and Timing

This section provides an overview of the typical usage modes and related timing infor-

mation for the MT9V126.

Composite Video Output

The external pin DOUT_LSB0 can be used to configure the device for default NTSC or PAL

operation. This and other video configuration settings are available as register settings

accessible through the serial interface.

NTSC

Both differential and single-ended connections of the full NTSC format are supported.

The differential connection that uses two output lines is used for low noise or long

distance applications. The single-ended connection is used for PCB tracks and screened

cable where noise is not a concern. The NTSC format has three black lines at the bottom

of each image for padding (which most LCDs do not display).

PAL

The PAL format is supported with 576 active image rows.

NTSC or PAL with External Image Processing

The on-chip video encoder and DAC can be used with external data stream input

(DIN[7:0] port). Correct NTSC or PAL formatted CCIR656 data is required for correct

composite video output.

The on-chip overlay may be put on top of the overlay generated by the external overlay

generator.

Single-Ended and Differential Composite Output

The composite output can be operated in a single-ended or differential mode by simply

changing the external resistor configuration. For single-ended termination, see

Figure 39 on page 61. The differential schematic is shown in Figure 40 on page 62.

Figure 39: Single-Ended Termination

75Ω 75Ω

Chip

Boundary

i = IPLUSi = IMINUS

Single-Ended

R1=75

Single-ended

e.g. PCB Track

e.g. 75Ω COAX Single-ended

L=1uH L = 1uH

C = 330

C0 C1

C = 330

L0 L1 L2

Typical Values for LC

75Ω Terminated Receiver

L = 2.2μH

75Ω

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Modes and Timing

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Figure 40: Differential Connection—Grounded Termination

Parallel Output (DOUT)

The DOUT[7:0] port supports both progressive and Interlaced mode. Progressive mode

(with FV and LV signal) include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced mode is

CCIR656 compliant.

Figure 41 shows the data that is output on the parallel port for CCIR656. Both NTSC and

PAL formats are displayed. The blue values in Figure 41 represent NTSC (525/60). The

red values represent PAL (625/50).

Figure 41: CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems

Figure 42 on page 63 shows detailed vertical blanking information for NTSC timing. See

Table 28 on page 63 for data on field, vertical blanking, EAV, and SAV states.

B Y C

R Y C

B Y C

R Y C

R Y F

268

280

1440

1716

1728

EAV CODE BLANKING SAV CODE CO - SITED _ CO - SITED _

Start of digital line Start of digital active line Next line

Digital

video

stream

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Figure 42: Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System

Figure 43 shows detailed vertical blanking information for PAL timing. See Table 29 on

page 64 for data on field, vertical blanking, EAV, and SAV states.

Table 28: Field, Vertical Blanking, EAV, and SAV States 525/60 Video System

Line Number F V H

(EAV) H

(SAV)

1–3 1 1 1 0

4–9 0 1 1 0

20–263 0 0 1 0

264–265 0 1 1 0

266–282 1 1 1 0

283–525 1 0 1 0

Blanking

Field 1 Active Video

Blanking

Field 2 Active Video

Line 4

266

Field 1

(F = 0)

Odd

Field 2

(F = 1)

Even

EAV SAV

Line 1 (V = 1)

Line 20 (V = 0)

Line 264 (V = 1)

Line 283 (V = 0)

Line 525 (V = 0)

H = 1H = 0

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Modes and Timing

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Figure 43: Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System

Table 29: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System

Line Number F V H

(EAV) H

(SAV)

1–22 0 1 1 0

23–310 0 0 1 0

311–312 0 1 1 0

313–335 1 1 1 0

336–623 1 0 1 0

624–625 1 1 1 0

Blanking

Field 1 Active Video

Blanking

Field 2 Active Video

Field 1

(F = 0)

Odd

Field 2

(F = 1)

Even

H = 1

EAV

H = 0

SAV

Blanking

Line 1 (V = 1)

Line 23 (V = 0)

Line 311 (V = 1)

Line 336 (V = 0)

Line 625 (V = 1)

Line 624 (V = 1)

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Parallel Input (DIN)

The data-in port allows external CCIR656 data to be multiplexed into the NTSC or PAL

output data. Figure 44 shows the timing of the data-in (DIN[7:0]) signals. Table 30

describes timing values for the parallel input waveform. Both mode 0 and mode 1 wave-

forms are supported.

Figure 44: Parallel Input Data Timing Waveform Using DIN_CLK

Note: Setup and hold times are measured with respect to the rising or falling edge of DIN_CLK, which can be

programmed by R0x0016[13].

Table 30: Parallel Input Data Timing Values Using DIN_CLK

Name Conditions Min Typical Max Parameter

tDIN_CLK Max ± 100 ppm – 37 – DIN_CLK Period

ts 8 – 18.5 DIN Setup Time

th 8 – 18.5 DIN Hold Time

DIN

CLK

D0 D1D2 D3D4D5

[7:0]

MODE 0

DIN

CLK

D0 D1D2 D3D4D5

DIN _CLK

MODE 1

DIN _CLK

[7:0]

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Modes and Timing

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Reset and Clocks

Reset

Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.

In the reset state, all control registers are set to default values. See “Device Configura-

tion” on page 35 for more details on Auto, Host, and Flash configurations.

Soft reset is asserted or de-asserted by the two-wire serial interface program. In soft-

reset mode, the two-wire serial interface and the register bus are still running. All control

registers are reset using default values.

Clocks

The MT9V126 has three primary clocks:

• A master clock coming from the EXTCLK signal.

• In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass

mode, PIXCLK runs at the same frequency as EXTCLK.

•D

IN_CLK that is associated with the parallel DIN port.

When the MT9V126 operates in sensor stand-alone mode, the image flow pipeline

clocks can be shut off to conserve power.

The sensor core is a master in the system. The sensor core frame rate defines the overall

image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced

by the sensor configuration, and are also a function of certain image flow pipeline func-

tions. The relationship of the primary clocks is depicted in Figure 45.

The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr

or 565RGB—but has only an 8-bit port through which to communicate this pixel data.

To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.

Figure 45: Primary Clock Relationships

10 bits/pixel

1 pixel/clock

16 bits/pixel

1 pixel/clock

16 bits/pixel (TYP)

0.5 pixel/clock

Colorpipe

Output Interface

Sensor

Pixel Clock

Sensor

Master Clock

EXTCLK Sensor Core

DIN_CLK

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Floating Inputs

The following MT9V126 pins cannot be floated:

•D

IN_CLK (tie to GND if not used)

•S

DATA–This pin is bidirectional and should not be floated

• FRAME_SYNC

•TRST_N

Output Data Ordering

Note: PIXCLK is 54 MHz when EXTCLK is 27 MHz.

Note: PIXCLK is 27 MHz when EXTCLK is 27 MHz.

Table 31: Output Data Ordering in DOUT RGB Mode

Mode

(Swap Disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0

565RGB First R7R6R5R4R3G7G6G5

Second G4 G3 G2 B7 B6 B5 B4 B3

555RGB First 0 R7 R6 R5 R4 R3 G7 G6

Second G5 G4 G3 B7 B6 B5 B4 B3

444xRGB First R7 R6 R5 R4 G7 G6 G5 G4

Second B7 B6 B5 B4 0 0 0 0

x444RGB First 0 0 0 0 R7 R6 R5 R4

Second G7 G6 G5 G4 B7 B6 B5 B4

Table 32: Output Data Ordering in Sensor Stand-Alone Mode

Mode D7 D6 D5 D4 D3 D2 D1 D0 DOUT_LSB1 DOUT_LSB0

10-bit Output B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

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Modes and Timing

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I/O Circuitry

Figure 46 illustrates typical circuitry used for each input, output, or I/O pad.

Figure 46: Typical I/O Equivalent Circuits

Note: All I/O circuitry shown above is for reference only. The actual implementation may be different.

_IO

Receiver

Input Pad

Pad

GND

_IO

Receiver

SPI_SDI and RESET_BAR

Input Pad

Pad

GND

Receiver

GND

_IO

Pad

I/O Pad

Slew

Rate

Control

_IO

Receiver

SCLK and XTAL_IN

Input Pad

Pad

GND

XTAL

Output Pad

Pad

_IO

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Figure 47: NTSC Block

Note: All I/O circuitry shown above is for reference only. The actual implementation may be different.

Figure 48: Serial Interface

Pad

VDD_DAC

GND

Pad

ESD

DAC_REF

ESD

DAC_POS

DAC_NEG

NTSC Block

Resistor

4.7kΩ/2.35kΩ

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Modes and Timing

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I/O Timing

Digital Output

By default, the MT9V126 launches pixel data, FV, and LV synchronously with the falling

edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the

rising edge of PIXCLK. The timing diagram is shown in Figure 49.

As an option, the polarity of the PIXCLK can be inverted from the default by program-

ming R0x0016[14].

Figure 49: Digital Output I/O Timing

Note: PIXCLK can be inverted from the default by programming R0x0016[14].

Table 33: Parallel Digital Output I/O Timing

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate

Signal Parameter Conditions Min Typ Max Unit

EXTCLK fextclk max ±100 ppm – 27 – MHz

textclk_period – 37 – ns

Duty cycle 45 50 55 %

PIXCLK1f

pixclk –27–MHz

tpixclk_period – 37 – ns

Duty cycle 45 50 55 %

DATA[7:0] tpixclkf_dout –2 0 2 ns

tdout_su 8 – 18.5 ns

tdout_ho 8 – 18.5 ns

FV/LV tpixclkf_fvlv –2 0 2 ns

tfvlv_su 8 – 18.5 ns

tfvlv_ho 8 – 18.5 ns

EXT

CLK

PIXCLK

OUT

[7 :0]

FRAME_VALID

LINE_VALID

pixclkf_dout

pixclkf_fvlv

Input

Output

fvlv_su

fvlv_ho

dout_ho

dout_su

extclk_period

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Slew Rate

Figure 50: Slew Rate Timing

Table 34: Slew Rate for PIXCLK and DOUT

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VΑΑ_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF

PIXCLK DOUT[7:0]

UnitR0x30 [10:8] Typical

Rise Time Typical

Fall Time R0x30 [2:0] Typical

Rise Time Typical

Fall Time

000 6.5 6.3 000 6.5 6.3 ns

001 4.8 4.6 001 4.8 4.6 ns

010 3.9 3.8 010 3.9 3.8 ns

011 3.7 3.7 011 3.7 3.7 ns

100 3.6 3.6 100 3.6 3.6 ns

101 3.5 3.5 101 3.5 3.5 ns

110 3.4 3.4 110 3.4 3.4 ns

111 3.3 3.3 111 3.3 3.3 ns

90%

10%

rise

fa ll

PIXCLK

OUT

rise

fa ll

90%

10%

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Modes and Timing

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Configuration Timing

During start-up, the Dout_LSB0, LV and FV are sampled. Setup and hold timing for the

RESET_BAR signal with respect to DOUT_LSB0, LV, and FV are shown in Figure 51 and

Table 35. These signals are sampled once by the on-chip firmware, which yields a long

tHold time.

Figure 51: Configuration Timing

Table 35: Configuration Timing

Signal Parameter Min Typ Max Unit

DOUT_LSB0, FRAME_VALID, LINE_VALID tSETUP 0μs

tHOLD 50 μs

tSETUP tHOLD

Valid Data

RESET_BAR

DOUT_LSB0

FRAME_VALID

LINE_VALID

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Figure 52: Power Up Sequence

Notes: 1. RESET_BAR may not exceed VDD_IO + 0.3V.

2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than the

1.8V core voltage at all times.

Notes: 1. Xtal settling time is component-dependent (Xtal, Oscillator, etc) and usually takes about 10mS ~100mS.

2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required

for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is performed by

the RC circuit, then the RC time must include the all power rail settle time and Xtal

3. This is required to load necessary patches via Flash mode (SPI) or Host mode (two-wire serial interface).

Loading time varies depending on the number of patches and bus speed.

Table 36: Power Up Sequence

Definition Symbol Minimum Typical Maximum Unit

VDD_PLL to VAA/VAA_PIX t0 0 – – μS

VAA/VAA_PIX to VDD_IO t1 0 – – μS

VDD_IO to VDD t2 10 – – μS

Xtal settle time tx – 301–mS

Hard Reset t3 102– – Clock cycle

Internal Initialization t4 50 – – mS

Patch Load (SPI or I2C) t5 – 4003–mS

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

RESET_BAR

VDD_IO (2.8)

t3 t4 t5

Hard Reset Internal

(NTSC/PAL)

Initialization

Patch Config

SPI or Host Streaming

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Figure 53: Power Down Sequence

(1) t3 is required between power down and next power up time, all decoupling caps from

regulators must completely discharged before next power up.

Figure 54: FRAME_SYNC to FRAME_VALID/LINE_VALID

Table 37: Power Down Sequence

Definition Symbol Minimum Typical Maximum Unit

VDD to VDD_IO t0 10 – – μS

VDD_IO to VAA/VAA_PIX t10––μS

VAA/VAA_PIX to VDD_PLL/DAC t20––μS

Power Down until Next Power Up Time t3 1001––ms

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

VDD_IO (2.8)

Power Down until next Power Up Cycle

FRAME_SYNC

FRAME_VALID

LINE_VALID

tFRAME_SYNC

tFRMSYNH_FVH

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Figure 55: Reset to SPI Access Delay

Figure 56: Reset to Serial Access Delay

Figure 57: Reset to AE/AWB Image

Table 38: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters

Parameter Name Conditions Min Typ Max Unit

FRAME_SYNC to FV/LV tFRMSYNC_FVH Auto Config mode 4 – – ms

tFRAME_SYNC tFRAMESYNC 30 ms

Table 39: RESET_BAR Delay Parameters

Parameter Name Condition Min Typ Max Unit

Power up delay 2.8V to 1.8V 0.1 – – ms

RESET_BAR HIGH to SPI_CS_N LOW tRSTH_CSL 18 – – ms

RESET_BAR HIGH to SDATA LOW tRSTH_SDATAL 1.8 – – ms

RESET_BAR HIGH to FRAME_VALID tRSTH_FVL 235 – – ms

R ESET_BAR

tRSTH_CSL

SPI_CS_N

RESET_BAR

SDATA

tRSTH_SDATAL

First Frame Overlay from

Flash

RESET_BAR

VIDEO

tRSTH_FVL

tRSTH_OVL

tRSTH_AEAWB

AE/AWB settled

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RESET_BAR HIGH to first Overlay tRSTH_OVL 235 – – ms

RESET_BAR HIGH to AE/AWB settled tRSTH_AEAWB – 400 – ms

Table 39: RESET_BAR Delay Parameters

Parameter Name Condition Min Typ Max Unit

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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Electrical Specifications

Figure 58: SPI Output Timing

Table 40: SPI Data Setup and Hold Timing

Parameter Description Min Typ Max Units

fSPI_SCLK SPI_SCLK Frequency 1.6875 4.5 18 MHz

tsu Setup time – – 110 ns

tSCLK_SDO Hold time 110 ns

tCS_SCLK Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK – 230 – ns

SPI_CS_N

SPI_SCLK

SPI_SDI

SPI_SDO

tCS_SCLK

tSCLK_SDO

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Caution Stresses greater than those listed in Table 41 may cause permanent damage to the device. This is

a stress rating only, and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Notes: 1. VAA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be taken

to avoid excessive noise injection in the analog supplies if all three supplies are tied together.

2. The imager operates in this temperature range, but image quality may degrade if it operates beyond the

functional operating temperature range.

3. Image quality is not guaranteed at temperatures equal to or greater than this range.

Table 41: Absolute Maximum Ratings

Symbol Parameter

Rating

UnitMin Max

VDD Digital power (1.8V) -0.3 2.4 V

VDD_IO I/O power (2.8v) -0.3 4 V

VAA VAA Analog power (2.8V) -0.3 4 V

VAA_PIX Pixel array power (2.8v) -0.3 4 V

VDD_PLL PLL power (2.8V) -0.3 4 V

VDD_DAC DAC power (2.8V) -0.3 4 V

VIN DC Input Voltage -0.3 VDD_IO+0.3 V

VOUT DC Output Voltage -0.3 VDD_IO+0.3 V

TSTG Storage temperature -50 150 °C

Table 42: Electrical Characteristics and Operating Conditions

Parameter1Condition Min Typ Max Unit

Core digital voltage (VDD)–1.71.81.9V

IO digital voltage (VDD_IO) – 2.66 2.8 2.94 V

Video DAC voltage (VDD_DAC) – 2.66 2.8 2.94 V

PLL Voltage (VDD_PLL) – 2.66 2.8 2.94 V

Analog voltage (VAA) – 2.66 2.8 2.94 V

Pixel supply voltage (VAA_PIX) – 2.66 2.8 2.94 V

Leakage current EXTCLK: HIGH or LOW 10 μA

Imager operating temperature2– –40 +105 °C

Functional operating temperature3 –40 +85 °C

Storage temperature – –50 +150 °C

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Table 43: Video DAC Electrical Characteristics–Single-Ended Mode

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V

Parameter Condition Min Typ Max Unit

Resolution – 10 - bits

DNL – 0.2 0.4 bits

INL – 0.7 3.5 bits

Output local load Output pad (DAC_POS) – 75 - Ω

Unused output (DAC_NEG) – 0 - Ω

Output voltage Single-ended mode, code 000h – .02 - V

Single-ended mode, code 3FFh – 1.30 - V

Output current Single-ended mode, code 000h – 0.26 - mA

Single-ended mode, code 3FFh – 17.33 - mA

Supply current Estimate – - 25.0 mA

DAC_REF DAC Reference – 1.15 +/-0.2 - V

R DAC_REF DAC Reference – 4.7 - KΩ

Table 44: Video DAC Electrical Characteristics–Differential Mode

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V

Parameter Condition Min Typ Max Unit

DNL – 0.2 0.25 Bits

INL – 0.8 2.5 Bits

Output local load Differential mode per pad

(DAC_POS and DAC_NEG)

– 37.5 – Ω

Output voltage Differential mode, code 000h, pad dacp – .02 – V

Differential mode, code 000h, pad dacn – 1.30 – V

Differential mode, code 3FFh, pad dacp – 1.30 – V

Differential mode, code 3FFH, pad dacn – .02 – V

Output current Differential mode, code 000h, pad dacp – .53 – mA

Differential mode, code 000h, pad dacn – 34.7 – mA

Differential mode, code 3FFh, pad dacp – 34.7 – mA

Differential mode, code 3FFH, pad dacn – .53 – mA

Differential output,

midlevel

–0.65–V

Supply current Estimate – – 50 mA

DAC_REF DAC Reference – 1.15 +/-0.2 V

R DAC_REF DAC Reference 2.35 KΩ

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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Notes: 1. All inputs are protected and may be active when All supplies (2.8V and 1.8V) are turned off.

Table 45: Digital I/O Parameters

TA = Ambient = 25°C; All supplies at 2.8V

Signal Parameter Definitions Condition Min Typ Max Unit

All

Outputs

Load capacitance 1 – 30 pF

Output signal slew 2.8V, 30pF load – – – V/ns

2.8V, 5pF load – – – V/ns

VOH Output high voltage – VDD_IO – V

VOL Output low voltage –0.3 – – V

IOH Output high current VDD = 2.8V, VOH

= 2.4V

–– 8mA

IOL Output low current VDD = 2.8V, VOL =

0.4V

–– 8mA

All Inputs VIH Input high voltage VDD = 2.8V 0.7 * VDD_IO – VDD_IO + 0.3 V

VIL Input low voltage VDD = 2.8V –0.3 – 0.3 * VDD_IO V

IIN Input leakage current –2 – 2 μA

Signal CAP Input signal

capacitance

–3.5 –pF

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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Power Consumption, Operating Mode

Analog output uses single-ended mode: DAC_Pos = 75Ω, DAC_Neg = open, parallel

output is disabled.

Analog output uses single-ended mode: DAC_Pos = 75Ω, DAC_Neg = open, parallel

output is enabled.

Table 46: Power Consumption – Condition 1

fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;

VDD _PLL = 2.8V; VDD _DAC = 2.8V

Power Plane Supply Condition 1 Typ Power Max Power Unit

VDD 1.8 140.4 162 mW

VDD_IO 2.8 Parallel off 4.2 8.4 mW

VAA 2.8 89.6 112 mW

VAA_PIX 2.8 1.96 5.04 mW

VDD_DAC 2.8 Single 75(1) 39.2 44.8 mW

VDD_PLL 2.8 13.44 16.8 mW

Total 288.8 349.04 mW

Table 47: Power Consumption – Condition 2

fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;

VDD _PLL = 2.8V; VDD _DAC = 2.8V

Power Plane Supply Condition 2 Typ Power Max Power Unit

VDD 1.8 140.4 162 mW

VDD_IO 2.8 Parallel on 42 50.4 mW

VAA 2.8 89.6 112 mW

VAA_PIX 2.8 1.96 5.04 mW

VDD_DAC 2.8 Single 75(1) 39.2 44.8 mW

VDD_PLL 2.8 13.44 16.8 mW

Total 326.6 391.04 mW

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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NTSC Signal Parameters

Notes: 1. Black and white levels are referenced to the blanking level.

2. NTSC convention standardized by the IRE (1 IRE = 7.14mV).

3. Encoder contrast setting R0x011 = R0x001 = 0.

4. DAC ref = 2.35kΩ, load = 37.5Ω.

Table 48: NTSC Signal Parameters

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V

Parameter Conditions Min Typ Max Units Notes

Line Frequency 15734.25 15734.27 15734.28 Hz

Field Frequency 59.94 59.94 59.94 Hz

Sync Rise Time 148 148 148 ns

Sync Fall Time 148 148 148 ns

Sync Width 4.744.744.74 μs

Sync Level 37 39.9 43 IRE 2, 4

Burst Level 37 39.7 43 IRE 2, 4

Sync to Setup

(with pedestal off)

9.44 9.44 9.44 μs

Sync to Burst Start 5.33 5.33 5.33 μs

Front Porch 1.331.331.33 μs

Black Level 6.5 7.5 8.5 IRE 1, 2, 4

White Level 90 100 110 IRE 1, 2, 3, 4

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Electrical Specifications

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Figure 59: Video Timing

Table 49: Video Timing

Signal NTSC

27 MHz PAL

27 MHz Units

A H Period 1716 1728 Clocks

B Hsync to burst 144 153 Clocks

C burst 63 66 Clocks

D Hsync to Signal 255 279 Clocks

E Video Signal 1423 1413 Clocks

F Front 36 39 Clocks

G Hsync Period 128 128 Clocks

H Sync rising/falling edge 4 4 Clocks

J Back overscan (BOS) 9 14 Clocks

K Front overscan (FOS) 8 13 Clocks

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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Figure 60: Equivalent Pulse

Table 50: Equivalent Pulse

Signal NTSC

27 MHz PAL

27 MHz Units

I H/2 Period 858 864 Clocks

JPulse width 6464Clocks

K Pulse rising/falling edge 4 4 Clocks

L Signal to pulse 38 41 Clocks

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Electrical Specifications

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Figure 61: V Pulse

Table 51: V Pulse

Signal NTSC

27 MHz PAL

27 MHz Units

M H/2 Period 858 864 Clocks

N Pulse width 730 736 Clocks

O V pulse interval 128 128 Clocks

P Pulse rising/falling edge 4 4 Clocks

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Electrical Specifications

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Two-Wire Serial Bus Timing

Figure 62 and Table 52 describe the timing for the two-wire serial interface.

Figure 62: Two-Wire Serial Bus Timing Parameters

Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the unde-

fined region of the falling edge of SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the

Table 52: Two-Wire Serial Bus Characteristics

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C

Parameter Symbol

Standard-Mode Fast-Mode

UnitMin Max Min Max

SCLK Clock Frequency fSCL 0 100 0 400 KHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

tHD;STA 4.0 - 0.6 - μS

LOW period of the SCLK clock tLOW 4.7 - 1.3 - μS

HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - μS

Set-up time for a repeated START

condition

tSU;STA 4.7 - 0.6 - μS

Data hold time: tHD;DAT 043.455060.95μS

Data set-up time tSU;DAT 250 - 1006-nS

Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7300 nS

Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7300 nS

Set-up time for STOP condition tSU;STO 4.0 - 0.6 - μS

Bus free time between a STOP and START

condition

tBUF 4.7 - 1.3 - μS

Capacitive load for each bus line Cb - 400 - 400 pF

Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF

SDATA max load capacitance CLOAD_SD - 30 - 30 pF

SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 KΩ

SSr

tSU;STO

tSU;STA

tHD;STA tHIGH

tLOW tSU;DAT

tHD;DAT

DATA

CLK

tBUF

trtHD;STA

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Spectral Characteristics

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LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must out-

put the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Stan-

dard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

Spectral Characteristics

Figure 63: Quantum Efficiency

350 450 550 650 750 850 950 1050 1150

Blue

Green (B)

Green (R)

Red

Quantum Efficiency (%)

Wavelength (nm)

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image SensorPackage and Die

Dimensions

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Package and Die Dimensions

Figure 64: 63-Ball iBGA Package Outline Drawing

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MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Revision History

Aptina Confidential and Proprietary

Revision History

Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/22/10

• Updated capacitor value in “Crystal Usage” on page 14

• Updated Note 4 in Table 48, “NTSC Signal Parameters,” on page 82

• Updated Figure 62: “Two-Wire Serial Bus Timing Parameters,” on page 86

• Updated Table 52, “Two-Wire Serial Bus Characteristics,” on page 86

Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/7/10

• Updated values for Sensitivity, Signal-to-noise ratio, and Pixel dynamic range in

Table 2, “Key Parameters (continued),” on page 2

• Updated temperature range for 1MB Flash in Table 14, “SPI Flash Devices,” on

page 37

• Deleted subheading under “Parallel Output (DOUT)” on page 62 and updated first

paragraph under it

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/26/09

• Updated to Production status

• Updated “Features” on page 1

• Updated Table 1, “Key Parameters,” on page 1 and Table 2, “Key Parameters

(continued),” on page 2

• Updated Table 3, “Available Part Numbers,” on page 3

• Updated “Crystal Usage” on page 14

• Updated Table 4, “Pin Descriptions,” on page 15

• Updated “Pin Assignments” on page 17

• Updated Table 6, “Reset/Default State of Interfaces,” on page 17

• Updated “Pixel Array Structure” on page 19

• Updated “Sensor Pixel Array” on page 21

• Updated “Positional Gain Adjustments (PGA)” on page 26

• Deleted 1D from “Color Correction and Aperture Correction” on page 27

• Deleted section on “Image Scaling”

• Updated “Usage Modes” on page 31

• Updated Figure 19: “External Overlay System Block Diagram,” on page 33

• Moved register tables and section on “How to Access Registers and Variables” to sepa-

rate document

• Updated “Command Flow” on page 40

• Updated Figure 28: “Single Write to Random Location,” on page 48

• Updated “Integrated Lens Distortion Correction” on page 50

• Updated Table 23, “TX Manager Host Commands,” on page 44

• Updated “Overlay Capability” on page 54

• Updated Figure 34: “Memory Partitioning,” on page 55

• Updated “Overlay Adjustment” on page 56

• Changed “Overlay Number Generator” to “Overlay Character Generator,” on page 58

• Updated Table 30, “Parallel Input Data Timing Values Using Din_CLK,” on page 65

• Updated Table 33, “Parallel Digital Output I/O Timing,” on page 70

• Updated Table 41, “Absolute Maximum Ratings,” on page 78

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Aptina, Aptina Imaging, DigitalClarity, and the Aptina logo are the property of Aptina Imaging Corporation

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final,

these specifications are subject to change, as further product development and data characterization sometimes occur.

MT9V126: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Revision History

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Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/2/08

• Added title to Table 66, “Power-Up Sequence Parameters,” on page 132 and added

units for tVDD_RESET and tEXTCLK_RESET

• Added typical value for leakage current for EXTCLK at VIN = 0V in

Table 72, “Digital I/O Parameters,” on page 138

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/9/09

•Initial release