1
LT1739
1739fas, sn1739
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
Dual 500mA, 200MHz
xDSL Line Driver Amplifier
■
3mm × 4mm High Power DFN Package
■
Exceeds All Requirements For Full Rate,
Downstream ADSL Line Drivers
■
±500mA Minimum I
OUT
■
±11.1V Output Swing, V
S
= ±12V, R
L
= 100Ω
■
±10.9V Output Swing, V
S
= ±12V, I
L
= 250mA
■
Low Distortion: –82dBc at 1MHz, 2V
P-P
Into 50Ω
■
Power Saving Adjustable Supply Current
■
Power Enhanced TSSOP-20 Small Footprint Package
■
200MHz Gain Bandwidth
■
600V/µs Slew Rate
■
Specified at ±12V and ±5V
■
High Density ADSL Central Office Line Drivers
■
High Efficiency ADSL, HDSL2, G.lite,
SHDSL Line Drivers
■
Buffers
■
Test Equipment Amplifiers
■
Cable Drivers
The LT
®
1739 is a 500mA minimum output current, dual op
amp with outstanding distortion performance. The ampli-
fiers are gain-of-ten stable, but can be easily compensated
for lower gains. The extended output swing allows for
lower supply rails to reduce system power. Supply current
is set with an external resistor to optimize power dissipa-
tion. The LT1739 features balanced, high impedance in-
puts with low input bias current and input offset voltage.
Active termination is easily implemented for further sys-
tem power reduction. Short-circuit protection and thermal
shutdown insure the device’s ruggedness.
The outputs drive a 100Ω load to ±11.1V with ±12V
supplies, and ±10.9V with a 250mA load. The LT1739 is a
pin-for-pin replacement for the LT1794 in xDSL line driver
applications and requires no circuit changes.
The LT1739 is available in the very small, thermally
enhanced, 3mm × 4mm DFN package or a 20-lead TSSOP
for maximum port density in central office line driver
applications. For a dual version of the LT1739, see the
LT6301 data sheet.
High Efficiency ±12V Supply ADSL Central Office Line Driver
1739 TA01
+
–
1/2
LT1739
–IN
–
+
1/2
LT1739
+IN
12V
SHDN
–12V
12.7Ω
R
BIAS
24.9k
1:2*
110Ω
1000pF
110Ω
1k
1k
12.7Ω
SHDNREF
100Ω
*COILCRAFT X8390-A OR EQUIVALENT
I
SUPPLY
= 10mA PER AMPLIFIER
WITH R
BIAS
= 24.9k
•
•
, LTC and LT are registered trademarks of Linear Technology Corporation.
4mm
3mm
0.8mm
1739 TA02
EXPOSED
THERMAL
PAD
3mm × 4mm DFN Package
Bottom View
2
LT1739
1739fas, sn1739
ORDER PART
NUMBER
Supply Voltage (V
+
to V
–
) ................................. ±13.5V
Input Current ..................................................... ±10mA
Output Short-Circuit Duration (Note 2)........... Indefinite
Operating Temperature Range ............... –40°C to 85°C
Specified Temperature Range (Note 3).. –40°C to 85°C
LT1739CFE
LT1739IFE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
(Note 1)
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
V
–
NC
–IN
+IN
SHDN
SHDNREF
+IN
–IN
NC
V
–
V
–
NC
OUT
V
+
NC
NC
V
+
OUT
NC
V
–
FE PACKAGE
20-LEAD PLASTIC TSSOP
T
JMAX
= 150°C, θ
JA
= 40°C/W, θ
JC
= 3°C/W (Note 4)
UNDERSIDE METAL CONNECTED TO V
–
Junction Temperature
FE Package ....................................................... 150°C
UE Package ......................................................125°C
Storage Temperature Range
FE Package ....................................... –65°C to 150°C
UE Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)..................300°C
ORDER PART
NUMBER
LT1739CUE
LT1739IUE
12
11
10
9
8
7
1
2
3
4
5
6
V–
OUT A
V+
V+
OUT B
V–
–IN A
+IN A
SHDN
SHDNREF
+IN B
–IN B
TOP VIEW
UE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
T
JMAX
= 125°C, θ
JA
= 60°C/W, θ
JC
= 3°C/W (Note 4)
UNDERSIDE METAL CONNECTED TO V
–
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
OS
Input Offset Voltage 15.0 mV
●7.5 mV
Input Offset Voltage Matching 0.3 5.0 mV
●7.5 mV
Input Offset Voltage Drift ●10 µV/°C
I
OS
Input Offset Current 100 500 nA
●800 nA
I
B
Input Bias Current ±0.1 ±4µA
●±6µA
Input Bias Current Matching 100 500 nA
●800 nA
e
n
Input Noise Voltage Density f = 10kHz 8 nV/√Hz
i
n
Input Noise Current Density f = 10kHz 0.8 pA/√Hz
UE PART
MARKING
1739
1739I
3
LT1739
1739fas, sn1739
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C.
VCM = 0V, pulse tested, ±5V ≤ VS ≤ ±12V, VSHDNREF = 0V, RBIAS = 24.9k between V+ and SHDN unless otherwise noted. (Note 3)
R
IN
Input Resistance V
CM
= (V
+
– 2V) to (V
–
+ 2V) ●550 MΩ
Differential 6.5 MΩ
C
IN
Input Capacitance 3pF
Input Voltage Range (Positive) (Note 5) ●V
+
– 2 V
+
– 1 V
Input Voltage Range (Negative) (Note 5) ●V
–
+ 1 V
–
+ 2 V
CMRR Common Mode Rejection Ratio V
CM
= (V
+
– 2V) to (V
–
+ 2V) 74 83 dB
●66 dB
PSRR Power Supply Rejection Ratio V
S
= ±4V to ±12V 74 88 dB
●66 dB
A
VOL
Large-Signal Voltage Gain (Note 8) V
S
= ±12V, V
OUT
= ±10V, R
L
= 40Ω63 76 dB
●57 dB
V
S
= ±5V, V
OUT
= ±3V, R
L
= 25Ω60 70 dB
●54 dB
V
OUT
Output Swing (Note 8) V
S
= ±12V, R
L
= 100Ω10.9 11.1 ±V
●10.7 ±V
V
S
= ±12V, I
L
= 250mA 10.6 10.9 ±V
●10.4 ±V
V
S
= ±5V, R
L
= 25Ω3.7 4.0 ±V
●3.5 ±V
V
S
= ±5V, I
L
= 250mA 3.6 3.9 ±V
●3.4 ±V
I
OUT
Maximum Output Current (Note 8) V
S
= ±12V, R
L
= 1Ω500 1200 mA
I
S
Supply Current per Amplifier V
S
= ±12V, R
BIAS
= 24.9k (Note 6) 8.0 10 13.5 mA
●6.7 15.0 mA
V
S
= ±12V, R
BIAS
= 32.4k (Note 6) 8 mA
V
S
= ±12V, R
BIAS
= 43.2k (Note 6) 6 mA
V
S
= ±12V, R
BIAS
= 66.5k (Note 6) 4 mA
V
S
= ±5V, R
BIAS
= 24.9k (Note 6) 2.2 3.4 5.0 mA
●1.8 5.8 mA
Supply Current in Shutdown V
SHDN
= 0.4V 0.1 1 mA
Output Leakage in Shutdown V
SHDN
= 0.4V 0.3 1 mA
Channel Separation (Note 8) V
S
= ±12V, V
OUT
= ±10V, R
L
= 40Ω80 110 dB
●77 dB
SR Slew Rate V
S
= ±12V, A
V
= –10, (Note 7) 300 600 V/µs
V
S
= ±5V, A
V
= –10, (Note 7) 100 200 V/µs
HD2 Differential 2nd Harmonic Distortion V
S
= ±12V, A
V
= 10, 2V
P-P
, R
L
= 50Ω, 1MHz –85 dBc
HD3 Differential 3rd Harmonic Distortion V
S
= ±12V, A
V
= 10, 2V
P-P
, R
L
= 50Ω, 1MHz –82 dBc
GBW Gain Bandwidth f = 1MHz 200 MHz
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Applies to short circuits to ground only. A short circuit between
the output and either supply may permanently damage the part when
operated on supplies greater than ±10V.
Note 3: The LT1739C is guaranteed to meet specified performance from
0°C to 85°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at –40°C. The LT1739I is
guaranteed to meet the extended temperature limits.
Note 4: Thermal resistance varies depending upon the amount of PC board
metal attached to the device and rate of air flow over the device. If the
maximum dissipation of the package is exceeded, the device will go into
thermal shutdown and be protected.
Note 5: Guaranteed by the CMRR tests.
Note 6: R
BIAS
is connected between V
+
and the SHDN pin, with the
SHDNREF pin grounded.
Note 7: Slew rate is measured at ±5V on a ±10V output signal while
operating on ±12V supplies and ±1V on a ±3V output signal while
operating on ±5V supplies.
Note 8: This parameter of the LT1739CUE/LT1739IUE is 100% tested at
room temperature, but is not tested at –40°C, 0°C or 85°C.
4
LT1739
1739fas, sn1739
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current
vs Ambient Temperature Input Common Mode Range
vs Supply Voltage Input Bias Current
vs Ambient Temperature
SUPPLY VOLTAGE (±V)
2
V–
COMMON MODE RANGE (V)
1.0
2.0
–2.0
46810
1739 G02
12
–1.0
V+
0.5
1.5
–1.5
–0.5
14
TA = 25°C
∆VOS > 1mV
TEMPERATURE (°C)
–50
I
SUPPLY
PER AMPLIFIER (mA)
11
13
15
1739 G01
9
7
10
12
14
8
6
5–30 –10 10 30 50 70 90
V
S
= ±12V
R
BIAS
= 24.9k TO SHDN
V
SHDNREF
= 0V
TEMPERATURE (°C)
–50
±I
BIAS
(nA)
120
160
200
50
1739 G03
80
40
100
140
180
60
20
0–30 –10 10 30 70 90
V
S
= ±12V
I
S
PER AMPLIFIER = 10mA
Input Noise Spectral Density Output Short-Circuit Current
vs Ambient Temperature Output Saturation Voltage
vs Ambient Temperature
FREQUENCY (Hz)
1
INPUT VOLTAGE NOISE (V/√Hz)
INPUT CURRENT NOISE (pA/√Hz)
10
1 100 1k 10k
1739 G04
0.1 10
100
1
10
0.1
100
100k
e
n
i
n
T
A
= 25°C
V
S
= ±12V
I
S
PER AMPLIFIER = 10mA
TEMPERATURE (°C)
–50
600
I
SC
(mA)
620
660
680
700
800
740
–10 30 50
1739 G05
640
760
780
720
–30 10 70 90
V
S
= ±12V
I
S
PER AMPLIFIER = 10mA
SINKING
SOURCING
TEMPERATURE (°C)
–50
OUTPUT SATURATION VOLTAGE (V)
–0.5
10
1739 G06
1.0
–30 –10 30
0.5
V
–
V
+
–1.0
–1.5
1.5
50 70 90
V
S
= ±12V
R
L
= 100Ω
R
L
= 100Ω
I
LOAD
= 250mA
I
LOAD
= 250mA
Open-Loop Gain and Phase
vs Frequency –3dB Bandwidth
vs Supply Current Slew Rate vs Supply Current
FREQUENCY (Hz)
–20
GAIN (dB)
PHASE (DEG)
100
120
–40
–60
80
20
60
40
0
100k 10M 100M
1739 G07
–80
–160
80
120
–200
–240
40
–80
0
–40
–120
–280
1M
TA = 25°C
VS = ±12V
AV = –10
RL = 100Ω
IS PER AMPLIFIER = 10mA
PHASE
GAIN
SUPPLY CURRENT PER AMPLIFIER (mA)
2
0
–3dB BANDWIDTH (MHz)
5
15
20
25
6 8 10 12 14
45
1739 G08
10
4
30
35
40
T
A
= 25°C
V
S
= ±12V
A
V
= 10
R
L
= 100Ω
SUPPLY CURRENT PER AMPLIFIER (mA)
2
SLEW RATE (V/µs)
600
800
1000
11 12
1739 G09
400
200
500
700
900
300
100
0345678910 13 14 15
T
A
= 25°C
V
S
= ±12V
A
V
= –10
R
L
= 1k RISING
FALLING
5
LT1739
1739fas, sn1739
TYPICAL PERFOR A CE CHARACTERISTICS
UW
CMRR vs Frequency PSRR vs Frequency Frequency Response
vs Supply Current
FREQUENCY (MHz)
0.1
40
COMMON MODE REJECTION RATIO (dB)
50
60
70
80
1 10 100
1739 G10
30
20
10
0
90
100 T
A
= 25°C
V
S
= ±12V
I
S
= 10mA PER AMPLIFIER
FREQUENCY (MHz)
30
POWER SUPPLY REJECTION (dB)
90
100
20
10
80
50
70
60
40
0.01 1 10 100
1739 G11
–10
0
0.1
V
S
= ±12V
A
V
= 10
I
S
= 10mA PER AMPLIFIER
(–) SUPPLY
(+) SUPPLY
FREQUENCY (Hz)
1k 10k
0
GAIN (dB)
5
10
15
20
100k 1M 10M 100M
1739 G12
–5
–10
–15
–20
25
30 V
S
= ±12V
A
V
= 10
2mA PER AMPLIFIER
10mA PER AMPLIFIER
15mA PER AMPLIFIER
Output Impedance vs Frequency ISHDN vs VSHDN Supply Current vs VSHDN
FREQUENCY (MHz)
0.01 0.1
0.01
OUTPUT IMPEDANCE (Ω)
1
1000
1 10 100
1739 G13
0.1
10
100
T
A
= 25°C
V
S
±12V
I
S
PER
AMPLIFIER = 2mA
I
S
PER
AMPLIFIER = 10mA
I
S
PER
AMPLIFIER = 15mA
V
SHDN
(V)
0
I
SHDN
(mA)
1.5
2.0
2.5
4.0
1739 G14
1.0
0.5
01.0 2.0 3.0 5.0
3.5
0.5 1.5 2.5 4.5
T
A
= 25°C
V
S
= ±12V
V
SHDNREF
= 0V
VSHDN (V)
0
SUPPLY CURRENT PER AMPLIFIER (mA)
15
20
25
30
35
4.0
1739 G14
10
5
01.0 2.0 3.0 5.0
3.5
0.5 1.5 2.5 4.5
TA = 25°C
VS = ±12V
VSHDNREF = 0V
Differential Harmonic Distortion
vs Output Amplitude
V
OUT(P-P)
–100
DISTORTION (dBc)
–90
–70
–60
–50
4 8 10 12 14 16 18
1739 G16
–80
02 6
–40 f = 1MHz
T
A
= 25°C
V
S
= ±12V
A
V
= 10
R
L
= 50Ω
I
S
PER AMPLIFIER = 10mA
HD3
HD2
Differential Harmonic Distortion
vs Frequency
FREQUENCY (kHz)
DISTORTION (dBc)
–60
–50
–40
800
1739 G17
–70
–80
–65
–55
–45
–75
–85
–90 200100 400300 600 700 900
500 1000
V
O
= 10V
P-P
T
A
= 25°C
V
S
= ±12V
A
V
= 10
R
L
= 50Ω
I
S
PER AMPLIFIER = 10mA
HD3
HD2
6
LT1739
1739fas, sn1739
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Undistorted Output Swing
vs Frequency
FREQUENCY (Hz)
100k
0
OUTPUT VOLTAGE (V
P-P
)
5
10
15
20
300k 1M 3M 10M
1739 G19
SFDR > 40dB
T
A
= 25°C
V
S
= ±12V
A
V
= 10
R
L
= 50Ω
I
S
PER AMPLIFIER = 10mA
+IN A
–IN A
–12V 1k
12V
SHDN
OUT A
OUT B
R
BIAS
110Ω
OUT (+)
OUT (–)
10k
E
IN
0.01µF
R
L
≈ 50Ω
1:2*
10k
49.9Ω110Ω
12.7Ω
1739 TC
SHDNREF
V
–
V
+
–
+
A
–IN B
+IN B
1k
0.1µF 4.7µF
0.1µF
12V
–12V
–
+
B
–12V
12.7Ω
V
OUT(P-P)
100 LINE LOAD
SUPPLY BYPASSING
*COILCRAFT X8390-A OR EQUIVALENT
V
OUTP-P
AMPLITUDE SET AT EACH AMPLIFIER OUTPUT
DISTORTION MEASURED ACROSS LINE LOAD
SPLITTER
MINICIRCUITS
ZSC5-2-2
+
+
4.7µF
+
0.1µF4.7µF
TEST CIRCUIT
Differential Harmonic Distortion
vs Supply Current
I
SUPPLY
PER AMPLIFIER (mA)
–85
DISTORTION (dBc)
–80
–70
–65
–60
78910
–40
1739 G18
–75
23456 11
–55
–50
–45
V
O
= 10V
P-P
V
S
= ±12V
A
V
= 10
R
L
= 50Ω
f = 1MHz, HD3
f = 1MHz, HD2
f = 100kHz, HD2
f = 100kHz, HD3
7
LT1739
1739fas, sn1739
APPLICATIO S I FOR ATIO
WUUU
The LT1739 is a high speed, 200MHz gain bandwidth
product, dual voltage feedback amplifier with high output
current drive capability, 500mA source and sink. The
LT1739 is ideal for use as a line driver in xDSL data
communication applications. The output voltage swing
has been optimized to provide sufficient headroom when
operating from ±12V power supplies in full-rate ADSL
applications. The LT1739 also allows for an adjustment of
the operating current to minimize power consumption. In
addition, the LT1739 is available in small footprint
3mm × 4mm DFN and 20-lead TSSOP surface mount
package to minimize PCB area in multiport central office
DSL cards.
To minimize signal distortion, the LT1739 amplifiers are
decompensated to provide very high open-loop gain at
high frequency. As a result each amplifier is frequency
stable with a closed-loop gain of 10 or more. If a closed-
loop gain of less than 10 is desired, external frequency
compensating components can be used.
Setting the Quiescent Operating Current
Power consumption and dissipation are critical concerns
in multiport xDSL applications. Two pins, Shutdown
(SHDN) and Shutdown Reference (SHDNREF), are pro-
vided to control quiescent power consumption and allow
for the complete shutdown of the driver. The quiescent
current should be set high enough to prevent distortion
induced errors in a particular application, but not so high
that power is wasted in the driver unnecessarily. A good
starting point to evaluate the LT1739 is to set the quiescent
current to 10mA per amplifier.
The internal biasing circuitry is shown in Figure 1. Ground-
ing the SHDNREF pin and directly driving the SHDN pin with
a voltage can control the operating current as seen in the
Typical Performance Characteristics. When the SHDN pin
is less than SHDNREF + 0.4V, the driver is shut down and
consumes typically only 100µA of supply current and the
outputs are in a high impedance state. Part to part varia-
tions, however, will cause inconsistent control of the qui-
escent current if direct voltage drive of the SHDN pin is used.
Using a single external resistor, R
BIAS
, connected in one of
two ways provides a much more predictable control of the
quiescent supply current. Figure 2 illustrates the effect
on supply current per amplifier with R
BIAS
connected
between the SHDN pin and the 12V V
+
supply of the
LT1739 and the approximate design equations. Figure 3
illustrates the same control with R
BIAS
connected between
the SHDNREF pin and ground while the SHDN pin is tied
to V
+
. Either approach is equally effective.
Figure 1. Internal Current Biasing Circuitry
2k
SHDN
SHDNREF
TO
START-UP
CIRCUITRY
1k
1739 F01
I
BIAS
TO AMPLIFIERS
BIAS CIRCUITRY
2I
I2I
5I
2
5
I
BIAS
=
I
SUPPLY
PER AMPLIFIER (mA) = 64 • I
BIAS
I
SHDN
= I
SHDNREF
R
BIAS
(kΩ)
0
I
SUPPLY
PER AMPLIFIER (mA)
10
20
30
5
15
25
10
1739 F02
7 40 70 100 130 160 190
V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
= • 25.6 – 2k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA) • 25.6
V
+
– 1.2V
R
BIAS
+ 2k
≈
R
BIAS
(kΩ)
4 7 10 50 90 130 170 210 25030 70 100 150 190 230 270 290
I
SUPPLY
PER AMPLIFIER (mA)
20
25
30
35
40
1739 F03
5
10
15
0
45 V
S
= ±12V
V
+
= 12V
R
BIAS
SHDN
SHDNREF
R
BIAS
= • 64 – 5k
V
+
– 1.2V
I
S
PER AMPLIFIER (mA)
I
S
PER AMPLIFIER
(mA) • 64
V
+
– 1.2V
R
BIAS
+ 5k
≈
Figure 2. RBIAS to V+ Current Control
Figure 3. RBIAS to Ground Current Control
8
LT1739
1739fas, sn1739
Two Control Inputs
RESISTOR VALUES (kΩ)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C1
R
CO
3V
40.2
11.5
19.1
3.3V
43.2
13.0
22.1
5V
60.4
21.5
36.5
3V
4.99
8.66
14.3
3.3V
6.81
10.7
17.8
5V
19.6
20.5
34.0
V
C0
H
L
H
L
V
C1
H
H
L
L
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
10
7
5
2
SUPPLY CURRENT PER AMPLIFIER (mA)
One Control Input
RESISTOR VALUES (kΩ)
R
SHDN
TO V
CC
(12V) R
SHDN
TO V
LOGIC
V
LOGIC
R
SHDN
R
C
3V
40.2
7.32
3.3V
43.2
8.25
5V
60.4
13.7
3V
4.99
5.49
3.3V
6.81
6.65
5V
19.6
12.7
V
C
H
L
10
2
10
2
10
2
10
2
10
2
10
2
SUPPLY CURRENT PER AMPLIFIER (mA)
R
SHDN
R
C1
V
C1
V
LOGIC
12V OR V
LOGIC
0V V
C0
R
C0
SHDN
SHDNREF
2k
R
SHDN
R
C
V
C
V
LOGIC
12V OR V
LOGIC
0V SHDN
SHDNREF
1739 F04
2k
APPLICATIO S I FOR ATIO
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Logic Controlled Operating Current
The DSP controller in a typical xDSL application can have
I/O pins assigned to provide logic control of the LT1739
line driver operating current. As shown in Figure 4 one or
two logic control inputs can set two or four different
operating modes. The logic inputs add or subtract current
to the SHDN input to set the operating current. The one
logic input example selects the supply current to be either
full power, 10mA per amplifier or just 2mA per amplifier,
which significantly reduces the driver power consumption
while maintaining less than 2Ω output impedance to
frequencies less than 1MHz. This low power mode retains
termination impedance at the amplifier outputs and the
line driving back termination resistors. With this termina-
tion, while a DSL port is not transmitting data, it can still
sense a received signal from the line across the back-
termination resistors and respond accordingly.
The two logic input control provides two intermediate
(approximately 7mA per amplifier and 5mA per amplifier)
operating levels between full power and termination
modes. For proper operation of the current control cir-
cuitry, it is necessary that the SHDNREF pin be biased at
least 2V more positive than V
–
. In single supply applica-
tions where V
–
is at ground potential, special attention to
the DC bias of the SHDNREF pin is required. Contact
Linear Technology for assistance in implementing a single
supply design with operating current control. These
modes can be useful for overall system power manage-
ment when full power transmissions are not necessary.
Shutdown and Recovery
The ultimate power saving action on a completely idle port
is to fully shut down the line driver by pulling the SHDN pin
to within 0.4V of the SHDNREF potential. As shown in
Figure 5 complete shutdown occurs in less than 10µs and,
more importantly, complete recovery from the shut down
state to full operation occurs in less than 2µs. The biasing
circuitry in the LT1739 reacts very quickly to bring the
amplifiers back to normal operation.
Figure 4. Providing Logic Input Control of Operating Current
V
SHDN
SHDNREF = 0V
AMPLIFIER
OUTPUT
1794 F05
Figure 5. Shutdown and Recovery Timing
Power Dissipation and Heat Management
xDSL applications require the line driver to dissipate a
significant amount of power and heat compared to other
components in the system. The large peak to RMS varia-
tions of DMT and CAP ADSL signals require high supply
voltages to prevent clipping, and the use of a step-up
transformer to couple the signal to the telephone line can
require high peak current levels. These requirements
result in the driver package having to dissipate significant
amounts of power. Several multiport cards inserted into
a rack in an enclosed central office box can add up to
many, many watts of power dissipation in an elevated
ambient temperature environment. The LT1739 has built-
in thermal shutdown cir
cuitry that will protect the ampli-
fiers if operated at excessive temperatures, however data
transmissions will be seriously impaired. It is important in
9
LT1739
1739fas, sn1739
the design of the PCB and card enclosure to take measures
to spread the heat developed in the driver away to the
ambient environment to prevent thermal shutdown (which
occurs when the junction temperature of the LT1739
exceeds 165°C).
Estimating Line Driver Power Dissipation
Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mWRMS of power on to the 100Ω
telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1739 is
set to 10mA per amplifier.
The power dissipated in the LT1739 is a combination of the
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
the upper power transistor of one amplifier, while sourc-
ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:
P
D
= P
QUIESCENT
+ P
Q(UPPER)
+ P
Q(LOWER)
P
D
= (V
+
– V
–
) • I
Q
+ (V
+
– V
OUTARMS
) •
I
LOAD
+ (V
–
– V
OUTBRMS
) • I
LOAD
With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies-
cent driver power dissipation is:
P
DQ
= 24V • 20mA = 480mW
This can be reduced in many applications by operating
with a lower quiescent current value.
When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.
APPLICATIO S I FOR ATIO
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Figure 6. Estimating Line Driver Power Dissipation
1739 F06
+
–
B
–IN
–
+
A
+IN
12V
20mA DC
SHDN
–12V
–2V
RMS
17.4Ω
24.9k – SETS I
Q
PER AMPLIFIER = 10mA
1:1.7
110Ω
1000pF
110Ω
1k
1k
17.4Ω
SHDNREF
100Ω3.16V
RMS
I
LOAD
= 57mA
RMS
•
•
2V
RMS
10
LT1739
1739fas, sn1739
APPLICATIO S I FOR ATIO
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At full power to the line the driver power dissipation is:
P
D(FULL)
= 24V • 8mA + (12V – 2V
RMS
) • 57mA
RMS
+ [|–12V – (–2V
RMS
)|] • 57mA
RMS
P
D(FULL)
= 192mW + 570mW + 570mW = 1.332W*
The junction temperature of the driver must be kept less
than the thermal shutdown temperature when processing
a signal. The junction temperature is determined from the
following expression:
T
J
= T
AMBIENT
(°C) + P
D(FULL)
(W) • θ
JA
(°C/W)
θ
JA
is the thermal resistance from the junction of the
LT1739 to the ambient air, which can be minimized by
heat-spreading PCB metal and airflow through the enclo-
sure as required. For the example given, assuming a
maximum ambient temperature of 85°C and keeping the
junction temperature of the LT1739 to 140°C maximum,
the maximum thermal resistance from junction to ambient
required is:
θJA MAX CC
WCW
() –
../=°°
=°
140 85
1 332 41 3
Heat Sinking Using PCB Metal
Designing a thermal management system is often a trial
and error process as it is never certain how effective it is
until it is manufactured and evaluated. As a general rule,
the more copper area of a PCB used for spreading heat
away from the driver package, the more the operating
junction temperature of the driver will be reduced. The
limit to this approach however is the need for very
compact circuit layout to allow more ports to be imple-
mented on any given size PCB.
Fortunately xDSL circuit boards use multiple layers of
metal for interconnection of components. Areas of metal
beneath the LT1739 connected together through several
small 13 mil vias can be effective in conducting heat away
from the driver package. The use of inner layer metal can
free up top and bottom layer PCB area for external compo-
nent placement.
Figure 8 shows examples of PCB metal being used for heat
spreading. These are provided as a reference for what
might be expected when using different combinations of
metal area on different layers of a PCB. These examples are
with a 4-layer board using 1oz copper on each. The most
effective layers for spreading heat are those closest to the
LT1739 junction. The small TSSOP and DFN packages are
very effective for compact line driver designs. Both pack-
ages also have an exposed metal heat sinking pad on the
bottom side which, when soldered to the PCB top layer
metal, directly conducts heat away from the IC junction.
Soldering the thermal pad to the board produces a thermal
resistance from junction to case, θ
JC
, of approximately
3°C/W.
As a minimum, the area directly beneath the package on all
PCB layers can be used for heat spreading. Limiting the
area of metal to just that of the exposed metal heat sinking
pad however is not very effective, particularly if the ampli-
fiers are required to dissipate significant power levels.
This is shown in Figure 8 for both the TSSOP and DFN
packages. Expanding the area of metal on various layers
significantly reduces the overall thermal resistance. If
possible, an entire unbroken plane of metal close to the
heat sinking pad is best for multiple drivers on one PCB
card. The addition of vias (small 13mil or smaller holes
which fill during PCB plating) connecting all layers of heat
spreading metal also helps to reduce operating tempera-
tures of the driver. These too are shown in Figure␣ 8.
Important Note: The metal planes used for heat sinking
the LT1739 are electrically connected to the negative
supply potential of the driver, typically –12V. These
planes must be isolated from any other power planes
used in the board design.
Figure 7. IQ vs ILOAD
I
LOAD
(mA)
–240 –200 –160 –120 –80 –40 0 40 80 120 160 200 240
TOTAL I
Q
(mA)
10
15
20
1739 F07
5
0
25
*Note: Design techniques exist to significantly reduce this value. (See Line Driving Back Termination)
11
LT1739
1739fas, sn1739
APPLICATIO S I FOR ATIO
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Figure 8. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top Layer.
Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size
When PCB cards containing multiple ports are inserted
into a rack in an enclosed cabinet, it is often necessary to
provide airflow through the cabinet and over the cards. As
seen in the graph of Figure 8, this is also very effective in
further reducing the junction-to-ambient thermal resis-
tance of each line driver.
STILL AIR θ
JA
TSSOP
100°C/W
TSSOP
50°C/W
TSSOP
45°C/W
DFN
130°C/W
PACKAGE TOP LAYER 2ND LAYER 3RD LAYER BOTTOM LAYER
DFN
75°C/W
1739 F08a
AIRFLOW (LINEAR FEET PER MINUTE, lfpm)
–50
–60
REDUCTION IN θ
JA
(%)
–30
–10
0
–40
–20
200 400 600 800
1739 F08b
10001000 300 500
Typical Reduction in θJA with
Laminar Airflow Over the Device
700 900
% REDUCTION RELATIVE
TO θ
JA
IN STILL AIR
12
LT1739
1739fas, sn1739
Layout and Passive Components
With a gain bandwidth product of 200MHz the LT1739
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors (i.e.,
0.1µF). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1µF to 10µF).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
Compensation
The LT1739 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.
Figure␣ 9 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
parallel combination of RC and RG is less than or equal to
RF/9. For lowest distortion and DC output offset, a series
capacitor, CC, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by RC
and CC should be less than 5MHz to minimize peaking.
Figure 10 shows compensation in the noninverting con-
figuration. The R
C
, C
C
network acts similarly to the invert-
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
Another compensation scheme for noninverting circuits is
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + R
F
/R
G
at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + R
F
/R
G
at mid-band and for stability, a gain of 10 or
greater at high frequencies.
Figure 9. Compensation for Inverting Gains
APPLICATIO S I FOR ATIO
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R
G
R
C
V
O
V
I
C
C
(OPTIONAL)
–
+
1739 F09
R
F
= –R
F
R
G
V
O
V
I
< 5MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
R
C
V
O
V
I
C
C
(OPTIONAL)
+
–
1739 F10
R
F
R
G
= 1 + R
F
R
G
V
O
V
I
< 5MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
Figure 10. Compensation for Noninverting Gains
+
–
1739 F11
R
F
R
G
V
i
V
O
C
C
< 5MHz
1
2πR
G
C
C
R
G
≤ R
F
/9
= 1 (LOW FREQUENCIES)
(HIGH FREQUENCIES)
V
O
V
I
= 1 + R
F
R
G
Figure 11. Alternate Noninverting Compensation
R
C
V
O
V
I
C
C
+
–
1739 F12
R
F
R
G
C
BIG
R
F
R
G
= 1 AT LOW FREQUENCIES
= 1 + AT MEDIUM FREQUENCIES
R
F
(R
C
|| R
G
)
= 1 + AT HIGH FREQUENCIES
V
O
V
I
Figure 12. Combination Compensation
13
LT1739
1739fas, sn1739
In differential driver applications, as shown on the first
page of this data sheet, it is recommended that the gain
setting resistor be comprised of two equal value resistors
connected to a good AC ground at high frequencies. This
ensures that the feedback factor of each amplifier remains
less than 0.1 at any frequency. The midpoint of the
resistors can be directly connected to ground, with the
resulting DC gain to the V
OS
of the amplifiers, or just
bypassed to ground with a 1000pF or larger capacitor.
Line Driving Back-Termination
The standard method of cable or line back-termination is
shown in Figure 13. The cable/line is terminated in its
characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.).
A back-termination resistor also equal to the chararacteristic
impedance should be used for maximum pulse fidelity of
outgoing signals, and to terminate the line for incoming
signals in a full-duplex application. There are three main
drawbacks to this approach. First, the power dissipated in
the load and back-termination resistors is equal so half of
the power delivered by the amplifier is wasted in the
termination resistor. Second, the signal is halved so the
gain of the amplifer must be doubled to have the same
overall gain to the load. The increase in gain increases
noise and decreases bandwidth (which can also increase
distortion). Third, the output swing of the amplifier is
doubled which can limit the power it can deliver to the load
for a given power supply voltage.
An alternate method of back-termination is shown in
Figure 14. Positive feedback increases the effective back-
termination resistance so R
BT
can be reduced by a factor
of n. To analyze this circuit, first ground the input. As R
BT
␣=
R
L
/n, and assuming R
P2
>>R
L
we require that:
∆V
A
= ∆V
O
(1 – 1/n) to increase the effective value of
R
BT
by n.
∆V
P
= ∆V
O
(1 – 1/n)/(1 + R
F
/R
G
)
∆V
O
= ∆V
P
(1 + R
P2
/R
P1
)
APPLICATIO S I FOR ATIO
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+
–
1739 F13
RF
RBT
CABLE OR LINE WITH
CHARACTERISTIC IMPEDANCE RL
RG
VO
VI
RL
(1 + RF/RG)
=
VO
VI
1
2
RBT = RL
Figure 13. Standard Cable/Line Back Termination
+
–
1739 F14
RF
RBT
RP2
RP1
RG
VIVA
VPVO
RL
RF
RG
1 +
RL
n
=
VO
VI
= 1 –
–
1
n
FOR RBT =
()
RF
RG
1 +
()
RP1
RP1 + RP2
RP1
RP2 + RP1
RP2/(RP2 + RP1)
()
1 + 1/n
Figure 14. Back Termination Using Postive Feedback
Eliminating ∆V
P
, we get the following:
(1 + R
P2
/R
P1
) = (1 + R
F
/R
G
)/(1 – 1/n)
For example, reducing R
BT
by a factor of n = 4, and with an
amplifer gain of (1 + R
F
/R
G
) = 10 requires that R
P2
/R
P1
=␣ 12.3.
Note that the overall gain is increased:
V
V
RRR
nRRRRR
O
I
PPP
FG P P P
=+
()
+
()
+
()
[]
−+
()
[]
221
12 1
11 1
/
// / /
14
LT1739
1739fas, sn1739
APPLICATIO S I FOR ATIO
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A simpler method of using positive feedback to reduce the
back-termination is shown in Figure 15. In this case, the
drivers are driven differentially and provide complemen-
tary outputs. Grounding the inputs, we see there is invert-
ing gain of –R
F
/R
P
from –V
O
to V
A
∆V
A
= ∆V
O
(R
F
/R
P
)
and assuming R
P
>> R
L
, we require
∆V
A
= ∆V
O
(1 – 1/n)
solving
R
F
/R
P
= 1 – 1/n
So to reduce the back-termination by a factor of 3 choose
R
F
/R
P
= 2/3. Note that the overall gain is increased to:
V
O
/V
I
= (1 + R
F
/R
G
+ R
F
/R
P
)/[2(1 – R
F
/R
P
)]
Using positive feedback is often referred to as active
termination.
Figure 18 shows a full-rate ADSL line driver incorporating
positive feedback to reduce the power lost in the back
termination resistors by 40% yet still maintains the proper
impedance match to the100Ω characteristic line imped-
ance. This circuit also reduces the transformer turns ratio
over the standard line driving approach resulting in lower
peak current requirements. With lower current and less
power loss in the back termination resistors, this driver
dissipates only 1W of power, a 30% reduction. (Additional
power savings are possible by further reducing the termi-
nation resistors’ value).
While the power savings of positive feedback are attractive
there is one important system consideration to be ad-
dressed, received signal sensitivity. The signal received
from the line is sensed across the back termination resis-
tors. With positive feedback, signals are present on both
ends of the R
BT
resistors, reducing the sensed amplitude.
Extra gain may be required in the receive channel to
compensate, or a completely separate receive path may be
implemented through a separate line coupling transformer.
A demo board, DC306A-C, is available for the LT1739CFE.
This demo board is a complete line driver with an LT1361
receiver included. It allows the evaluation of both standard
and active termination approaches. It also has circuitry
built in to evaluate the effects of operating with reduced
supply current. The schematic of this demo board is
shown in Figure 17.
Considerations for Fault Protection
The basic line driver design, shown on the front page of
this data sheet, presents a direct DC path between the
outputs of the two amplifiers. An imbalance in the DC
biasing potentials at the noninverting inputs through
either a fault condition or during turn-on of the system can
create a DC voltage differential between the two amplifier
outputs. This condition can force a considerable amount
of current to flow as it is limited only by the small valued
back-termination resistors and the DC resistance of the
transformer primary. This high current can possibly cause
the power supply voltage source to drop significantly
impacting overall system performance. If left unchecked,
the high DC current can heat the LT1739 to thermal
shutdown.
–
+
R
BT
R
F
R
G
R
P
R
P
R
G
R
L
R
L
–V
I
V
A
–V
A
V
I
–V
O
V
O
–
+
R
BT
1739 F15
R
F
R
L
n
=
V
O
V
I
n =
1 –2
FOR R
BT
=
R
F
R
P
R
F
R
P
+
R
F
R
G
1 +
1 – R
F
R
P
1
()
Figure 15. Back Termination Using Differential Postive Feedback
15
LT1739
1739fas, sn1739
Using DC blocking capacitors, as shown in Figure 16, to
AC couple the signal to the transformer eliminates the
possibility for DC current to flow under any conditions.
These capacitors should be sized large enough to not
impair the frequency response characteristics required for
the data transmission.
Another important fault related concern has to do with
very fast high voltage transients appearing on the tele-
phone line (lightning strikes for example). TransZorbs
®
,
varistors and other transient protection devices are often
used to absorb the transient energy, but in doing so also
1739 F16
+
–
1/2
LT1739
–IN
–
+
1/2
LT1739
+IN
12V
SHDN
–12V
12.7Ω0.1µF
12V –12V
24.9k
1:2
LINE
LOAD
110Ω
1000pF
110Ω
1k
1k
12.7Ω
SHDNREF
•
•
0.1µF
12V –12V
BAV99
BAV99
Figure 16. Protecting the Driver Against Load Faults and Line Transients
create fast voltage transitions themselves that can be
coupled through the transformer to the outputs of the line
driver. Several hundred volt transient signals can appear
at the primary windings of the transformer with current
into the driver outputs limited only by the back termination
resistors. While the LT1739 has clamps to the supply rails
at the output pins, they may not be large enough to handle
the significant transient energy. External clamping diodes,
such as BAV99s, at each end of the transformer primary
help to shunt this destructive transient energy away from
the amplifier outputs.
TransZorb is a registered trademark of General Instruments, GSI
APPLICATIO S I FOR ATIO
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16
LT1739
1739fas, sn1739
212
9
19
1739 SD
++
–
+
–
+
–
+
–
+
–
+
+
–
20 10
11 1
1
V
DD
V
EE
ON/OFF
ON
123
JP3
GND
OUT IN
LT1121CST-5
SOT233
C2
1µF
25V
3216
C3
1µF
25V
3216
+
C5
10µF
35V
7343
+
C7
1µF
25V
3216
C4
0.1µF
25V
0603
C6
0.1µF
C1
0.1µF
C9
0.1µF
C13
0.1µF
C14
0.1µF
C11
1µF
25V
3216
C10
0.1µF
+
5V
V
DD
V
CC
V
CC
V
CC
V
EE
V
EE
E1
V
CC
E3
GND
E4
LINE (+)
E2
DRV (+)
E8
DRV (–)
E10
ON/OFF
E11
V
C0NTROL
E7
RCV
IN
(+)
E13
RCV
IN
(–)
E12
RCV (–)
E9
RCV (+)
E5
LINE (–)
E6
V
EE
PLACE C4 AND C5
AS CLOSE TO
U2 AS POSSIBLE
U1
C8
0.1µF
100V
C12
0.1µF
100V
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3
3
33
3
3
3
33
4
4
4
4
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
10
COILCRAFT
X8504-A
U3A
LT1361CS8
U3B
LT1361CS8
U4A
LT1541CS8
U4B
LT1541CS8
14
1718
R2
10k
R13
10k
R18
10k
R22
10k
R21
10k
R23
OPT
R25
107Ω
R24
107Ω
R5
OPT
C15
OPT
R15
OPT
R26
OPT
C17
OPT
C16
1000pF
C18
OPT
1206
JP6
JP5
JP4
JP2
R3
1k
R6
2.49k
R4
2.49k
R7
1k
U2A
LT1739CFE
U2B
LT1739CFE
V
BIAS
V
BIAS
ADJ FIXED
Q1
FMMT3904
R17
21.5k
R8
15.4Ω
1/2W
2010
R11
1.6k
R14
1.6k
R10
1k
R19
1k
R16
1k
R12
1k
R20
9.31k
13
R1
15.4Ω
1/2W
2010
JP1
R9
10k
Figure 17. LT1739, LT1361 ADSL Demo Board (DC306A-C)
APPLICATIO S I FOR ATIO
WUUU
17
LT1739
1739fas, sn1739
–IN
V
+
Q1 Q5
R1
V
–
+IN OUT
Q2
Q3
Q12
Q4
Q7
Q8
Q6
Q16
Q17
Q15
Q14
Q9
C2
C1
Q13
Q18
1739 SS
Q10
Q11
(one amplifier shown)
SI PLIFIED SCHE ATIC
WW
18
LT1739
1739fas, sn1739
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
FE20 (CA) TSSOP 0203
0.09 – 0.20
(.0036 – .0079)
0° – 8°
RECOMMENDED SOLDER PAD LAYOUT
0.45 – 0.75
(.018 – .030)
4.30 – 4.50*
(.169 – .177)
6.40
BSC
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
4.95
(.195)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
19
LT1739
1739fas, sn1739
U
PACKAGE DESCRIPTIO
UE12 Package
12-Lead Plastic DFN (3mm × 4mm)
(Reference LTC DWG # 05-08-1695)
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE IS A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
0.23 ± 0.05
3.30 ±0.10
(2 SIDES)
16
127
0.50
BSC
PIN 1
NOTCH
PIN 1
TOP MARK
0.200 REF
0.00 – 0.05
(UE12) DFN 0102
0.23 ± 0.05
3.30 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.70 ±0.05
(2 SIDES)2.24 ±0.05
0.50
BSC
0.58 ±0.05
3.40 ±0.05
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20
LT1739
1739fas, sn1739
PART NUMBER DESCRIPTION COMMENTS
LT1361 Dual 50MHz, 800V/µs Op Amp ±15V Operation, 1mV V
OS
, 1µA I
B
LT1794 Dual 500mA, 200MHz xDSL Line Driver ADSL CO Driver, Extended Output Swing, Low Power
LT1795 Dual 500mA, 50MHz Current Feedback Amplifier Shutdown/Current Set Function, ADSL CO Driver
LT1813 Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Low Noise, Low Power Differential Receiver, 4mA/Amplifier
LT1886 Dual 200mA, 700MHz Op Amp 12V Operation, 7mA/Amplifier, ADSL Modem Line Driver
LT1969 Dual 200mA, 700MHz Op Amp with Power Control 12V Operation, MSOP Package, ADSL Modem Line Driver
LT6300 Dual 500mA, 200MHz xDSL Line Driver ADSL CO Driver in SSOP Package
LINEAR TECHNOLOGY CORPORATION 2001
LT/TP 0602 1.5K REV A • PRINTED IN THE USA
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
Figure 18. ADSL Line Driver Using Active Termination
U
TYPICAL APPLICATIO
1739 F17
+
–
1/2
LT1739
–IN
–
+
1/2
LT1739
+IN
12V
SHDN
–12V
13.7Ω
24.9k
1:1.2*
182Ω
1000pF
182Ω
1k
1.65k
1.65k
1k
13.7Ω
SHDNREF
100Ω
LINE
*COILCRAFT X8502-A OR EQUIVALENT
1W DRIVER POWER DISSIPATION
1.15W POWER CONSUMPTION
•
•
