DG611/612/613 High-Speed, Low-Glitch D/CMOS Analog Switches Features Benefits Applications Fast Switching-- tON: 12 ns Low Charge Injection: 2 pC Wide Bandwidth: 500 MHz 5-V CMOS Logic Compatible Low rDS(on): 18 Low Quiescent Power : 1.2 nW Single Supply Operation Improved Data Throughput Minimal Switching Transients Improved System Performance Easily Interfaced Low Insertion Loss Minimal Power Consumption Fast Sample-and-Holds Synchronous Demodulators Pixel-Rate Video Switching Disk/Tape Drives DAC Deglitching Switched Capacitor Filters GaAs FET Drivers Satellite Receivers Description The DG611/612/613 feature high-speed low-capacitance lateral DMOS switches. Charge injection has been minimized to optimize performance in fast sample-and-hold applications. Each switch conducts equally well in both directions when on and blocks up to 16 Vp-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the DG611/612/613 are built on the Siliconix proprietary D/CMOS process. This process combines n-channel DMOS switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The DG611 and DG612 differ only in that they respond to opposite logic levels. The versatile DG613 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPDT, one DPDT. For additional information see Applications Note AN207. Functional Block Diagram and Pin Configuration DG611 DG611 IN1 IN2 D1 D2 S1 S2 V+ VL S3 V- GND S4 Dual-In-Line and SOIC D4 D3 IN4 IN3 V- V+ NC NC GND VL S1 S4 S2 S3 Four SPST Switches per Package Logic Truth Table DG611 DG612 0 ON OFF 1 OFF ON Logic "0" 1 V Logic "1" 4 V Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70057. Applications information may be obtained via FaxBack, request document #70605. Siliconix S-52880--Rev. E, 28-Apr-97 1 DG611/612/613 Functional Block Diagram and Pin Configuration (Cont'd) DG613 DG613 IN1 D1 IN2 D2 S1 V- S2 V+ GND S4 Dual-In-Line and SOIC D4 IN4 VL S3 D3 Four SPST Switches per Package V- V+ Logic SW2, SW3 NC SW1, SW4 NC 0 OFF ON GND 1 ON OFF S1 S4 Truth Table V L S3 IN3 S2 Logic "0" 1 V Logic "1" 4 V Ordering Information Temp Range Package Part Number DG611/612 16-Pin Plastic DIP -40 to 85 85_C C 16 Pin Narrow SOIC 16-Pin 16 Pin CerDIP 16-Pin -55 55 to 125_C LCC 20 LCC-20 DG611DJ DG612DJ DG611DY DG612DY DG611AK/883 DG612AK/883 DG611AZ/883 DG612AZ/883 DG613 Temp Range -40 to 85_C 85 C 55 to 125_C -55 Package Part Number 16-Pin Plastic DIP DG613DJ 16-Pin Narrow SOIC DG613DY 16-Pin CerDIP DG613AK/883 LCC-20 DG613AZ/883 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 21 V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 21 V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -19 V to 0.3 V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 V to (V+) + 1 V or 20 mA, whichever occurs first VINa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -1 V to (V+) + 1 V or 20 mA, whichever occurs first VS, VDa . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -0.3 V to (V-) + 16 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . 30 mA Current, S or D (Pulsed at 1 ms, 10% Duty Cycle) . . . . . . . . 100 mA Storage Temperature: 2 CerDIP . . . . . . . . . . . . . . . . -65 to 150_C Plastic . . . . . . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 16-Pin Narrow SOICd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW 16-Pin CerDIPe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 20-Pin LCCe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW/_C above 75_C d. Derate 7.6 mW/_C above 75_C e. Derate 12 mW/_C above 75_C Siliconix S-52880--Rev. E, 28-Apr-97 DG611/612/613 Recommended Operating Range V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 21 V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 0 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V to V+ VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VL VANALOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to (V+) - 5 V Specificationsa Test Conditions Unless Otherwise Specified Symbol V+ = 15 V, V- = -3 V VL = 5 V, VIN = 4 V, 1 Vf Tempb Analog Signal Rangee VANALOG V- = -5 V, V+ = 12 V Full Switch OnResistance rDS(on) Parameter Typc A Suffix D Suffix -55 to 125_C -40 to 85_C Mind Maxd Mind Maxd Unit Analog Switch Resistance Match Bet Ch. DrDS(on) IS = -1 mA, mA VD = 0 V -5 Room Full 18 Room 2 7 -5 45 60 7 45 60 Source Off Leakage IS(off) VS = 0 V, VD = 10 V Room Hot 0.001 -0.25 -20 0.25 20 -0.25 -20 0.25 20 Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Room Hot 0.001 -0.25 -20 0.25 20 -0.25 -20 0.25 20 Switch On Leakage Current ID(on) VS = VD = 0 V Room Hot 0.001 -0.4 -40 0.4 40 -0.4 -40 0.4 40 V W nA Digital Control Input Voltage High VIH Full Input Voltage Low VIL Full 4 Input Current IIN Room Hot 0.005 Input Capacitance CIN Room 5 4 1 -1 -20 1 20 1 -1 -20 1 20 V mA pF Dynamic Characteristics Off State Input Capacitance CS(off) VS = 0 V Room 3 Off State Output Capacitance CD(off) VD = 0 V Room 2 On State Input Capacitance CS(on) VS = VD = 0 V Room 10 Bandwidth BW RL = 50 W Room 500 TurnOn Timee tON 12 25 25 tOFF RL = 300 W, CL = 3 pF VS = 2 V See Test Circuit, Figure 2 Room TurnOff Timee Room 8 20 20 TurnOn Time tON Room Full 19 35 50 35 50 TurnOff Time tOFF RL = 300 W, CL = 75 pF VS = 2 V See Test Circuit, Figure 2 Room Full 16 25 35 25 35 Q CL = 1 nF, VS= 0 V Room 4 DQ CL = 1 nF, VS 3 V Room 3 4 4 Off Isolatione OIRR RIN = 50 W, RL = 50 W f = 5 MHz Room 74 Crosstalke XTALK RIN = 10 W, RL = 50 W f = 5 MHz Room 87 Charge Injectione Ch. Injection Changee, g Siliconix S-52880--Rev. E, 28-Apr-97 pF MHz ns pC dB 3 DG611/612/613 Specificationsa Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, V- = -3 V VL = 5 V, VIN = 4 V, 1 Vf Tempb Typc A Suffix D Suffix -55 to 125_C -40 to 85_C Mind Maxd Mind Maxd Unit Power Supplies Positive Supply Curent I+ Room Full 0.005 Negative Supply Current I- Room Full -0.005 Logic Supply Current IL Room Full 0.005 Room Full -0.005 Ground Current VIN = 0 V or 5 V IGND 1 5 -1 -5 1 5 -1 -5 1 5 -1 -5 1 5 mA -1 -5 Specificationsa for Unipolar Supplies Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, V- = -3 V VL = 5 V, VIN = 4 V, 1 Vf Tempb Typc A Suffix D Suffix -55 to 125_C -40 to 85_C Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee VANALOG Switch OnResistance rDS(on) Full 0 7 0 7 V W IS = -1 mA, VD = 1 V Room 25 60 60 RL = 300 W, CL = 3 pF, p VS = 2 V See Test Circuit, Figure 2 Room 15 30 30 Room 10 25 25 Dynamic Characteristics TurnOn Timee tON TurnOff Timee tOFF ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. DQ = Q at VS = 3 V - Q at VS = -3 V. 4 Siliconix S-52880--Rev. E, 28-Apr-97 DG611/612/613 Typical Characteristics rDS(on) vs. VD and Power Supply Voltages IS = -1 mA 350 V+ = 12 V V- = -5 V 300 V+ = 5 V V- = -5 V 250 V+ = 15 V V- = -3 V 200 150 100 50 0 -5 -4 rDS(on) vs. VD and Temperature 400 rDS(on) - Drain-Source On-Resistance ( rDS(on) - Drain-Source On-Resistance ( 400 V+ = 15 V V- = -3 V IS = -1 mA 350 300 250 200 150 25_C 100 12_C 50 -55_C 0 -2 0 2 4 6 8 VD - Drain Voltage (V) 10 12 -4 Leakage Current vs. Analog Voltage 2 4 6 8 VD - Drain Voltage (V) 10 12 Leakage Currents vs. Temperature V+ = 15 V V- = -3 V 2 1 nA I S(off) , I D(off) - Leakage (A) I S , I D - Leakage Current (pA) 0 10 nA 3 1 IS(off), ID(off) 0 -1 ID(on) -2 -3 100 pA ID(on) 10 pA IS(off), ID(off) 1 pA 0.1 pA -4 -2 0 2 4 6 8 VD or VS - Drain or Source Voltage (V) 10 -55 0 25 50 75 Temperature (_C) 100 125 24 22 V+ = 15 V V- = -3 V 5 -25 Switching Times vs. Temperature Input Switching Threshold vs. VL 6 20 tON 18 4 16 Time (ns) VIN - Logic Input Voltage (V) -2 3 2 14 tOFF 12 10 8 V+ = 15 V V- = -3 V RL = 300 CL = 10 pF 6 1 4 2 0 0 0 5 10 VL - Logic Supply Voltage (V) Siliconix S-52880--Rev. E, 28-Apr-97 15 -55 -35 -15 5 25 45 65 85 105 125 Temperature (_C) 5 DG611/612/613 Typical Characteristics (Cont'd) Charge Injection vs. Analog Voltage Crosstalk and Off Isolation vs. Frequency -120 20 V+ = 15 V V- = -3 V V+ = 15 V V- = -3 V -100 10 Crosstalk -80 (dB) Charge (pC) Qd 0 -60 Qs Off Isolation -10 -40 -20 -20 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 1 10 VANALOG - Analog Voltage (V) f - Frequency (MHz) -3 dB Bandwidth/Insertion Loss vs. Frequency 0 Supply Currents vs. Switching Frequency 6 RL = 50 V+ = 15 V V- = -3 V VL = 5 V CX = 0, 5 V 5 -4 4 3 Supply Current (mA) Insertion Loss (dB) 100 -8 -12 -3 dB Point -16 I+ 2 1 IL 0 -1 I- -2 -3 -20 -4 -24 -5 1 10 100 1000 1k f - Frequency (MHz) 100 k 100 k 1M 10 M f - Frequency (Hz) Schematic Diagram (Typical Channel) V+ VL S INX Input Logic Level Translator D Driver DMOS Switch V- Figure 1. 6 Siliconix S-52880--Rev. E, 28-Apr-97 DG611/612/613 Test Circuits +5 V +15 V VL S V+ D tr < 10 ns tf < 10 ns 5V 50% Logic Input 2 V VO 0V VS= "2 V IN GND V- RL 300 CL 90% Switch Output 20% 0V tON tOFF -3 V CL (includes fixture and stray capacitance) RL VO = VS RL + rDS(on) Figure 2. Switching Time C +5 V +15 V VL S V+ D VL S1 VS Rg = 50 Rg 5V GND +15 V C V+ D1 50 IN1 1 V, 4 V NC CL 1 nF IN Vg VO +5 V 1 V, 4 V V- S2 XTALK Isolation = 20 log C = RF bypass Figure 3. Charge Injection RL IN2 GND -3 V VO D2 V- C VS -3 V VO Figure 4. Crosstalk Applications High-Speed Sample-and-Hold Pixel-Rate Switch In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The Si581, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (See Figure 5.) Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the DG613. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (See Figure 6.) Siliconix S-52880--Rev. E, 28-Apr-97 GaAs FET Drivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on 0 V are applied to its gate via S1, whereas to turn it off, -8 V are applied via S2. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. 7 DG611/612/613 Applications (Cont'd) +5 V Input Buffer +12 V Output Buffer Analog Input S Si581 D + LF356 - 75 W 5 V Output to A/D IN 5 V Control 1/ 4 CHOLD 650 pF Polystyrene DG611 -5 V Figure 5. High-Speed Sample-and-Hold +5 V +12 V Output Buffer Background D + 75 W Si582 75 W Composite Output - 1/ Si584 2 250 W Titles 250 W 75 W 5 V Control 1/ 2 DG613 -5 V Figure 6. A Pixel-Rate Switch Creates Title Overlays +5 V VL S1 V+ D1 RF IN GaAs RF OUT IN1 1/ 2 DG613 S2 5V D2 IN2 GND V- -8 V Figure 7. A High-Speed GaAs FET Driver that Saves Power 8 Siliconix S-52880--Rev. E, 28-Apr-97